arch/powerpc/include/asm/ppc4xx-isram.h

   1
   2 /*
   3  * See file CREDITS for list of people who contributed to this
   4  * project.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #ifndef _PPC4xx_ISRAM_H_
  23 #define _PPC4xx_ISRAM_H_
  24
  25 /*
  26  * Internal SRAM
  27  */
  28 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  29 #define ISRAM0_DCR_BASE 0x380
  30 #else
  31 #define ISRAM0_DCR_BASE 0x020
  32 #endif
  33 #define ISRAM0_SB0CR    (ISRAM0_DCR_BASE+0x00)  /* SRAM bank config 0*/
  34 #define ISRAM0_SB1CR    (ISRAM0_DCR_BASE+0x01)  /* SRAM bank config 1*/
  35 #define ISRAM0_SB2CR    (ISRAM0_DCR_BASE+0x02)  /* SRAM bank config 2*/
  36 #define ISRAM0_SB3CR    (ISRAM0_DCR_BASE+0x03)  /* SRAM bank config 3*/
  37 #define ISRAM0_BEAR     (ISRAM0_DCR_BASE+0x04)  /* SRAM bus error addr reg */
  38 #define ISRAM0_BESR0    (ISRAM0_DCR_BASE+0x05)  /* SRAM bus error status reg 0 */
  39 #define ISRAM0_BESR1    (ISRAM0_DCR_BASE+0x06)  /* SRAM bus error status reg 1 */
  40 #define ISRAM0_PMEG     (ISRAM0_DCR_BASE+0x07)  /* SRAM power management */
  41 #define ISRAM0_CID      (ISRAM0_DCR_BASE+0x08)  /* SRAM bus core id reg */
  42 #define ISRAM0_REVID    (ISRAM0_DCR_BASE+0x09)  /* SRAM bus revision id reg */
  43 #define ISRAM0_DPC      (ISRAM0_DCR_BASE+0x0a)  /* SRAM data parity check reg */
  44
  45 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  46 #define ISRAM1_DCR_BASE 0x0B0
  47 #define ISRAM1_SB0CR    (ISRAM1_DCR_BASE+0x00)  /* SRAM1 bank config 0*/
  48 #define ISRAM1_BEAR     (ISRAM1_DCR_BASE+0x04)  /* SRAM1 bus error addr reg */
  49 #define ISRAM1_BESR0    (ISRAM1_DCR_BASE+0x05)  /* SRAM1 bus error status reg 0 */
  50 #define ISRAM1_BESR1    (ISRAM1_DCR_BASE+0x06)  /* SRAM1 bus error status reg 1 */
  51 #define ISRAM1_PMEG     (ISRAM1_DCR_BASE+0x07)  /* SRAM1 power management */
  52 #define ISRAM1_CID      (ISRAM1_DCR_BASE+0x08)  /* SRAM1 bus core id reg */
  53 #define ISRAM1_REVID    (ISRAM1_DCR_BASE+0x09)  /* SRAM1 bus revision id reg */
  54 #define ISRAM1_DPC      (ISRAM1_DCR_BASE+0x0a)  /* SRAM1 data parity check reg */
  55 #endif /* CONFIG_460EX || CONFIG_460GT */
  56
  57 /*
  58  * L2 Cache
  59  */
  60 #if defined (CONFIG_440GX) || \
  61     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  62     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  63     defined(CONFIG_460SX)
  64 #define L2_CACHE_BASE   0x030
  65 #define L2_CACHE_CFG    (L2_CACHE_BASE+0x00)    /* L2 Cache Config      */
  66 #define L2_CACHE_CMD    (L2_CACHE_BASE+0x01)    /* L2 Cache Command     */
  67 #define L2_CACHE_ADDR   (L2_CACHE_BASE+0x02)    /* L2 Cache Address     */
  68 #define L2_CACHE_DATA   (L2_CACHE_BASE+0x03)    /* L2 Cache Data        */
  69 #define L2_CACHE_STAT   (L2_CACHE_BASE+0x04)    /* L2 Cache Status      */
  70 #define L2_CACHE_CVER   (L2_CACHE_BASE+0x05)    /* L2 Cache Revision ID */
  71 #define L2_CACHE_SNP0   (L2_CACHE_BASE+0x06)    /* L2 Cache Snoop reg 0 */
  72 #define L2_CACHE_SNP1   (L2_CACHE_BASE+0x07)    /* L2 Cache Snoop reg 1 */
  73 #endif /* CONFIG_440GX */
  74
  75 #endif /* _PPC4xx_ISRAM_H_ */