arch/powerpc/include/asm/ppc4xx.h

   1 /*----------------------------------------------------------------------------+
   2 |       This source code is dual-licensed.  You may use it under the terms of
   3 |       the GNU General Public License version 2, or under the license below.
   4 |
   5 |       This source code has been made available to you by IBM on an AS-IS
   6 |       basis.  Anyone receiving this source is licensed under IBM
   7 |       copyrights to use it in any way he or she deems fit, including
   8 |       copying it, modifying it, compiling it, and redistributing it either
   9 |       with or without modifications.  No license under IBM patents or
  10 |       patent applications is to be implied by the copyright license.
  11 |
  12 |       Any user of this software should understand that IBM cannot provide
  13 |       technical support for this software and will not be responsible for
  14 |       any consequences resulting from the use of this software.
  15 |
  16 |       Any person who transfers this source code or any derivative work
  17 |       must include the IBM copyright notice, this paragraph, and the
  18 |       preceding two paragraphs in the transferred software.
  19 |
  20 |       COPYRIGHT   I B M   CORPORATION 1999
  21 |       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  22 +----------------------------------------------------------------------------*/
  23
  24 #ifndef __PPC4XX_H__
  25 #define __PPC4XX_H__
  26
  27 /*
  28  * Include SoC specific headers
  29  */
  30 #if defined(CONFIG_405CR)
  31 #include <asm/ppc405cr.h>
  32 #endif
  33
  34 #if defined(CONFIG_405EP)
  35 #include <asm/ppc405ep.h>
  36 #endif
  37
  38 #if defined(CONFIG_405EX)
  39 #include <asm/ppc405ex.h>
  40 #endif
  41
  42 #if defined(CONFIG_405EZ)
  43 #include <asm/ppc405ez.h>
  44 #endif
  45
  46 #if defined(CONFIG_405GP)
  47 #include <asm/ppc405gp.h>
  48 #endif
  49
  50 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
  51 #include <asm/ppc440ep_gr.h>
  52 #endif
  53
  54 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  55 #include <asm/ppc440epx_grx.h>
  56 #endif
  57
  58 #if defined(CONFIG_440GP)
  59 #include <asm/ppc440gp.h>
  60 #endif
  61
  62 #if defined(CONFIG_440GX)
  63 #include <asm/ppc440gx.h>
  64 #endif
  65
  66 #if defined(CONFIG_440SP)
  67 #include <asm/ppc440sp.h>
  68 #endif
  69
  70 #if defined(CONFIG_440SPE)
  71 #include <asm/ppc440spe.h>
  72 #endif
  73
  74 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  75 #include <asm/ppc460ex_gt.h>
  76 #endif
  77
  78 #if defined(CONFIG_460SX)
  79 #include <asm/ppc460sx.h>
  80 #endif
  81
  82 /*
  83  * Configure which SDRAM/DDR/DDR2 controller is equipped
  84  */
  85 // test-only: what to do with these???
  86 #if defined(CONFIG_AP1000) || defined(CONFIG_ML2)
  87 #define CONFIG_SDRAM_PPC4xx_IBM_SDRAM   /* IBM SDRAM controller */
  88 #endif
  89
  90 /*
  91  * Common registers for all SoC's
  92  */
  93 /* DCR registers */
  94 #define PLB3A0_ACR      0x0077
  95 #define PLB4A0_ACR      0x0081
  96 #define PLB4A1_ACR      0x0089
  97
  98 /* CPR register declarations */
  99
 100 #define PLB4Ax_ACR_PPM_MASK             0xf0000000
 101 #define PLB4Ax_ACR_PPM_FIXED            0x00000000
 102 #define PLB4Ax_ACR_PPM_FAIR             0xd0000000
 103 #define PLB4Ax_ACR_HBU_MASK             0x08000000
 104 #define PLB4Ax_ACR_HBU_DISABLED         0x00000000
 105 #define PLB4Ax_ACR_HBU_ENABLED          0x08000000
 106 #define PLB4Ax_ACR_RDP_MASK             0x06000000
 107 #define PLB4Ax_ACR_RDP_DISABLED         0x00000000
 108 #define PLB4Ax_ACR_RDP_2DEEP            0x02000000
 109 #define PLB4Ax_ACR_RDP_3DEEP            0x04000000
 110 #define PLB4Ax_ACR_RDP_4DEEP            0x06000000
 111 #define PLB4Ax_ACR_WRP_MASK             0x01000000
 112 #define PLB4Ax_ACR_WRP_DISABLED         0x00000000
 113 #define PLB4Ax_ACR_WRP_2DEEP            0x01000000
 114
 115 /*
 116  * External Bus Controller
 117  */
 118 /* Values for EBC0_CFGADDR register - indirect addressing of these regs */
 119 #define PB0CR           0x00    /* periph bank 0 config reg             */
 120 #define PB1CR           0x01    /* periph bank 1 config reg             */
 121 #define PB2CR           0x02    /* periph bank 2 config reg             */
 122 #define PB3CR           0x03    /* periph bank 3 config reg             */
 123 #define PB4CR           0x04    /* periph bank 4 config reg             */
 124 #define PB5CR           0x05    /* periph bank 5 config reg             */
 125 #define PB6CR           0x06    /* periph bank 6 config reg             */
 126 #define PB7CR           0x07    /* periph bank 7 config reg             */
 127 #define PB0AP           0x10    /* periph bank 0 access parameters      */
 128 #define PB1AP           0x11    /* periph bank 1 access parameters      */
 129 #define PB2AP           0x12    /* periph bank 2 access parameters      */
 130 #define PB3AP           0x13    /* periph bank 3 access parameters      */
 131 #define PB4AP           0x14    /* periph bank 4 access parameters      */
 132 #define PB5AP           0x15    /* periph bank 5 access parameters      */
 133 #define PB6AP           0x16    /* periph bank 6 access parameters      */
 134 #define PB7AP           0x17    /* periph bank 7 access parameters      */
 135 #define PBEAR           0x20    /* periph bus error addr reg            */
 136 #define PBESR0          0x21    /* periph bus error status reg 0        */
 137 #define PBESR1          0x22    /* periph bus error status reg 1        */
 138 #define EBC0_CFG        0x23    /* external bus configuration reg       */
 139
 140 /*
 141  * GPIO macro register defines
 142  */
 143 /* todo: merge with gpio.h header */
 144 #define GPIO_BASE               GPIO0_BASE
 145
 146 #define GPIO0_OR                (GPIO0_BASE + 0x0)
 147 #define GPIO0_TCR               (GPIO0_BASE + 0x4)
 148 #define GPIO0_OSRL              (GPIO0_BASE + 0x8)
 149 #define GPIO0_OSRH              (GPIO0_BASE + 0xC)
 150 #define GPIO0_TSRL              (GPIO0_BASE + 0x10)
 151 #define GPIO0_TSRH              (GPIO0_BASE + 0x14)
 152 #define GPIO0_ODR               (GPIO0_BASE + 0x18)
 153 #define GPIO0_IR                (GPIO0_BASE + 0x1C)
 154 #define GPIO0_RR1               (GPIO0_BASE + 0x20)
 155 #define GPIO0_RR2               (GPIO0_BASE + 0x24)
 156 #define GPIO0_RR3               (GPIO0_BASE + 0x28)
 157 #define GPIO0_ISR1L             (GPIO0_BASE + 0x30)
 158 #define GPIO0_ISR1H             (GPIO0_BASE + 0x34)
 159 #define GPIO0_ISR2L             (GPIO0_BASE + 0x38)
 160 #define GPIO0_ISR2H             (GPIO0_BASE + 0x3C)
 161 #define GPIO0_ISR3L             (GPIO0_BASE + 0x40)
 162 #define GPIO0_ISR3H             (GPIO0_BASE + 0x44)
 163
 164 #define GPIO1_OR                (GPIO1_BASE + 0x0)
 165 #define GPIO1_TCR               (GPIO1_BASE + 0x4)
 166 #define GPIO1_OSRL              (GPIO1_BASE + 0x8)
 167 #define GPIO1_OSRH              (GPIO1_BASE + 0xC)
 168 #define GPIO1_TSRL              (GPIO1_BASE + 0x10)
 169 #define GPIO1_TSRH              (GPIO1_BASE + 0x14)
 170 #define GPIO1_ODR               (GPIO1_BASE + 0x18)
 171 #define GPIO1_IR                (GPIO1_BASE + 0x1C)
 172 #define GPIO1_RR1               (GPIO1_BASE + 0x20)
 173 #define GPIO1_RR2               (GPIO1_BASE + 0x24)
 174 #define GPIO1_RR3               (GPIO1_BASE + 0x28)
 175 #define GPIO1_ISR1L             (GPIO1_BASE + 0x30)
 176 #define GPIO1_ISR1H             (GPIO1_BASE + 0x34)
 177 #define GPIO1_ISR2L             (GPIO1_BASE + 0x38)
 178 #define GPIO1_ISR2H             (GPIO1_BASE + 0x3C)
 179 #define GPIO1_ISR3L             (GPIO1_BASE + 0x40)
 180 #define GPIO1_ISR3H             (GPIO1_BASE + 0x44)
 181
 182 /* General Purpose Timer (GPT) Register Offsets */
 183 #define GPT0_TBC                0x00000000
 184 #define GPT0_IM                 0x00000018
 185 #define GPT0_ISS                0x0000001C
 186 #define GPT0_ISC                0x00000020
 187 #define GPT0_IE                 0x00000024
 188 #define GPT0_COMP0              0x00000080
 189 #define GPT0_COMP1              0x00000084
 190 #define GPT0_COMP2              0x00000088
 191 #define GPT0_COMP3              0x0000008C
 192 #define GPT0_COMP4              0x00000090
 193 #define GPT0_COMP5              0x00000094
 194 #define GPT0_COMP6              0x00000098
 195 #define GPT0_MASK0              0x000000C0
 196 #define GPT0_MASK1              0x000000C4
 197 #define GPT0_MASK2              0x000000C8
 198 #define GPT0_MASK3              0x000000CC
 199 #define GPT0_MASK4              0x000000D0
 200 #define GPT0_MASK5              0x000000D4
 201 #define GPT0_MASK6              0x000000D8
 202 #define GPT0_DCT0               0x00000110
 203 #define GPT0_DCIS               0x0000011C
 204
 205 #if 0 // test-only
 206 /*
 207  * All PPC4xx share the same NS16550 UART(s). Only base addresses
 208  * may differ. We define here the integration of the common NS16550
 209  * driver for all PPC4xx SoC's. The board config header must specify
 210  * on which UART the console should be located via CONFIG_CONS_INDEX.
 211  */
 212 #if 0 /* test-only */
 213 #define CONFIG_SERIAL_MULTI
 214 #endif
 215 #define CONFIG_SYS_NS16550
 216 #define CONFIG_SYS_NS16550_SERIAL
 217 #define CONFIG_SYS_NS16550_REG_SIZE     1
 218 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 219 #endif
 220
 221 #if defined(CONFIG_440)
 222 #include <asm/ppc440.h>
 223 #else
 224 #include <asm/ppc405.h>
 225 #endif
 226
 227 #include <asm/ppc4xx-sdram.h>
 228 #include <asm/ppc4xx-ebc.h>
 229 #if !defined(CONFIG_XILINX_440)
 230 #include <asm/ppc4xx-uic.h>
 231 #endif
 232
 233 /*
 234  * Macro for generating register field mnemonics
 235  */
 236 #define PPC_REG_BITS            32
 237 #define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
 238
 239 /*
 240  * Elide casts when assembling register mnemonics
 241  */
 242 #ifndef __ASSEMBLY__
 243 #define static_cast(type, val)  (type)(val)
 244 #else
 245 #define static_cast(type, val)  (val)
 246 #endif
 247
 248 /*
 249  * Common stuff for 4xx (405 and 440)
 250  */
 251
 252 #define EXC_OFF_SYS_RESET       0x0100  /* System reset                 */
 253 #define _START_OFFSET           (EXC_OFF_SYS_RESET + 0x2000)
 254
 255 #define RESET_VECTOR    0xfffffffc
 256 #define CACHELINE_MASK  (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for
 257                                                 cache line aligned data. */
 258
 259 #define CPR0_DCR_BASE   0x0C
 260 #define CPR0_CFGADDR    (CPR0_DCR_BASE + 0x0)
 261 #define CPR0_CFGDATA    (CPR0_DCR_BASE + 0x1)
 262
 263 #define SDR_DCR_BASE    0x0E
 264 #define SDR0_CFGADDR    (SDR_DCR_BASE + 0x0)
 265 #define SDR0_CFGDATA    (SDR_DCR_BASE + 0x1)
 266
 267 #define SDRAM_DCR_BASE  0x10
 268 #define SDRAM0_CFGADDR  (SDRAM_DCR_BASE + 0x0)
 269 #define SDRAM0_CFGDATA  (SDRAM_DCR_BASE + 0x1)
 270
 271 #define EBC_DCR_BASE    0x12
 272 #define EBC0_CFGADDR    (EBC_DCR_BASE + 0x0)
 273 #define EBC0_CFGDATA    (EBC_DCR_BASE + 0x1)
 274
 275 /*
 276  * Macros for indirect DCR access
 277  */
 278 #define mtcpr(reg, d)   \
 279   do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0)
 280 #define mfcpr(reg, d)   \
 281   do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0)
 282
 283 #define mtebc(reg, d)   \
 284   do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0)
 285 #define mfebc(reg, d)   \
 286   do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0)
 287
 288 #define mtsdram(reg, d) \
 289   do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
 290 #define mfsdram(reg, d) \
 291   do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
 292
 293 #define mtsdr(reg, d)   \
 294   do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0)
 295 #define mfsdr(reg, d)   \
 296   do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0)
 297
 298 #ifndef __ASSEMBLY__
 299
 300 typedef struct
 301 {
 302         unsigned long freqDDR;
 303         unsigned long freqEBC;
 304         unsigned long freqOPB;
 305         unsigned long freqPCI;
 306         unsigned long freqPLB;
 307         unsigned long freqTmrClk;
 308         unsigned long freqUART;
 309         unsigned long freqProcessor;
 310         unsigned long freqVCOHz;
 311         unsigned long freqVCOMhz;       /* in MHz                          */
 312         unsigned long pciClkSync;       /* PCI clock is synchronous        */
 313         unsigned long pciIntArbEn;      /* Internal PCI arbiter is enabled */
 314         unsigned long pllExtBusDiv;
 315         unsigned long pllFbkDiv;
 316         unsigned long pllFwdDiv;
 317         unsigned long pllFwdDivA;
 318         unsigned long pllFwdDivB;
 319         unsigned long pllOpbDiv;
 320         unsigned long pllPciDiv;
 321         unsigned long pllPlbDiv;
 322 } PPC4xx_SYS_INFO;
 323
 324 static inline u32 get_mcsr(void)
 325 {
 326         u32 val;
 327
 328         asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
 329         return val;
 330 }
 331
 332 static inline void set_mcsr(u32 val)
 333 {
 334         asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
 335 }
 336
 337 int ppc4xx_pci_sync_clock_config(u32 async);
 338
 339 #endif  /* __ASSEMBLY__ */
 340
 341 /* for multi-cpu support */
 342 #define NA_OR_UNKNOWN_CPU       -1
 343
 344 #endif  /* __PPC4XX_H__ */