arch/powerpc/include/asm/ppc4xx.h

   1 /*----------------------------------------------------------------------------+
   2 |       This source code is dual-licensed.  You may use it under the terms of
   3 |       the GNU General Public License version 2, or under the license below.
   4 |
   5 |       This source code has been made available to you by IBM on an AS-IS
   6 |       basis.  Anyone receiving this source is licensed under IBM
   7 |       copyrights to use it in any way he or she deems fit, including
   8 |       copying it, modifying it, compiling it, and redistributing it either
   9 |       with or without modifications.  No license under IBM patents or
  10 |       patent applications is to be implied by the copyright license.
  11 |
  12 |       Any user of this software should understand that IBM cannot provide
  13 |       technical support for this software and will not be responsible for
  14 |       any consequences resulting from the use of this software.
  15 |
  16 |       Any person who transfers this source code or any derivative work
  17 |       must include the IBM copyright notice, this paragraph, and the
  18 |       preceding two paragraphs in the transferred software.
  19 |
  20 |       COPYRIGHT   I B M   CORPORATION 1999
  21 |       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  22 +----------------------------------------------------------------------------*/
  23
  24 #ifndef __PPC4XX_H__
  25 #define __PPC4XX_H__
  26
  27 /*
  28  * Include SoC specific headers
  29  */
  30 #if defined(CONFIG_405CR)
  31 #include <asm/ppc405cr.h>
  32 #endif
  33
  34 #if defined(CONFIG_405EP)
  35 #include <asm/ppc405ep.h>
  36 #endif
  37
  38 #if defined(CONFIG_405EX)
  39 #include <asm/ppc405ex.h>
  40 #endif
  41
  42 #if defined(CONFIG_405EZ)
  43 #include <asm/ppc405ez.h>
  44 #endif
  45
  46 #if defined(CONFIG_405GP)
  47 #include <asm/ppc405gp.h>
  48 #endif
  49
  50 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
  51 #include <asm/ppc440ep_gr.h>
  52 #endif
  53
  54 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  55 #include <asm/ppc440epx_grx.h>
  56 #endif
  57
  58 #if defined(CONFIG_440GP)
  59 #include <asm/ppc440gp.h>
  60 #endif
  61
  62 #if defined(CONFIG_440GX)
  63 #include <asm/ppc440gx.h>
  64 #endif
  65
  66 #if defined(CONFIG_440SP)
  67 #include <asm/ppc440sp.h>
  68 #endif
  69
  70 #if defined(CONFIG_440SPE)
  71 #include <asm/ppc440spe.h>
  72 #endif
  73
  74 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  75 #include <asm/ppc460ex_gt.h>
  76 #endif
  77
  78 #if defined(CONFIG_460SX)
  79 #include <asm/ppc460sx.h>
  80 #endif
  81
  82 #if defined(CONFIG_APM821XX)
  83 #include <asm/apm821xx.h>
  84 #endif
  85
  86 /*
  87  * Configure which SDRAM/DDR/DDR2 controller is equipped
  88  */
  89 #if defined(CONFIG_AP1000) || defined(CONFIG_ML2)
  90 #define CONFIG_SDRAM_PPC4xx_IBM_SDRAM   /* IBM SDRAM controller */
  91 #endif
  92
  93 /*
  94  * Common registers for all SoC's
  95  */
  96 /* DCR registers */
  97 #define PLB3A0_ACR      0x0077
  98 #define PLB4A0_ACR      0x0081
  99 #define PLB4A1_ACR      0x0089
 100
 101 /* CPR register declarations */
 102
 103 #define PLB4Ax_ACR_PPM_MASK             0xf0000000
 104 #define PLB4Ax_ACR_PPM_FIXED            0x00000000
 105 #define PLB4Ax_ACR_PPM_FAIR             0xd0000000
 106 #define PLB4Ax_ACR_HBU_MASK             0x08000000
 107 #define PLB4Ax_ACR_HBU_DISABLED         0x00000000
 108 #define PLB4Ax_ACR_HBU_ENABLED          0x08000000
 109 #define PLB4Ax_ACR_RDP_MASK             0x06000000
 110 #define PLB4Ax_ACR_RDP_DISABLED         0x00000000
 111 #define PLB4Ax_ACR_RDP_2DEEP            0x02000000
 112 #define PLB4Ax_ACR_RDP_3DEEP            0x04000000
 113 #define PLB4Ax_ACR_RDP_4DEEP            0x06000000
 114 #define PLB4Ax_ACR_WRP_MASK             0x01000000
 115 #define PLB4Ax_ACR_WRP_DISABLED         0x00000000
 116 #define PLB4Ax_ACR_WRP_2DEEP            0x01000000
 117
 118 /*
 119  * External Bus Controller
 120  */
 121 /* Values for EBC0_CFGADDR register - indirect addressing of these regs */
 122 #define PB0CR           0x00    /* periph bank 0 config reg             */
 123 #define PB1CR           0x01    /* periph bank 1 config reg             */
 124 #define PB2CR           0x02    /* periph bank 2 config reg             */
 125 #define PB3CR           0x03    /* periph bank 3 config reg             */
 126 #define PB4CR           0x04    /* periph bank 4 config reg             */
 127 #define PB5CR           0x05    /* periph bank 5 config reg             */
 128 #define PB6CR           0x06    /* periph bank 6 config reg             */
 129 #define PB7CR           0x07    /* periph bank 7 config reg             */
 130 #define PB0AP           0x10    /* periph bank 0 access parameters      */
 131 #define PB1AP           0x11    /* periph bank 1 access parameters      */
 132 #define PB2AP           0x12    /* periph bank 2 access parameters      */
 133 #define PB3AP           0x13    /* periph bank 3 access parameters      */
 134 #define PB4AP           0x14    /* periph bank 4 access parameters      */
 135 #define PB5AP           0x15    /* periph bank 5 access parameters      */
 136 #define PB6AP           0x16    /* periph bank 6 access parameters      */
 137 #define PB7AP           0x17    /* periph bank 7 access parameters      */
 138 #define PBEAR           0x20    /* periph bus error addr reg            */
 139 #define PBESR0          0x21    /* periph bus error status reg 0        */
 140 #define PBESR1          0x22    /* periph bus error status reg 1        */
 141 #define EBC0_CFG        0x23    /* external bus configuration reg       */
 142
 143 /*
 144  * GPIO macro register defines
 145  */
 146 /* todo: merge with gpio.h header */
 147 #define GPIO_BASE               GPIO0_BASE
 148
 149 #define GPIO0_OR                (GPIO0_BASE + 0x0)
 150 #define GPIO0_TCR               (GPIO0_BASE + 0x4)
 151 #define GPIO0_OSRL              (GPIO0_BASE + 0x8)
 152 #define GPIO0_OSRH              (GPIO0_BASE + 0xC)
 153 #define GPIO0_TSRL              (GPIO0_BASE + 0x10)
 154 #define GPIO0_TSRH              (GPIO0_BASE + 0x14)
 155 #define GPIO0_ODR               (GPIO0_BASE + 0x18)
 156 #define GPIO0_IR                (GPIO0_BASE + 0x1C)
 157 #define GPIO0_RR1               (GPIO0_BASE + 0x20)
 158 #define GPIO0_RR2               (GPIO0_BASE + 0x24)
 159 #define GPIO0_RR3               (GPIO0_BASE + 0x28)
 160 #define GPIO0_ISR1L             (GPIO0_BASE + 0x30)
 161 #define GPIO0_ISR1H             (GPIO0_BASE + 0x34)
 162 #define GPIO0_ISR2L             (GPIO0_BASE + 0x38)
 163 #define GPIO0_ISR2H             (GPIO0_BASE + 0x3C)
 164 #define GPIO0_ISR3L             (GPIO0_BASE + 0x40)
 165 #define GPIO0_ISR3H             (GPIO0_BASE + 0x44)
 166
 167 #define GPIO1_OR                (GPIO1_BASE + 0x0)
 168 #define GPIO1_TCR               (GPIO1_BASE + 0x4)
 169 #define GPIO1_OSRL              (GPIO1_BASE + 0x8)
 170 #define GPIO1_OSRH              (GPIO1_BASE + 0xC)
 171 #define GPIO1_TSRL              (GPIO1_BASE + 0x10)
 172 #define GPIO1_TSRH              (GPIO1_BASE + 0x14)
 173 #define GPIO1_ODR               (GPIO1_BASE + 0x18)
 174 #define GPIO1_IR                (GPIO1_BASE + 0x1C)
 175 #define GPIO1_RR1               (GPIO1_BASE + 0x20)
 176 #define GPIO1_RR2               (GPIO1_BASE + 0x24)
 177 #define GPIO1_RR3               (GPIO1_BASE + 0x28)
 178 #define GPIO1_ISR1L             (GPIO1_BASE + 0x30)
 179 #define GPIO1_ISR1H             (GPIO1_BASE + 0x34)
 180 #define GPIO1_ISR2L             (GPIO1_BASE + 0x38)
 181 #define GPIO1_ISR2H             (GPIO1_BASE + 0x3C)
 182 #define GPIO1_ISR3L             (GPIO1_BASE + 0x40)
 183 #define GPIO1_ISR3H             (GPIO1_BASE + 0x44)
 184
 185 /* General Purpose Timer (GPT) Register Offsets */
 186 #define GPT0_TBC                0x00000000
 187 #define GPT0_IM                 0x00000018
 188 #define GPT0_ISS                0x0000001C
 189 #define GPT0_ISC                0x00000020
 190 #define GPT0_IE                 0x00000024
 191 #define GPT0_COMP0              0x00000080
 192 #define GPT0_COMP1              0x00000084
 193 #define GPT0_COMP2              0x00000088
 194 #define GPT0_COMP3              0x0000008C
 195 #define GPT0_COMP4              0x00000090
 196 #define GPT0_COMP5              0x00000094
 197 #define GPT0_COMP6              0x00000098
 198 #define GPT0_MASK0              0x000000C0
 199 #define GPT0_MASK1              0x000000C4
 200 #define GPT0_MASK2              0x000000C8
 201 #define GPT0_MASK3              0x000000CC
 202 #define GPT0_MASK4              0x000000D0
 203 #define GPT0_MASK5              0x000000D4
 204 #define GPT0_MASK6              0x000000D8
 205 #define GPT0_DCT0               0x00000110
 206 #define GPT0_DCIS               0x0000011C
 207
 208 #if defined(CONFIG_440)
 209 #include <asm/ppc440.h>
 210 #else
 211 #include <asm/ppc405.h>
 212 #endif
 213
 214 #include <asm/ppc4xx-sdram.h>
 215 #include <asm/ppc4xx-ebc.h>
 216 #if !defined(CONFIG_XILINX_440)
 217 #include <asm/ppc4xx-uic.h>
 218 #endif
 219
 220 /*
 221  * Macro for generating register field mnemonics
 222  */
 223 #define PPC_REG_BITS            32
 224 #define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
 225
 226 /*
 227  * Elide casts when assembling register mnemonics
 228  */
 229 #ifndef __ASSEMBLY__
 230 #define static_cast(type, val)  (type)(val)
 231 #else
 232 #define static_cast(type, val)  (val)
 233 #endif
 234
 235 /*
 236  * Common stuff for 4xx (405 and 440)
 237  */
 238
 239 #define EXC_OFF_SYS_RESET       0x0100  /* System reset                 */
 240 #define _START_OFFSET           (EXC_OFF_SYS_RESET + 0x2000)
 241
 242 #define RESET_VECTOR    0xfffffffc
 243 #define CACHELINE_MASK  (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for
 244                                                 cache line aligned data. */
 245
 246 #define CPR0_DCR_BASE   0x0C
 247 #define CPR0_CFGADDR    (CPR0_DCR_BASE + 0x0)
 248 #define CPR0_CFGDATA    (CPR0_DCR_BASE + 0x1)
 249
 250 #define SDR_DCR_BASE    0x0E
 251 #define SDR0_CFGADDR    (SDR_DCR_BASE + 0x0)
 252 #define SDR0_CFGDATA    (SDR_DCR_BASE + 0x1)
 253
 254 #define SDRAM_DCR_BASE  0x10
 255 #define SDRAM0_CFGADDR  (SDRAM_DCR_BASE + 0x0)
 256 #define SDRAM0_CFGDATA  (SDRAM_DCR_BASE + 0x1)
 257
 258 #define EBC_DCR_BASE    0x12
 259 #define EBC0_CFGADDR    (EBC_DCR_BASE + 0x0)
 260 #define EBC0_CFGDATA    (EBC_DCR_BASE + 0x1)
 261
 262 /*
 263  * Macros for indirect DCR access
 264  */
 265 #define mtcpr(reg, d)   \
 266   do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0)
 267 #define mfcpr(reg, d)   \
 268   do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0)
 269
 270 #define mtebc(reg, d)   \
 271   do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0)
 272 #define mfebc(reg, d)   \
 273   do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0)
 274
 275 #define mtsdram(reg, d) \
 276   do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
 277 #define mfsdram(reg, d) \
 278   do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
 279
 280 #define mtsdr(reg, d)   \
 281   do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0)
 282 #define mfsdr(reg, d)   \
 283   do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0)
 284
 285 #ifndef __ASSEMBLY__
 286
 287 typedef struct
 288 {
 289         unsigned long freqDDR;
 290         unsigned long freqEBC;
 291         unsigned long freqOPB;
 292         unsigned long freqPCI;
 293         unsigned long freqPLB;
 294         unsigned long freqTmrClk;
 295         unsigned long freqUART;
 296         unsigned long freqProcessor;
 297         unsigned long freqVCOHz;
 298         unsigned long freqVCOMhz;       /* in MHz                          */
 299         unsigned long pciClkSync;       /* PCI clock is synchronous        */
 300         unsigned long pciIntArbEn;      /* Internal PCI arbiter is enabled */
 301         unsigned long pllExtBusDiv;
 302         unsigned long pllFbkDiv;
 303         unsigned long pllFwdDiv;
 304         unsigned long pllFwdDivA;
 305         unsigned long pllFwdDivB;
 306         unsigned long pllOpbDiv;
 307         unsigned long pllPciDiv;
 308         unsigned long pllPlbDiv;
 309 } PPC4xx_SYS_INFO;
 310
 311 static inline u32 get_mcsr(void)
 312 {
 313         u32 val;
 314
 315         asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
 316         return val;
 317 }
 318
 319 static inline void set_mcsr(u32 val)
 320 {
 321         asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
 322 }
 323
 324 int ppc4xx_pci_sync_clock_config(u32 async);
 325
 326 #endif  /* __ASSEMBLY__ */
 327
 328 /* for multi-cpu support */
 329 #define NA_OR_UNKNOWN_CPU       -1
 330
 331 #endif  /* __PPC4XX_H__ */