arch/powerpc/include/asm/ppc4xx.h

   1 /*
   2  * SPDX-License-Identifier:     GPL-2.0 IBM-pibs
   3  */
   4
   5 #ifndef __PPC4XX_H__
   6 #define __PPC4XX_H__
   7
   8 /*
   9  * Include SoC specific headers
  10  */
  11 #if defined(CONFIG_405EP)
  12 #include <asm/ppc405ep.h>
  13 #endif
  14
  15 #if defined(CONFIG_405EX)
  16 #include <asm/ppc405ex.h>
  17 #endif
  18
  19 #if defined(CONFIG_405EZ)
  20 #include <asm/ppc405ez.h>
  21 #endif
  22
  23 #if defined(CONFIG_405GP)
  24 #include <asm/ppc405gp.h>
  25 #endif
  26
  27 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
  28 #include <asm/ppc440ep_gr.h>
  29 #endif
  30
  31 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  32 #include <asm/ppc440epx_grx.h>
  33 #endif
  34
  35 #if defined(CONFIG_440GP)
  36 #include <asm/ppc440gp.h>
  37 #endif
  38
  39 #if defined(CONFIG_440GX)
  40 #include <asm/ppc440gx.h>
  41 #endif
  42
  43 #if defined(CONFIG_440SP)
  44 #include <asm/ppc440sp.h>
  45 #endif
  46
  47 #if defined(CONFIG_440SPE)
  48 #include <asm/ppc440spe.h>
  49 #endif
  50
  51 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  52 #include <asm/ppc460ex_gt.h>
  53 #endif
  54
  55 #if defined(CONFIG_460SX)
  56 #include <asm/ppc460sx.h>
  57 #endif
  58
  59 #if defined(CONFIG_APM821XX)
  60 #include <asm/apm821xx.h>
  61 #endif
  62
  63 /*
  64  * Common registers for all SoC's
  65  */
  66 /* DCR registers */
  67 #define PLB3A0_ACR      0x0077
  68 #define PLB4A0_ACR      0x0081
  69 #define PLB4A1_ACR      0x0089
  70
  71 /* CPR register declarations */
  72
  73 #define PLB4Ax_ACR_PPM_MASK             0xf0000000
  74 #define PLB4Ax_ACR_PPM_FIXED            0x00000000
  75 #define PLB4Ax_ACR_PPM_FAIR             0xd0000000
  76 #define PLB4Ax_ACR_HBU_MASK             0x08000000
  77 #define PLB4Ax_ACR_HBU_DISABLED         0x00000000
  78 #define PLB4Ax_ACR_HBU_ENABLED          0x08000000
  79 #define PLB4Ax_ACR_RDP_MASK             0x06000000
  80 #define PLB4Ax_ACR_RDP_DISABLED         0x00000000
  81 #define PLB4Ax_ACR_RDP_2DEEP            0x02000000
  82 #define PLB4Ax_ACR_RDP_3DEEP            0x04000000
  83 #define PLB4Ax_ACR_RDP_4DEEP            0x06000000
  84 #define PLB4Ax_ACR_WRP_MASK             0x01000000
  85 #define PLB4Ax_ACR_WRP_DISABLED         0x00000000
  86 #define PLB4Ax_ACR_WRP_2DEEP            0x01000000
  87
  88 /*
  89  * External Bus Controller
  90  */
  91 /* Values for EBC0_CFGADDR register - indirect addressing of these regs */
  92 #define PB0CR           0x00    /* periph bank 0 config reg             */
  93 #define PB1CR           0x01    /* periph bank 1 config reg             */
  94 #define PB2CR           0x02    /* periph bank 2 config reg             */
  95 #define PB3CR           0x03    /* periph bank 3 config reg             */
  96 #define PB4CR           0x04    /* periph bank 4 config reg             */
  97 #define PB5CR           0x05    /* periph bank 5 config reg             */
  98 #define PB6CR           0x06    /* periph bank 6 config reg             */
  99 #define PB7CR           0x07    /* periph bank 7 config reg             */
 100 #define PB0AP           0x10    /* periph bank 0 access parameters      */
 101 #define PB1AP           0x11    /* periph bank 1 access parameters      */
 102 #define PB2AP           0x12    /* periph bank 2 access parameters      */
 103 #define PB3AP           0x13    /* periph bank 3 access parameters      */
 104 #define PB4AP           0x14    /* periph bank 4 access parameters      */
 105 #define PB5AP           0x15    /* periph bank 5 access parameters      */
 106 #define PB6AP           0x16    /* periph bank 6 access parameters      */
 107 #define PB7AP           0x17    /* periph bank 7 access parameters      */
 108 #define PBEAR           0x20    /* periph bus error addr reg            */
 109 #define PBESR0          0x21    /* periph bus error status reg 0        */
 110 #define PBESR1          0x22    /* periph bus error status reg 1        */
 111 #define EBC0_CFG        0x23    /* external bus configuration reg       */
 112
 113 /*
 114  * GPIO macro register defines
 115  */
 116 /* todo: merge with gpio.h header */
 117 #define GPIO_BASE               GPIO0_BASE
 118
 119 #define GPIO0_OR                (GPIO0_BASE + 0x0)
 120 #define GPIO0_TCR               (GPIO0_BASE + 0x4)
 121 #define GPIO0_OSRL              (GPIO0_BASE + 0x8)
 122 #define GPIO0_OSRH              (GPIO0_BASE + 0xC)
 123 #define GPIO0_TSRL              (GPIO0_BASE + 0x10)
 124 #define GPIO0_TSRH              (GPIO0_BASE + 0x14)
 125 #define GPIO0_ODR               (GPIO0_BASE + 0x18)
 126 #define GPIO0_IR                (GPIO0_BASE + 0x1C)
 127 #define GPIO0_RR1               (GPIO0_BASE + 0x20)
 128 #define GPIO0_RR2               (GPIO0_BASE + 0x24)
 129 #define GPIO0_RR3               (GPIO0_BASE + 0x28)
 130 #define GPIO0_ISR1L             (GPIO0_BASE + 0x30)
 131 #define GPIO0_ISR1H             (GPIO0_BASE + 0x34)
 132 #define GPIO0_ISR2L             (GPIO0_BASE + 0x38)
 133 #define GPIO0_ISR2H             (GPIO0_BASE + 0x3C)
 134 #define GPIO0_ISR3L             (GPIO0_BASE + 0x40)
 135 #define GPIO0_ISR3H             (GPIO0_BASE + 0x44)
 136
 137 #define GPIO1_OR                (GPIO1_BASE + 0x0)
 138 #define GPIO1_TCR               (GPIO1_BASE + 0x4)
 139 #define GPIO1_OSRL              (GPIO1_BASE + 0x8)
 140 #define GPIO1_OSRH              (GPIO1_BASE + 0xC)
 141 #define GPIO1_TSRL              (GPIO1_BASE + 0x10)
 142 #define GPIO1_TSRH              (GPIO1_BASE + 0x14)
 143 #define GPIO1_ODR               (GPIO1_BASE + 0x18)
 144 #define GPIO1_IR                (GPIO1_BASE + 0x1C)
 145 #define GPIO1_RR1               (GPIO1_BASE + 0x20)
 146 #define GPIO1_RR2               (GPIO1_BASE + 0x24)
 147 #define GPIO1_RR3               (GPIO1_BASE + 0x28)
 148 #define GPIO1_ISR1L             (GPIO1_BASE + 0x30)
 149 #define GPIO1_ISR1H             (GPIO1_BASE + 0x34)
 150 #define GPIO1_ISR2L             (GPIO1_BASE + 0x38)
 151 #define GPIO1_ISR2H             (GPIO1_BASE + 0x3C)
 152 #define GPIO1_ISR3L             (GPIO1_BASE + 0x40)
 153 #define GPIO1_ISR3H             (GPIO1_BASE + 0x44)
 154
 155 /* General Purpose Timer (GPT) Register Offsets */
 156 #define GPT0_TBC                0x00000000
 157 #define GPT0_IM                 0x00000018
 158 #define GPT0_ISS                0x0000001C
 159 #define GPT0_ISC                0x00000020
 160 #define GPT0_IE                 0x00000024
 161 #define GPT0_COMP0              0x00000080
 162 #define GPT0_COMP1              0x00000084
 163 #define GPT0_COMP2              0x00000088
 164 #define GPT0_COMP3              0x0000008C
 165 #define GPT0_COMP4              0x00000090
 166 #define GPT0_COMP5              0x00000094
 167 #define GPT0_COMP6              0x00000098
 168 #define GPT0_MASK0              0x000000C0
 169 #define GPT0_MASK1              0x000000C4
 170 #define GPT0_MASK2              0x000000C8
 171 #define GPT0_MASK3              0x000000CC
 172 #define GPT0_MASK4              0x000000D0
 173 #define GPT0_MASK5              0x000000D4
 174 #define GPT0_MASK6              0x000000D8
 175 #define GPT0_DCT0               0x00000110
 176 #define GPT0_DCIS               0x0000011C
 177
 178 #if defined(CONFIG_440)
 179 #include <asm/ppc440.h>
 180 #else
 181 #include <asm/ppc405.h>
 182 #endif
 183
 184 #include <asm/ppc4xx-sdram.h>
 185 #include <asm/ppc4xx-ebc.h>
 186 #if !defined(CONFIG_XILINX_440)
 187 #include <asm/ppc4xx-uic.h>
 188 #endif
 189
 190 /*
 191  * Macro for generating register field mnemonics
 192  */
 193 #define PPC_REG_BITS            32
 194 #define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
 195
 196 /*
 197  * Elide casts when assembling register mnemonics
 198  */
 199 #ifndef __ASSEMBLY__
 200 #define static_cast(type, val)  (type)(val)
 201 #else
 202 #define static_cast(type, val)  (val)
 203 #endif
 204
 205 /*
 206  * Common stuff for 4xx (405 and 440)
 207  */
 208
 209 #define EXC_OFF_SYS_RESET       0x0100  /* System reset                 */
 210 #define _START_OFFSET           (EXC_OFF_SYS_RESET + 0x2000)
 211
 212 #define RESET_VECTOR    0xfffffffc
 213 #define CACHELINE_MASK  (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for
 214                                                 cache line aligned data. */
 215
 216 #define CPR0_DCR_BASE   0x0C
 217 #define CPR0_CFGADDR    (CPR0_DCR_BASE + 0x0)
 218 #define CPR0_CFGDATA    (CPR0_DCR_BASE + 0x1)
 219
 220 #define SDR_DCR_BASE    0x0E
 221 #define SDR0_CFGADDR    (SDR_DCR_BASE + 0x0)
 222 #define SDR0_CFGDATA    (SDR_DCR_BASE + 0x1)
 223
 224 #define SDRAM_DCR_BASE  0x10
 225 #define SDRAM0_CFGADDR  (SDRAM_DCR_BASE + 0x0)
 226 #define SDRAM0_CFGDATA  (SDRAM_DCR_BASE + 0x1)
 227
 228 #define EBC_DCR_BASE    0x12
 229 #define EBC0_CFGADDR    (EBC_DCR_BASE + 0x0)
 230 #define EBC0_CFGDATA    (EBC_DCR_BASE + 0x1)
 231
 232 /*
 233  * Macros for indirect DCR access
 234  */
 235 #define mtcpr(reg, d)   \
 236   do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0)
 237 #define mfcpr(reg, d)   \
 238   do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0)
 239
 240 #define mtebc(reg, d)   \
 241   do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0)
 242 #define mfebc(reg, d)   \
 243   do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0)
 244
 245 #define mtsdram(reg, d) \
 246   do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
 247 #define mfsdram(reg, d) \
 248   do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
 249
 250 #define mtsdr(reg, d)   \
 251   do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0)
 252 #define mfsdr(reg, d)   \
 253   do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0)
 254
 255 #ifndef __ASSEMBLY__
 256
 257 typedef struct
 258 {
 259         unsigned long freqDDR;
 260         unsigned long freqEBC;
 261         unsigned long freqOPB;
 262         unsigned long freqPCI;
 263         unsigned long freqPLB;
 264         unsigned long freqTmrClk;
 265         unsigned long freqUART;
 266         unsigned long freqProcessor;
 267         unsigned long freqVCOHz;
 268         unsigned long freqVCOMhz;       /* in MHz                          */
 269         unsigned long pciClkSync;       /* PCI clock is synchronous        */
 270         unsigned long pciIntArbEn;      /* Internal PCI arbiter is enabled */
 271         unsigned long pllExtBusDiv;
 272         unsigned long pllFbkDiv;
 273         unsigned long pllFwdDiv;
 274         unsigned long pllFwdDivA;
 275         unsigned long pllFwdDivB;
 276         unsigned long pllOpbDiv;
 277         unsigned long pllPciDiv;
 278         unsigned long pllPlbDiv;
 279 } PPC4xx_SYS_INFO;
 280
 281 static inline u32 get_mcsr(void)
 282 {
 283         u32 val;
 284
 285         asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
 286         return val;
 287 }
 288
 289 static inline void set_mcsr(u32 val)
 290 {
 291         asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
 292 }
 293
 294 int ppc4xx_pci_sync_clock_config(u32 async);
 295
 296 #endif  /* __ASSEMBLY__ */
 297
 298 /* for multi-cpu support */
 299 #define NA_OR_UNKNOWN_CPU       -1
 300
 301 #endif  /* __PPC4XX_H__ */