arch/ppc/cpu/mpc824x/start.S

   1 /*
   2  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   3  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   4  *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /* U-Boot - Startup Code for PowerPC based Embedded Boards
  26  *
  27  *
  28  * The processor starts at 0x00000100 and the code is executed
  29  * from flash. The code is organized to be at an other address
  30  * in memory, but as long we don't jump around before relocating.
  31  * board_init lies at a quite high address and when the cpu has
  32  * jumped there, everything is ok.
  33  * This works because the cpu gives the FLASH (CS0) the whole
  34  * address space at startup, and board_init lies as a echo of
  35  * the flash somewhere up there in the memorymap.
  36  *
  37  * board_init will change CS0 to be positioned at the correct
  38  * address and (s)dram will be positioned at address 0
  39  */
  40 #include <config.h>
  41 #include <mpc824x.h>
  42 #include <timestamp.h>
  43 #include <version.h>
  44
  45 #define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
  46
  47 #include <ppc_asm.tmpl>
  48 #include <ppc_defs.h>
  49
  50 #include <asm/cache.h>
  51 #include <asm/mmu.h>
  52
  53 #ifndef CONFIG_IDENT_STRING
  54 #define CONFIG_IDENT_STRING ""
  55 #endif
  56
  57 /* We don't want the MMU yet.
  58 */
  59 #undef  MSR_KERNEL
  60 /* FP, Machine Check and Recoverable Interr. */
  61 #define MSR_KERNEL ( MSR_FP | MSR_ME | MSR_RI )
  62
  63 /*
  64  * Set up GOT: Global Offset Table
  65  *
  66  * Use r12 to access the GOT
  67  */
  68         START_GOT
  69         GOT_ENTRY(_GOT2_TABLE_)
  70         GOT_ENTRY(_FIXUP_TABLE_)
  71
  72         GOT_ENTRY(_start)
  73         GOT_ENTRY(_start_of_vectors)
  74         GOT_ENTRY(_end_of_vectors)
  75         GOT_ENTRY(transfer_to_handler)
  76
  77         GOT_ENTRY(__init_end)
  78         GOT_ENTRY(_end)
  79         GOT_ENTRY(__bss_start)
  80 #if defined(CONFIG_FADS)
  81         GOT_ENTRY(environment)
  82 #endif
  83         END_GOT
  84
  85 /*
  86  * r3 - 1st arg to board_init(): IMMP pointer
  87  * r4 - 2nd arg to board_init(): boot flag
  88  */
  89         .text
  90         .long   0x27051956              /* U-Boot Magic Number                  */
  91         .globl  version_string
  92 version_string:
  93         .ascii U_BOOT_VERSION
  94         .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
  95         .ascii CONFIG_IDENT_STRING, "\0"
  96
  97         . = EXC_OFF_SYS_RESET
  98         .globl  _start
  99 _start:
 100         li      r21, BOOTFLAG_COLD      /* Normal Power-On: Boot from FLASH     */
 101         b       boot_cold
 102
 103         . = EXC_OFF_SYS_RESET + 0x10
 104
 105         .globl  _start_warm
 106 _start_warm:
 107         li      r21, BOOTFLAG_WARM      /* Software reboot                      */
 108         b       boot_warm
 109
 110 boot_cold:
 111 boot_warm:
 112
 113         /* Initialize machine status; enable machine check interrupt            */
 114         /*----------------------------------------------------------------------*/
 115         li      r3, MSR_KERNEL          /* Set FP, ME, RI flags */
 116         mtmsr   r3
 117         mtspr   SRR1, r3                /* Make SRR1 match MSR */
 118
 119         addis   r0,0,0x0000             /* lets make sure that r0 is really 0 */
 120         mtspr   HID0, r0                /* disable I and D caches */
 121
 122         mfspr   r3, ICR                 /* clear Interrupt Cause Register */
 123
 124         mfmsr   r3                      /* turn off address translation */
 125         addis   r4,0,0xffff
 126         ori     r4,r4,0xffcf
 127         and     r3,r3,r4
 128         mtmsr   r3
 129         isync
 130         sync                            /* the MMU should be off... */
 131
 132
 133 in_flash:
 134 #if defined(CONFIG_BMW)
 135         bl early_init_f /* Must be ASM: no stack yet! */
 136 #endif
 137         /*
 138          * Setup BATs - cannot be done in C since we don't have a stack yet
 139          */
 140         bl      setup_bats
 141
 142         /* Enable MMU.
 143          */
 144         mfmsr   r3
 145         ori     r3, r3, (MSR_IR | MSR_DR)
 146         mtmsr   r3
 147 #if !defined(CONFIG_BMW)
 148         /* Enable and invalidate data cache.
 149          */
 150         mfspr   r3, HID0
 151         mr      r2, r3
 152         ori     r3, r3, HID0_DCE | HID0_DCI
 153         ori     r2, r2, HID0_DCE
 154         sync
 155         mtspr   HID0, r3
 156         mtspr   HID0, r2
 157         sync
 158
 159         /* Allocate Initial RAM in data cache.
 160          */
 161         lis     r3, CONFIG_SYS_INIT_RAM_ADDR@h
 162         ori     r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
 163         li      r2, 128
 164         mtctr   r2
 165 1:
 166         dcbz    r0, r3
 167         addi    r3, r3, 32
 168         bdnz    1b
 169
 170         /* Lock way0 in data cache.
 171          */
 172         mfspr   r3, 1011
 173         lis     r2, 0xffff
 174         ori     r2, r2, 0xff1f
 175         and     r3, r3, r2
 176         ori     r3, r3, 0x0080
 177         sync
 178         mtspr   1011, r3
 179 #endif /* !CONFIG_BMW */
 180         /*
 181          * Thisk the stack pointer *somewhere* sensible. Doesnt
 182          * matter much where as we'll move it when we relocate
 183          */
 184         lis     r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
 185         ori     r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
 186
 187         li      r0, 0                   /* Make room for stack frame header and */
 188         stwu    r0, -4(r1)              /* clear final stack frame so that      */
 189         stwu    r0, -4(r1)              /* stack backtraces terminate cleanly   */
 190
 191         /* let the C-code set up the rest                                       */
 192         /*                                                                      */
 193         /* Be careful to keep code relocatable !                                */
 194         /*----------------------------------------------------------------------*/
 195
 196         GET_GOT                 /* initialize GOT access                        */
 197
 198         /* r3: IMMR */
 199         bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
 200
 201         mr      r3, r21
 202         /* r3: BOOTFLAG */
 203         bl      board_init_f    /* run 1st part of board init code (from Flash) */
 204
 205
 206         .globl  _start_of_vectors
 207 _start_of_vectors:
 208
 209 /* Machine check */
 210         STD_EXCEPTION(EXC_OFF_MACH_CHCK, MachineCheck, MachineCheckException)
 211
 212 /* Data Storage exception.  "Never" generated on the 860. */
 213         STD_EXCEPTION(EXC_OFF_DATA_STOR, DataStorage, UnknownException)
 214
 215 /* Instruction Storage exception.  "Never" generated on the 860. */
 216         STD_EXCEPTION(EXC_OFF_INS_STOR, InstStorage, UnknownException)
 217
 218 /* External Interrupt exception. */
 219         STD_EXCEPTION(EXC_OFF_EXTERNAL, ExtInterrupt, external_interrupt)
 220
 221 /* Alignment exception. */
 222         . = EXC_OFF_ALIGN
 223 Alignment:
 224         EXCEPTION_PROLOG(SRR0, SRR1)
 225         mfspr   r4,DAR
 226         stw     r4,_DAR(r21)
 227         mfspr   r5,DSISR
 228         stw     r5,_DSISR(r21)
 229         addi    r3,r1,STACK_FRAME_OVERHEAD
 230         EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
 231
 232 /* Program check exception */
 233         . = EXC_OFF_PROGRAM
 234 ProgramCheck:
 235         EXCEPTION_PROLOG(SRR0, SRR1)
 236         addi    r3,r1,STACK_FRAME_OVERHEAD
 237         EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
 238                 MSR_KERNEL, COPY_EE)
 239
 240         /* No FPU on MPC8xx. This exception is not supposed to happen.
 241         */
 242         STD_EXCEPTION(EXC_OFF_FPUNAVAIL, FPUnavailable, UnknownException)
 243
 244         /* I guess we could implement decrementer, and may have
 245          * to someday for timekeeping.
 246          */
 247         STD_EXCEPTION(EXC_OFF_DECR, Decrementer, timer_interrupt)
 248         STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
 249         STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
 250         STD_EXCEPTION(0xc00, SystemCall, UnknownException)
 251
 252         STD_EXCEPTION(EXC_OFF_TRACE, SingleStep, UnknownException)
 253
 254         STD_EXCEPTION(EXC_OFF_FPUNASSIST, Trap_0e, UnknownException)
 255         STD_EXCEPTION(EXC_OFF_PMI, Trap_0f, UnknownException)
 256
 257         STD_EXCEPTION(EXC_OFF_ITME, InstructionTransMiss, UnknownException)
 258         STD_EXCEPTION(EXC_OFF_DLTME, DataLoadTransMiss, UnknownException)
 259         STD_EXCEPTION(EXC_OFF_DSTME, DataStoreTransMiss, UnknownException)
 260         STD_EXCEPTION(EXC_OFF_IABE, InstructionBreakpoint, DebugException)
 261         STD_EXCEPTION(EXC_OFF_SMIE, SysManageInt, UnknownException)
 262         STD_EXCEPTION(0x1500, Reserved5, UnknownException)
 263         STD_EXCEPTION(0x1600, Reserved6, UnknownException)
 264         STD_EXCEPTION(0x1700, Reserved7, UnknownException)
 265         STD_EXCEPTION(0x1800, Reserved8, UnknownException)
 266         STD_EXCEPTION(0x1900, Reserved9, UnknownException)
 267         STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
 268         STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
 269         STD_EXCEPTION(0x1c00, ReservedC, UnknownException)
 270         STD_EXCEPTION(0x1d00, ReservedD, UnknownException)
 271         STD_EXCEPTION(0x1e00, ReservedE, UnknownException)
 272         STD_EXCEPTION(0x1f00, ReservedF, UnknownException)
 273
 274         STD_EXCEPTION(EXC_OFF_RMTE, RunModeTrace, UnknownException)
 275
 276         .globl  _end_of_vectors
 277 _end_of_vectors:
 278
 279
 280         . = 0x3000
 281
 282 /*
 283  * This code finishes saving the registers to the exception frame
 284  * and jumps to the appropriate handler for the exception.
 285  * Register r21 is pointer into trap frame, r1 has new stack pointer.
 286  */
 287         .globl  transfer_to_handler
 288 transfer_to_handler:
 289         stw     r22,_NIP(r21)
 290         lis     r22,MSR_POW@h
 291         andc    r23,r23,r22
 292         stw     r23,_MSR(r21)
 293         SAVE_GPR(7, r21)
 294         SAVE_4GPRS(8, r21)
 295         SAVE_8GPRS(12, r21)
 296         SAVE_8GPRS(24, r21)
 297 #if 0
 298         andi.   r23,r23,MSR_PR
 299         mfspr   r23,SPRG3               /* if from user, fix up tss.regs */
 300         beq     2f
 301         addi    r24,r1,STACK_FRAME_OVERHEAD
 302         stw     r24,PT_REGS(r23)
 303 2:      addi    r2,r23,-TSS             /* set r2 to current */
 304         tovirt(r2,r2,r23)
 305 #endif
 306         mflr    r23
 307         andi.   r24,r23,0x3f00          /* get vector offset */
 308         stw     r24,TRAP(r21)
 309         li      r22,0
 310         stw     r22,RESULT(r21)
 311         mtspr   SPRG2,r22               /* r1 is now kernel sp */
 312 #if 0
 313         addi    r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */
 314         cmplw   0,r1,r2
 315         cmplw   1,r1,r24
 316         crand   1,1,4
 317         bgt     stack_ovf               /* if r2 < r1 < r2+TASK_STRUCT_SIZE */
 318 #endif
 319         lwz     r24,0(r23)              /* virtual address of handler */
 320         lwz     r23,4(r23)              /* where to go when done */
 321         mtspr   SRR0,r24
 322         ori     r20,r20,0x30            /* enable IR, DR */
 323         mtspr   SRR1,r20
 324         mtlr    r23
 325         SYNC
 326         rfi                             /* jump to handler, enable MMU */
 327
 328 int_return:
 329         mfmsr   r28             /* Disable interrupts */
 330         li      r4,0
 331         ori     r4,r4,MSR_EE
 332         andc    r28,r28,r4
 333         SYNC                    /* Some chip revs need this... */
 334         mtmsr   r28
 335         SYNC
 336         lwz     r2,_CTR(r1)
 337         lwz     r0,_LINK(r1)
 338         mtctr   r2
 339         mtlr    r0
 340         lwz     r2,_XER(r1)
 341         lwz     r0,_CCR(r1)
 342         mtspr   XER,r2
 343         mtcrf   0xFF,r0
 344         REST_10GPRS(3, r1)
 345         REST_10GPRS(13, r1)
 346         REST_8GPRS(23, r1)
 347         REST_GPR(31, r1)
 348         lwz     r2,_NIP(r1)     /* Restore environment */
 349         lwz     r0,_MSR(r1)
 350         mtspr   SRR0,r2
 351         mtspr   SRR1,r0
 352         lwz     r0,GPR0(r1)
 353         lwz     r2,GPR2(r1)
 354         lwz     r1,GPR1(r1)
 355         SYNC
 356         rfi
 357
 358 /* Cache functions.
 359 */
 360         .globl  icache_enable
 361 icache_enable:
 362         mfspr   r5,HID0         /* turn on the I cache. */
 363         ori     r5,r5,0x8800    /* Instruction cache only! */
 364         addis   r6,0,0xFFFF
 365         ori     r6,r6,0xF7FF
 366         and     r6,r5,r6        /* clear the invalidate bit */
 367         sync
 368         mtspr   HID0,r5
 369         mtspr   HID0,r6
 370         isync
 371         sync
 372         blr
 373
 374         .globl  icache_disable
 375 icache_disable:
 376         mfspr   r5,HID0
 377         addis   r6,0,0xFFFF
 378         ori     r6,r6,0x7FFF
 379         and     r5,r5,r6
 380         sync
 381         mtspr   HID0,r5
 382         isync
 383         sync
 384         blr
 385
 386         .globl  icache_status
 387 icache_status:
 388         mfspr   r3, HID0
 389         srwi    r3, r3, 15      /* >>15 & 1=> select bit 16 */
 390         andi.   r3, r3, 1
 391         blr
 392
 393         .globl  dcache_enable
 394 dcache_enable:
 395         mfspr   r5,HID0         /* turn on the D cache. */
 396         ori     r5,r5,0x4400    /* Data cache only! */
 397         mfspr   r4, PVR         /* read PVR */
 398         srawi   r3, r4, 16      /* shift off the least 16 bits */
 399         cmpi    0, 0, r3, 0xC   /* Check for Max pvr */
 400         bne     NotMax
 401         ori     r5,r5,0x0040    /* setting the DCFA bit, for Max rev 1 errata */
 402 NotMax:
 403         addis   r6,0,0xFFFF
 404         ori     r6,r6,0xFBFF
 405         and     r6,r5,r6        /* clear the invalidate bit */
 406         sync
 407         mtspr   HID0,r5
 408         mtspr   HID0,r6
 409         isync
 410         sync
 411         blr
 412
 413         .globl  dcache_disable
 414 dcache_disable:
 415         mfspr   r5,HID0
 416         addis   r6,0,0xFFFF
 417         ori     r6,r6,0xBFFF
 418         and     r5,r5,r6
 419         sync
 420         mtspr   HID0,r5
 421         isync
 422         sync
 423         blr
 424
 425         .globl  dcache_status
 426 dcache_status:
 427         mfspr   r3, HID0
 428         srwi    r3, r3, 14      /* >>14 & 1=> select bit 17 */
 429         andi.   r3, r3, 1
 430         blr
 431
 432         .globl  dc_read
 433 dc_read:
 434 /*TODO : who uses this, what should it do?
 435 */
 436         blr
 437
 438
 439         .globl get_pvr
 440 get_pvr:
 441         mfspr   r3, PVR
 442         blr
 443
 444
 445 /*------------------------------------------------------------------------------*/
 446
 447 /*
 448  * void relocate_code (addr_sp, gd, addr_moni)
 449  *
 450  * This "function" does not return, instead it continues in RAM
 451  * after relocating the monitor code.
 452  *
 453  * r3 = dest
 454  * r4 = src
 455  * r5 = length in bytes
 456  * r6 = cachelinesize
 457  */
 458         .globl  relocate_code
 459 relocate_code:
 460
 461         mr      r1,  r3         /* Set new stack pointer                */
 462         mr      r9,  r4         /* Save copy of Global Data pointer     */
 463         mr      r10, r5         /* Save copy of Destination Address     */
 464
 465         GET_GOT
 466         mr      r3,  r5                         /* Destination Address  */
 467 #ifdef CONFIG_SYS_RAMBOOT
 468         lis     r4, CONFIG_SYS_SDRAM_BASE@h             /* Source      Address  */
 469         ori     r4, r4, CONFIG_SYS_SDRAM_BASE@l
 470 #else
 471         lis     r4, CONFIG_SYS_MONITOR_BASE@h           /* Source      Address  */
 472         ori     r4, r4, CONFIG_SYS_MONITOR_BASE@l
 473 #endif
 474         lwz     r5, GOT(__init_end)
 475         sub     r5, r5, r4
 476         li      r6, CONFIG_SYS_CACHELINE_SIZE           /* Cache Line Size      */
 477
 478         /*
 479          * Fix GOT pointer:
 480          *
 481          * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
 482          *
 483          * Offset:
 484          */
 485         sub     r15, r10, r4
 486
 487         /* First our own GOT */
 488         add     r12, r12, r15
 489         /* the the one used by the C code */
 490         add     r30, r30, r15
 491
 492         /*
 493          * Now relocate code
 494          */
 495
 496         cmplw   cr1,r3,r4
 497         addi    r0,r5,3
 498         srwi.   r0,r0,2
 499         beq     cr1,4f          /* In place copy is not necessary       */
 500         beq     7f              /* Protect against 0 count              */
 501         mtctr   r0
 502         bge     cr1,2f
 503
 504         la      r8,-4(r4)
 505         la      r7,-4(r3)
 506 1:      lwzu    r0,4(r8)
 507         stwu    r0,4(r7)
 508         bdnz    1b
 509         b       4f
 510
 511 2:      slwi    r0,r0,2
 512         add     r8,r4,r0
 513         add     r7,r3,r0
 514 3:      lwzu    r0,-4(r8)
 515         stwu    r0,-4(r7)
 516         bdnz    3b
 517
 518 4:
 519 #if !defined(CONFIG_BMW)
 520 /* Unlock the data cache and invalidate locked area */
 521         xor     r0, r0, r0
 522         mtspr   1011, r0
 523         lis     r4, CONFIG_SYS_INIT_RAM_ADDR@h
 524         ori     r4, r4, CONFIG_SYS_INIT_RAM_ADDR@l
 525         li      r0, 128
 526         mtctr   r0
 527 41:
 528         dcbi    r0, r4
 529         addi    r4, r4, 32
 530         bdnz    41b
 531 #endif
 532
 533 /*
 534  * Now flush the cache: note that we must start from a cache aligned
 535  * address. Otherwise we might miss one cache line.
 536  */
 537         cmpwi   r6,0
 538         add     r5,r3,r5
 539         beq     7f              /* Always flush prefetch queue in any case */
 540         subi    r0,r6,1
 541         andc    r3,r3,r0
 542         mr      r4,r3
 543 5:      dcbst   0,r4
 544         add     r4,r4,r6
 545         cmplw   r4,r5
 546         blt     5b
 547         sync                    /* Wait for all dcbst to complete on bus */
 548         mr      r4,r3
 549 6:      icbi    0,r4
 550         add     r4,r4,r6
 551         cmplw   r4,r5
 552         blt     6b
 553 7:      sync                    /* Wait for all icbi to complete on bus */
 554         isync
 555
 556 /*
 557  * We are done. Do not return, instead branch to second part of board
 558  * initialization, now running from RAM.
 559  */
 560
 561         addi    r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
 562         mtlr    r0
 563         blr
 564
 565 in_ram:
 566
 567         /*
 568          * Relocation Function, r12 point to got2+0x8000
 569          *
 570          * Adjust got2 pointers, no need to check for 0, this code
 571          * already puts a few entries in the table.
 572          */
 573         li      r0,__got2_entries@sectoff@l
 574         la      r3,GOT(_GOT2_TABLE_)
 575         lwz     r11,GOT(_GOT2_TABLE_)
 576         mtctr   r0
 577         sub     r11,r3,r11
 578         addi    r3,r3,-4
 579 1:      lwzu    r0,4(r3)
 580         cmpwi   r0,0
 581         beq-    2f
 582         add     r0,r0,r11
 583         stw     r0,0(r3)
 584 2:      bdnz    1b
 585
 586         /*
 587          * Now adjust the fixups and the pointers to the fixups
 588          * in case we need to move ourselves again.
 589          */
 590         li      r0,__fixup_entries@sectoff@l
 591         lwz     r3,GOT(_FIXUP_TABLE_)
 592         cmpwi   r0,0
 593         mtctr   r0
 594         addi    r3,r3,-4
 595         beq     4f
 596 3:      lwzu    r4,4(r3)
 597         lwzux   r0,r4,r11
 598         add     r0,r0,r11
 599         stw     r10,0(r3)
 600         stw     r0,0(r4)
 601         bdnz    3b
 602 4:
 603 clear_bss:
 604         /*
 605          * Now clear BSS segment
 606          */
 607         lwz     r3,GOT(__bss_start)
 608         lwz     r4,GOT(_end)
 609
 610         cmplw   0, r3, r4
 611         beq     6f
 612
 613         li      r0, 0
 614 5:
 615         stw     r0, 0(r3)
 616         addi    r3, r3, 4
 617         cmplw   0, r3, r4
 618         blt     5b
 619 6:
 620
 621         mr      r3, r9          /* Global Data pointer          */
 622         mr      r4, r10         /* Destination Address          */
 623         bl      board_init_r
 624
 625         /*
 626          * Copy exception vector code to low memory
 627          *
 628          * r3: dest_addr
 629          * r7: source address, r8: end address, r9: target address
 630          */
 631         .globl  trap_init
 632 trap_init:
 633         mflr    r4                      /* save link register           */
 634         GET_GOT
 635         lwz     r7, GOT(_start)
 636         lwz     r8, GOT(_end_of_vectors)
 637
 638         li      r9, 0x100               /* reset vector always at 0x100 */
 639
 640         cmplw   0, r7, r8
 641         bgelr                           /* return if r7>=r8 - just in case */
 642 1:
 643         lwz     r0, 0(r7)
 644         stw     r0, 0(r9)
 645         addi    r7, r7, 4
 646         addi    r9, r9, 4
 647         cmplw   0, r7, r8
 648         bne     1b
 649
 650         /*
 651          * relocate `hdlr' and `int_return' entries
 652          */
 653         li      r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
 654         li      r8, Alignment - _start + EXC_OFF_SYS_RESET
 655 2:
 656         bl      trap_reloc
 657         addi    r7, r7, 0x100           /* next exception vector        */
 658         cmplw   0, r7, r8
 659         blt     2b
 660
 661         li      r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
 662         bl      trap_reloc
 663
 664         li      r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
 665         bl      trap_reloc
 666
 667         li      r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
 668         li      r8, SystemCall - _start + EXC_OFF_SYS_RESET
 669 3:
 670         bl      trap_reloc
 671         addi    r7, r7, 0x100           /* next exception vector        */
 672         cmplw   0, r7, r8
 673         blt     3b
 674
 675         li      r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
 676         li      r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
 677 4:
 678         bl      trap_reloc
 679         addi    r7, r7, 0x100           /* next exception vector        */
 680         cmplw   0, r7, r8
 681         blt     4b
 682
 683         mtlr    r4                      /* restore link register        */
 684         blr
 685
 686         /* Setup the BAT registers.
 687          */
 688 setup_bats:
 689         lis     r4, CONFIG_SYS_IBAT0L@h
 690         ori     r4, r4, CONFIG_SYS_IBAT0L@l
 691         lis     r3, CONFIG_SYS_IBAT0U@h
 692         ori     r3, r3, CONFIG_SYS_IBAT0U@l
 693         mtspr   IBAT0L, r4
 694         mtspr   IBAT0U, r3
 695         isync
 696
 697         lis     r4, CONFIG_SYS_DBAT0L@h
 698         ori     r4, r4, CONFIG_SYS_DBAT0L@l
 699         lis     r3, CONFIG_SYS_DBAT0U@h
 700         ori     r3, r3, CONFIG_SYS_DBAT0U@l
 701         mtspr   DBAT0L, r4
 702         mtspr   DBAT0U, r3
 703         isync
 704
 705         lis     r4, CONFIG_SYS_IBAT1L@h
 706         ori     r4, r4, CONFIG_SYS_IBAT1L@l
 707         lis     r3, CONFIG_SYS_IBAT1U@h
 708         ori     r3, r3, CONFIG_SYS_IBAT1U@l
 709         mtspr   IBAT1L, r4
 710         mtspr   IBAT1U, r3
 711         isync
 712
 713         lis     r4, CONFIG_SYS_DBAT1L@h
 714         ori     r4, r4, CONFIG_SYS_DBAT1L@l
 715         lis     r3, CONFIG_SYS_DBAT1U@h
 716         ori     r3, r3, CONFIG_SYS_DBAT1U@l
 717         mtspr   DBAT1L, r4
 718         mtspr   DBAT1U, r3
 719         isync
 720
 721         lis     r4, CONFIG_SYS_IBAT2L@h
 722         ori     r4, r4, CONFIG_SYS_IBAT2L@l
 723         lis     r3, CONFIG_SYS_IBAT2U@h
 724         ori     r3, r3, CONFIG_SYS_IBAT2U@l
 725         mtspr   IBAT2L, r4
 726         mtspr   IBAT2U, r3
 727         isync
 728
 729         lis     r4, CONFIG_SYS_DBAT2L@h
 730         ori     r4, r4, CONFIG_SYS_DBAT2L@l
 731         lis     r3, CONFIG_SYS_DBAT2U@h
 732         ori     r3, r3, CONFIG_SYS_DBAT2U@l
 733         mtspr   DBAT2L, r4
 734         mtspr   DBAT2U, r3
 735         isync
 736
 737         lis     r4, CONFIG_SYS_IBAT3L@h
 738         ori     r4, r4, CONFIG_SYS_IBAT3L@l
 739         lis     r3, CONFIG_SYS_IBAT3U@h
 740         ori     r3, r3, CONFIG_SYS_IBAT3U@l
 741         mtspr   IBAT3L, r4
 742         mtspr   IBAT3U, r3
 743         isync
 744
 745         lis     r4, CONFIG_SYS_DBAT3L@h
 746         ori     r4, r4, CONFIG_SYS_DBAT3L@l
 747         lis     r3, CONFIG_SYS_DBAT3U@h
 748         ori     r3, r3, CONFIG_SYS_DBAT3U@l
 749         mtspr   DBAT3L, r4
 750         mtspr   DBAT3U, r3
 751         isync
 752
 753         /* Invalidate TLBs.
 754          * -> for (val = 0; val < 0x20000; val+=0x1000)
 755          * ->   tlbie(val);
 756          */
 757         lis     r3, 0
 758         lis     r5, 2
 759
 760 1:
 761         tlbie   r3
 762         addi    r3, r3, 0x1000
 763         cmp     0, 0, r3, r5
 764         blt     1b
 765
 766         blr