arch/ppc/cpu/mpc83xx/cpu_init.c

   1 /*
   2  * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <mpc83xx.h>
  25 #include <ioports.h>
  26 #include <asm/io.h>
  27 #ifdef CONFIG_USB_EHCI_FSL
  28 #include <usb/ehci-fsl.h>
  29 #endif
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 #ifdef CONFIG_QE
  34 extern qe_iop_conf_t qe_iop_conf_tab[];
  35 extern void qe_config_iopin(u8 port, u8 pin, int dir,
  36                          int open_drain, int assign);
  37 extern void qe_init(uint qe_base);
  38 extern void qe_reset(void);
  39
  40 static void config_qe_ioports(void)
  41 {
  42         u8      port, pin;
  43         int     dir, open_drain, assign;
  44         int     i;
  45
  46         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  47                 port            = qe_iop_conf_tab[i].port;
  48                 pin             = qe_iop_conf_tab[i].pin;
  49                 dir             = qe_iop_conf_tab[i].dir;
  50                 open_drain      = qe_iop_conf_tab[i].open_drain;
  51                 assign          = qe_iop_conf_tab[i].assign;
  52                 qe_config_iopin(port, pin, dir, open_drain, assign);
  53         }
  54 }
  55 #endif
  56
  57 /*
  58  * Breathe some life into the CPU...
  59  *
  60  * Set up the memory map,
  61  * initialize a bunch of registers,
  62  * initialize the UPM's
  63  */
  64 void cpu_init_f (volatile immap_t * im)
  65 {
  66         __be32 acr_mask =
  67 #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
  68                 (ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
  69 #endif
  70 #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
  71                 (ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
  72 #endif
  73 #ifdef CONFIG_SYS_ACR_APARK     /* Arbiter address parking mode */
  74                 (ACR_APARK << ACR_APARK_SHIFT) |
  75 #endif
  76 #ifdef CONFIG_SYS_ACR_PARKM     /* Arbiter parking master */
  77                 (ACR_PARKM << ACR_PARKM_SHIFT) |
  78 #endif
  79                 0;
  80         __be32 acr_val =
  81 #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
  82                 (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
  83 #endif
  84 #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
  85                 (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
  86 #endif
  87 #ifdef CONFIG_SYS_ACR_APARK     /* Arbiter address parking mode */
  88                 (CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) |
  89 #endif
  90 #ifdef CONFIG_SYS_ACR_PARKM     /* Arbiter parking master */
  91                 (CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) |
  92 #endif
  93                 0;
  94         __be32 spcr_mask =
  95 #ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
  96                 (SPCR_OPT << SPCR_OPT_SHIFT) |
  97 #endif
  98 #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
  99                 (SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
 100 #endif
 101 #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
 102                 (SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
 103 #endif
 104 #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
 105                 (SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
 106 #endif
 107                 0;
 108         __be32 spcr_val =
 109 #ifdef CONFIG_SYS_SPCR_OPT
 110                 (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
 111 #endif
 112 #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
 113                 (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
 114 #endif
 115 #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
 116                 (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
 117 #endif
 118 #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
 119                 (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
 120 #endif
 121                 0;
 122         __be32 sccr_mask =
 123 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
 124                 (SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
 125 #endif
 126 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
 127                 (SCCR_PCICM << SCCR_PCICM_SHIFT) |
 128 #endif
 129 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
 130                 (SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
 131 #endif
 132 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
 133                 (SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
 134 #endif
 135 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
 136                 (SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
 137 #endif
 138 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
 139                 (SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
 140 #endif
 141 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
 142                 (SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
 143 #endif
 144 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
 145                 (SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
 146 #endif
 147 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
 148                 (SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
 149 #endif
 150 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
 151                 (SCCR_SATACM << SCCR_SATACM_SHIFT) |
 152 #endif
 153                 0;
 154         __be32 sccr_val =
 155 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
 156                 (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
 157 #endif
 158 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
 159                 (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
 160 #endif
 161 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
 162                 (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
 163 #endif
 164 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
 165                 (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
 166 #endif
 167 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
 168                 (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
 169 #endif
 170 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
 171                 (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
 172 #endif
 173 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
 174                 (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
 175 #endif
 176 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
 177                 (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
 178 #endif
 179 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
 180                 (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
 181 #endif
 182 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
 183                 (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
 184 #endif
 185                 0;
 186         __be32 lcrr_mask =
 187 #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
 188                 LCRR_DBYP |
 189 #endif
 190 #ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
 191                 LCRR_EADC |
 192 #endif
 193 #ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
 194                 LCRR_CLKDIV |
 195 #endif
 196                 0;
 197         __be32 lcrr_val =
 198 #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
 199                 CONFIG_SYS_LCRR_DBYP |
 200 #endif
 201 #ifdef CONFIG_SYS_LCRR_EADC
 202                 CONFIG_SYS_LCRR_EADC |
 203 #endif
 204 #ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
 205                 CONFIG_SYS_LCRR_CLKDIV |
 206 #endif
 207                 0;
 208
 209         /* Pointer is writable since we allocated a register for it */
 210         gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 211
 212         /* Clear initial global data */
 213         memset ((void *) gd, 0, sizeof (gd_t));
 214
 215         /* system performance tweaking */
 216         clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
 217
 218         clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
 219
 220         clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
 221
 222         /* RSR - Reset Status Register - clear all status (4.6.1.3) */
 223         gd->reset_status = __raw_readl(&im->reset.rsr);
 224         __raw_writel(~(RSR_RES), &im->reset.rsr);
 225
 226         /* AER - Arbiter Event Register - store status */
 227         gd->arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
 228         gd->arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
 229
 230         /*
 231          * RMR - Reset Mode Register
 232          * contains checkstop reset enable (4.6.1.4)
 233          */
 234         __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
 235
 236         /* LCRR - Clock Ratio Register (10.3.1.16)
 237          * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
 238          */
 239         clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
 240         __raw_readl(&im->lbus.lcrr);
 241         isync();
 242
 243         /* Enable Time Base & Decrementer ( so we will have udelay() )*/
 244         setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
 245
 246         /* System General Purpose Register */
 247 #ifdef CONFIG_SYS_SICRH
 248 #if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
 249         /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
 250         __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
 251                      &im->sysconf.sicrh);
 252 #else
 253         __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
 254 #endif
 255 #endif
 256 #ifdef CONFIG_SYS_SICRL
 257         __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
 258 #endif
 259 #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
 260         __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
 261 #endif
 262 #ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
 263         __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
 264 #endif
 265
 266 #ifdef CONFIG_QE
 267         /* Config QE ioports */
 268         config_qe_ioports();
 269 #endif
 270
 271         /*
 272          * Memory Controller:
 273          */
 274
 275         /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
 276          * addresses - these have to be modified later when FLASH size
 277          * has been determined
 278          */
 279
 280 #if defined(CONFIG_SYS_BR0_PRELIM)  \
 281         && defined(CONFIG_SYS_OR0_PRELIM) \
 282         && defined(CONFIG_SYS_LBLAWBAR0_PRELIM) \
 283         && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
 284         im->lbus.bank[0].br = CONFIG_SYS_BR0_PRELIM;
 285         im->lbus.bank[0].or = CONFIG_SYS_OR0_PRELIM;
 286         im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
 287         im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
 288 #else
 289 #error  CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
 290 #endif
 291
 292 #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
 293         im->lbus.bank[1].br = CONFIG_SYS_BR1_PRELIM;
 294         im->lbus.bank[1].or = CONFIG_SYS_OR1_PRELIM;
 295 #endif
 296 #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
 297         im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
 298         im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
 299 #endif
 300 #if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
 301         im->lbus.bank[2].br = CONFIG_SYS_BR2_PRELIM;
 302         im->lbus.bank[2].or = CONFIG_SYS_OR2_PRELIM;
 303 #endif
 304 #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
 305         im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
 306         im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
 307 #endif
 308 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
 309         im->lbus.bank[3].br = CONFIG_SYS_BR3_PRELIM;
 310         im->lbus.bank[3].or = CONFIG_SYS_OR3_PRELIM;
 311 #endif
 312 #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
 313         im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
 314         im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
 315 #endif
 316 #if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
 317         im->lbus.bank[4].br = CONFIG_SYS_BR4_PRELIM;
 318         im->lbus.bank[4].or = CONFIG_SYS_OR4_PRELIM;
 319 #endif
 320 #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
 321         im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
 322         im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
 323 #endif
 324 #if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
 325         im->lbus.bank[5].br = CONFIG_SYS_BR5_PRELIM;
 326         im->lbus.bank[5].or = CONFIG_SYS_OR5_PRELIM;
 327 #endif
 328 #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
 329         im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
 330         im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
 331 #endif
 332 #if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
 333         im->lbus.bank[6].br = CONFIG_SYS_BR6_PRELIM;
 334         im->lbus.bank[6].or = CONFIG_SYS_OR6_PRELIM;
 335 #endif
 336 #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
 337         im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
 338         im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
 339 #endif
 340 #if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
 341         im->lbus.bank[7].br = CONFIG_SYS_BR7_PRELIM;
 342         im->lbus.bank[7].or = CONFIG_SYS_OR7_PRELIM;
 343 #endif
 344 #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
 345         im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
 346         im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
 347 #endif
 348 #ifdef CONFIG_SYS_GPIO1_PRELIM
 349         im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
 350         im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
 351 #endif
 352 #ifdef CONFIG_SYS_GPIO2_PRELIM
 353         im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
 354         im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
 355 #endif
 356 #ifdef CONFIG_USB_EHCI_FSL
 357 #ifndef CONFIG_MPC834x
 358         uint32_t temp;
 359         struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
 360
 361         /* Configure interface. */
 362         setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
 363
 364         /* Wait for clock to stabilize */
 365         do {
 366                 temp = __raw_readl(&ehci->control);
 367                 udelay(1000);
 368         } while (!(temp & PHY_CLK_VALID));
 369 #endif
 370 #endif
 371 }
 372
 373 int cpu_init_r (void)
 374 {
 375 #ifdef CONFIG_QE
 376         uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
 377
 378         qe_init(qe_base);
 379         qe_reset();
 380 #endif
 381         return 0;
 382 }
 383
 384 /*
 385  * Print out the bus arbiter event
 386  */
 387 #if defined(CONFIG_DISPLAY_AER_FULL)
 388 static int print_83xx_arb_event(int force)
 389 {
 390         static char* event[] = {
 391                 "Address Time Out",
 392                 "Data Time Out",
 393                 "Address Only Transfer Type",
 394                 "External Control Word Transfer Type",
 395                 "Reserved Transfer Type",
 396                 "Transfer Error",
 397                 "reserved",
 398                 "reserved"
 399         };
 400         static char* master[] = {
 401                 "e300 Core Data Transaction",
 402                 "reserved",
 403                 "e300 Core Instruction Fetch",
 404                 "reserved",
 405                 "TSEC1",
 406                 "TSEC2",
 407                 "USB MPH",
 408                 "USB DR",
 409                 "Encryption Core",
 410                 "I2C Boot Sequencer",
 411                 "JTAG",
 412                 "reserved",
 413                 "eSDHC",
 414                 "PCI1",
 415                 "PCI2",
 416                 "DMA",
 417                 "QUICC Engine 00",
 418                 "QUICC Engine 01",
 419                 "QUICC Engine 10",
 420                 "QUICC Engine 11",
 421                 "reserved",
 422                 "reserved",
 423                 "reserved",
 424                 "reserved",
 425                 "SATA1",
 426                 "SATA2",
 427                 "SATA3",
 428                 "SATA4",
 429                 "reserved",
 430                 "PCI Express 1",
 431                 "PCI Express 2",
 432                 "TDM-DMAC"
 433         };
 434         static char *transfer[] = {
 435                 "Address-only, Clean Block",
 436                 "Address-only, lwarx reservation set",
 437                 "Single-beat or Burst write",
 438                 "reserved",
 439                 "Address-only, Flush Block",
 440                 "reserved",
 441                 "Burst write",
 442                 "reserved",
 443                 "Address-only, sync",
 444                 "Address-only, tlbsync",
 445                 "Single-beat or Burst read",
 446                 "Single-beat or Burst read",
 447                 "Address-only, Kill Block",
 448                 "Address-only, icbi",
 449                 "Burst read",
 450                 "reserved",
 451                 "Address-only, eieio",
 452                 "reserved",
 453                 "Single-beat write",
 454                 "reserved",
 455                 "ecowx - Illegal single-beat write",
 456                 "reserved",
 457                 "reserved",
 458                 "reserved",
 459                 "Address-only, TLB Invalidate",
 460                 "reserved",
 461                 "Single-beat or Burst read",
 462                 "reserved",
 463                 "eciwx - Illegal single-beat read",
 464                 "reserved",
 465                 "Burst read",
 466                 "reserved"
 467         };
 468
 469         int etype = (gd->arbiter_event_attributes & AEATR_EVENT)
 470                     >> AEATR_EVENT_SHIFT;
 471         int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID)
 472                       >> AEATR_MSTR_ID_SHIFT;
 473         int tbst = (gd->arbiter_event_attributes & AEATR_TBST)
 474                    >> AEATR_TBST_SHIFT;
 475         int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE)
 476                     >> AEATR_TSIZE_SHIFT;
 477         int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE)
 478                     >> AEATR_TTYPE_SHIFT;
 479
 480         if (!force && !gd->arbiter_event_address)
 481                 return 0;
 482
 483         puts("Arbiter Event Status:\n");
 484         printf("       Event Address: 0x%08lX\n", gd->arbiter_event_address);
 485         printf("       Event Type:    0x%1x  = %s\n", etype, event[etype]);
 486         printf("       Master ID:     0x%02x = %s\n", mstr_id, master[mstr_id]);
 487         printf("       Transfer Size: 0x%1x  = %d bytes\n", (tbst<<3) | tsize,
 488                                 tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
 489         printf("       Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
 490
 491         return gd->arbiter_event_address;
 492 }
 493
 494 #elif defined(CONFIG_DISPLAY_AER_BRIEF)
 495
 496 static int print_83xx_arb_event(int force)
 497 {
 498         if (!force && !gd->arbiter_event_address)
 499                 return 0;
 500
 501         printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
 502                 gd->arbiter_event_attributes, gd->arbiter_event_address);
 503
 504         return gd->arbiter_event_address;
 505 }
 506 #endif /* CONFIG_DISPLAY_AER_xxxx */
 507
 508 /*
 509  * Figure out the cause of the reset
 510  */
 511 int prt_83xx_rsr(void)
 512 {
 513         static struct {
 514                 ulong mask;
 515                 char *desc;
 516         } bits[] = {
 517                 {
 518                 RSR_SWSR, "Software Soft"}, {
 519                 RSR_SWHR, "Software Hard"}, {
 520                 RSR_JSRS, "JTAG Soft"}, {
 521                 RSR_CSHR, "Check Stop"}, {
 522                 RSR_SWRS, "Software Watchdog"}, {
 523                 RSR_BMRS, "Bus Monitor"}, {
 524                 RSR_SRS,  "External/Internal Soft"}, {
 525                 RSR_HRS,  "External/Internal Hard"}
 526         };
 527         static int n = sizeof bits / sizeof bits[0];
 528         ulong rsr = gd->reset_status;
 529         int i;
 530         char *sep;
 531
 532         puts("Reset Status:");
 533
 534         sep = " ";
 535         for (i = 0; i < n; i++)
 536                 if (rsr & bits[i].mask) {
 537                         printf("%s%s", sep, bits[i].desc);
 538                         sep = ", ";
 539                 }
 540         puts("\n");
 541
 542 #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
 543         print_83xx_arb_event(rsr & RSR_BMRS);
 544 #endif
 545         puts("\n");
 546
 547         return 0;
 548 }