arch/ppc/cpu/mpc83xx/speed.c

   1 /*
   2  * (C) Copyright 2000-2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <mpc83xx.h>
  28 #include <command.h>
  29 #include <asm/processor.h>
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 /* ----------------------------------------------------------------- */
  34
  35 typedef enum {
  36         _unk,
  37         _off,
  38         _byp,
  39         _x8,
  40         _x4,
  41         _x2,
  42         _x1,
  43         _1x,
  44         _1_5x,
  45         _2x,
  46         _2_5x,
  47         _3x
  48 } mult_t;
  49
  50 typedef struct {
  51         mult_t core_csb_ratio;
  52         mult_t vco_divider;
  53 } corecnf_t;
  54
  55 corecnf_t corecnf_tab[] = {
  56         {_byp, _byp},           /* 0x00 */
  57         {_byp, _byp},           /* 0x01 */
  58         {_byp, _byp},           /* 0x02 */
  59         {_byp, _byp},           /* 0x03 */
  60         {_byp, _byp},           /* 0x04 */
  61         {_byp, _byp},           /* 0x05 */
  62         {_byp, _byp},           /* 0x06 */
  63         {_byp, _byp},           /* 0x07 */
  64         {_1x, _x2},             /* 0x08 */
  65         {_1x, _x4},             /* 0x09 */
  66         {_1x, _x8},             /* 0x0A */
  67         {_1x, _x8},             /* 0x0B */
  68         {_1_5x, _x2},           /* 0x0C */
  69         {_1_5x, _x4},           /* 0x0D */
  70         {_1_5x, _x8},           /* 0x0E */
  71         {_1_5x, _x8},           /* 0x0F */
  72         {_2x, _x2},             /* 0x10 */
  73         {_2x, _x4},             /* 0x11 */
  74         {_2x, _x8},             /* 0x12 */
  75         {_2x, _x8},             /* 0x13 */
  76         {_2_5x, _x2},           /* 0x14 */
  77         {_2_5x, _x4},           /* 0x15 */
  78         {_2_5x, _x8},           /* 0x16 */
  79         {_2_5x, _x8},           /* 0x17 */
  80         {_3x, _x2},             /* 0x18 */
  81         {_3x, _x4},             /* 0x19 */
  82         {_3x, _x8},             /* 0x1A */
  83         {_3x, _x8},             /* 0x1B */
  84 };
  85
  86 /* ----------------------------------------------------------------- */
  87
  88 /*
  89  *
  90  */
  91 int get_clocks(void)
  92 {
  93         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  94         u32 pci_sync_in;
  95         u8 spmf;
  96         u8 clkin_div;
  97         u32 sccr;
  98         u32 corecnf_tab_index;
  99         u8 corepll;
 100         u32 lcrr;
 101
 102         u32 csb_clk;
 103 #if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
 104         u32 tsec1_clk;
 105         u32 tsec2_clk;
 106         u32 usbdr_clk;
 107 #endif
 108 #ifdef CONFIG_MPC834x
 109         u32 usbmph_clk;
 110 #endif
 111         u32 core_clk;
 112         u32 i2c1_clk;
 113 #if !defined(CONFIG_MPC832x)
 114         u32 i2c2_clk;
 115 #endif
 116 #if defined(CONFIG_MPC8315)
 117         u32 tdm_clk;
 118 #endif
 119 #if defined(CONFIG_MPC837x)
 120         u32 sdhc_clk;
 121 #endif
 122         u32 enc_clk;
 123         u32 lbiu_clk;
 124         u32 lclk_clk;
 125         u32 mem_clk;
 126 #if defined(CONFIG_MPC8360)
 127         u32 mem_sec_clk;
 128 #endif
 129 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
 130         u32 qepmf;
 131         u32 qepdf;
 132         u32 qe_clk;
 133         u32 brg_clk;
 134 #endif
 135 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
 136         u32 pciexp1_clk;
 137         u32 pciexp2_clk;
 138 #endif
 139 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
 140         u32 sata_clk;
 141 #endif
 142
 143         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 144                 return -1;
 145
 146         clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
 147
 148         if (im->reset.rcwh & HRCWH_PCI_HOST) {
 149 #if defined(CONFIG_83XX_CLKIN)
 150                 pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
 151 #else
 152                 pci_sync_in = 0xDEADBEEF;
 153 #endif
 154         } else {
 155 #if defined(CONFIG_83XX_PCICLK)
 156                 pci_sync_in = CONFIG_83XX_PCICLK;
 157 #else
 158                 pci_sync_in = 0xDEADBEEF;
 159 #endif
 160         }
 161
 162         spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT);
 163         csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
 164
 165         sccr = im->clk.sccr;
 166
 167 #if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
 168         switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
 169         case 0:
 170                 tsec1_clk = 0;
 171                 break;
 172         case 1:
 173                 tsec1_clk = csb_clk;
 174                 break;
 175         case 2:
 176                 tsec1_clk = csb_clk / 2;
 177                 break;
 178         case 3:
 179                 tsec1_clk = csb_clk / 3;
 180                 break;
 181         default:
 182                 /* unkown SCCR_TSEC1CM value */
 183                 return -2;
 184         }
 185
 186         switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
 187         case 0:
 188                 usbdr_clk = 0;
 189                 break;
 190         case 1:
 191                 usbdr_clk = csb_clk;
 192                 break;
 193         case 2:
 194                 usbdr_clk = csb_clk / 2;
 195                 break;
 196         case 3:
 197                 usbdr_clk = csb_clk / 3;
 198                 break;
 199         default:
 200                 /* unkown SCCR_USBDRCM value */
 201                 return -3;
 202         }
 203 #endif
 204
 205 #if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
 206         switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
 207         case 0:
 208                 tsec2_clk = 0;
 209                 break;
 210         case 1:
 211                 tsec2_clk = csb_clk;
 212                 break;
 213         case 2:
 214                 tsec2_clk = csb_clk / 2;
 215                 break;
 216         case 3:
 217                 tsec2_clk = csb_clk / 3;
 218                 break;
 219         default:
 220                 /* unkown SCCR_TSEC2CM value */
 221                 return -4;
 222         }
 223 #elif defined(CONFIG_MPC8313)
 224         tsec2_clk = tsec1_clk;
 225
 226         if (!(sccr & SCCR_TSEC1ON))
 227                 tsec1_clk = 0;
 228         if (!(sccr & SCCR_TSEC2ON))
 229                 tsec2_clk = 0;
 230 #endif
 231
 232 #if defined(CONFIG_MPC834x)
 233         switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
 234         case 0:
 235                 usbmph_clk = 0;
 236                 break;
 237         case 1:
 238                 usbmph_clk = csb_clk;
 239                 break;
 240         case 2:
 241                 usbmph_clk = csb_clk / 2;
 242                 break;
 243         case 3:
 244                 usbmph_clk = csb_clk / 3;
 245                 break;
 246         default:
 247                 /* unkown SCCR_USBMPHCM value */
 248                 return -5;
 249         }
 250
 251         if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
 252                 /* if USB MPH clock is not disabled and
 253                  * USB DR clock is not disabled then
 254                  * USB MPH & USB DR must have the same rate
 255                  */
 256                 return -6;
 257         }
 258 #endif
 259         switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
 260         case 0:
 261                 enc_clk = 0;
 262                 break;
 263         case 1:
 264                 enc_clk = csb_clk;
 265                 break;
 266         case 2:
 267                 enc_clk = csb_clk / 2;
 268                 break;
 269         case 3:
 270                 enc_clk = csb_clk / 3;
 271                 break;
 272         default:
 273                 /* unkown SCCR_ENCCM value */
 274                 return -7;
 275         }
 276
 277 #if defined(CONFIG_MPC837x)
 278         switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
 279         case 0:
 280                 sdhc_clk = 0;
 281                 break;
 282         case 1:
 283                 sdhc_clk = csb_clk;
 284                 break;
 285         case 2:
 286                 sdhc_clk = csb_clk / 2;
 287                 break;
 288         case 3:
 289                 sdhc_clk = csb_clk / 3;
 290                 break;
 291         default:
 292                 /* unkown SCCR_SDHCCM value */
 293                 return -8;
 294         }
 295 #endif
 296 #if defined(CONFIG_MPC8315)
 297         switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
 298         case 0:
 299                 tdm_clk = 0;
 300                 break;
 301         case 1:
 302                 tdm_clk = csb_clk;
 303                 break;
 304         case 2:
 305                 tdm_clk = csb_clk / 2;
 306                 break;
 307         case 3:
 308                 tdm_clk = csb_clk / 3;
 309                 break;
 310         default:
 311                 /* unkown SCCR_TDMCM value */
 312                 return -8;
 313         }
 314 #endif
 315
 316 #if defined(CONFIG_MPC834x)
 317         i2c1_clk = tsec2_clk;
 318 #elif defined(CONFIG_MPC8360)
 319         i2c1_clk = csb_clk;
 320 #elif defined(CONFIG_MPC832x)
 321         i2c1_clk = enc_clk;
 322 #elif defined(CONFIG_MPC831x)
 323         i2c1_clk = enc_clk;
 324 #elif defined(CONFIG_MPC837x)
 325         i2c1_clk = sdhc_clk;
 326 #endif
 327 #if !defined(CONFIG_MPC832x)
 328         i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
 329 #endif
 330
 331 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
 332         switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
 333         case 0:
 334                 pciexp1_clk = 0;
 335                 break;
 336         case 1:
 337                 pciexp1_clk = csb_clk;
 338                 break;
 339         case 2:
 340                 pciexp1_clk = csb_clk / 2;
 341                 break;
 342         case 3:
 343                 pciexp1_clk = csb_clk / 3;
 344                 break;
 345         default:
 346                 /* unkown SCCR_PCIEXP1CM value */
 347                 return -9;
 348         }
 349
 350         switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
 351         case 0:
 352                 pciexp2_clk = 0;
 353                 break;
 354         case 1:
 355                 pciexp2_clk = csb_clk;
 356                 break;
 357         case 2:
 358                 pciexp2_clk = csb_clk / 2;
 359                 break;
 360         case 3:
 361                 pciexp2_clk = csb_clk / 3;
 362                 break;
 363         default:
 364                 /* unkown SCCR_PCIEXP2CM value */
 365                 return -10;
 366         }
 367 #endif
 368
 369 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
 370         switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
 371         case 0:
 372                 sata_clk = 0;
 373                 break;
 374         case 1:
 375                 sata_clk = csb_clk;
 376                 break;
 377         case 2:
 378                 sata_clk = csb_clk / 2;
 379                 break;
 380         case 3:
 381                 sata_clk = csb_clk / 3;
 382                 break;
 383         default:
 384                 /* unkown SCCR_SATACM value */
 385                 return -11;
 386         }
 387 #endif
 388
 389         lbiu_clk = csb_clk *
 390                    (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
 391         lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
 392         switch (lcrr) {
 393         case 2:
 394         case 4:
 395         case 8:
 396                 lclk_clk = lbiu_clk / lcrr;
 397                 break;
 398         default:
 399                 /* unknown lcrr */
 400                 return -12;
 401         }
 402
 403         mem_clk = csb_clk *
 404                   (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
 405         corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
 406 #if defined(CONFIG_MPC8360)
 407         mem_sec_clk = csb_clk * (1 +
 408                        ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
 409 #endif
 410
 411         corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
 412         if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
 413                 /* corecnf_tab_index is too high, possibly worng value */
 414                 return -11;
 415         }
 416         switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
 417         case _byp:
 418         case _x1:
 419         case _1x:
 420                 core_clk = csb_clk;
 421                 break;
 422         case _1_5x:
 423                 core_clk = (3 * csb_clk) / 2;
 424                 break;
 425         case _2x:
 426                 core_clk = 2 * csb_clk;
 427                 break;
 428         case _2_5x:
 429                 core_clk = (5 * csb_clk) / 2;
 430                 break;
 431         case _3x:
 432                 core_clk = 3 * csb_clk;
 433                 break;
 434         default:
 435                 /* unkown core to csb ratio */
 436                 return -13;
 437         }
 438
 439 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
 440         qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT;
 441         qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT;
 442         qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
 443         brg_clk = qe_clk / 2;
 444 #endif
 445
 446         gd->csb_clk = csb_clk;
 447 #if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
 448         gd->tsec1_clk = tsec1_clk;
 449         gd->tsec2_clk = tsec2_clk;
 450         gd->usbdr_clk = usbdr_clk;
 451 #endif
 452 #if defined(CONFIG_MPC834x)
 453         gd->usbmph_clk = usbmph_clk;
 454 #endif
 455 #if defined(CONFIG_MPC8315)
 456         gd->tdm_clk = tdm_clk;
 457 #endif
 458 #if defined(CONFIG_MPC837x)
 459         gd->sdhc_clk = sdhc_clk;
 460 #endif
 461         gd->core_clk = core_clk;
 462         gd->i2c1_clk = i2c1_clk;
 463 #if !defined(CONFIG_MPC832x)
 464         gd->i2c2_clk = i2c2_clk;
 465 #endif
 466         gd->enc_clk = enc_clk;
 467         gd->lbiu_clk = lbiu_clk;
 468         gd->lclk_clk = lclk_clk;
 469         gd->mem_clk = mem_clk;
 470 #if defined(CONFIG_MPC8360)
 471         gd->mem_sec_clk = mem_sec_clk;
 472 #endif
 473 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
 474         gd->qe_clk = qe_clk;
 475         gd->brg_clk = brg_clk;
 476 #endif
 477 #if defined(CONFIG_MPC837x)
 478         gd->pciexp1_clk = pciexp1_clk;
 479         gd->pciexp2_clk = pciexp2_clk;
 480 #endif
 481 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
 482         gd->sata_clk = sata_clk;
 483 #endif
 484         gd->pci_clk = pci_sync_in;
 485         gd->cpu_clk = gd->core_clk;
 486         gd->bus_clk = gd->csb_clk;
 487         return 0;
 488
 489 }
 490
 491 /********************************************
 492  * get_bus_freq
 493  * return system bus freq in Hz
 494  *********************************************/
 495 ulong get_bus_freq(ulong dummy)
 496 {
 497         return gd->csb_clk;
 498 }
 499
 500 int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 501 {
 502         char buf[32];
 503
 504         printf("Clock configuration:\n");
 505         printf("  Core:                %-4s MHz\n", strmhz(buf, gd->core_clk));
 506         printf("  Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
 507 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
 508         printf("  QE:                  %-4s MHz\n", strmhz(buf, gd->qe_clk));
 509         printf("  BRG:                 %-4s MHz\n", strmhz(buf, gd->brg_clk));
 510 #endif
 511         printf("  Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk));
 512         printf("  Local Bus:           %-4s MHz\n", strmhz(buf, gd->lclk_clk));
 513         printf("  DDR:                 %-4s MHz\n", strmhz(buf, gd->mem_clk));
 514 #if defined(CONFIG_MPC8360)
 515         printf("  DDR Secondary:       %-4s MHz\n", strmhz(buf, gd->mem_sec_clk));
 516 #endif
 517         printf("  SEC:                 %-4s MHz\n", strmhz(buf, gd->enc_clk));
 518         printf("  I2C1:                %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
 519 #if !defined(CONFIG_MPC832x)
 520         printf("  I2C2:                %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
 521 #endif
 522 #if defined(CONFIG_MPC8315)
 523         printf("  TDM:                 %-4s MHz\n", strmhz(buf, gd->tdm_clk));
 524 #endif
 525 #if defined(CONFIG_MPC837x)
 526         printf("  SDHC:                %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
 527 #endif
 528 #if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
 529         printf("  TSEC1:               %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
 530         printf("  TSEC2:               %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
 531         printf("  USB DR:              %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
 532 #endif
 533 #if defined(CONFIG_MPC834x)
 534         printf("  USB MPH:             %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
 535 #endif
 536 #if defined(CONFIG_MPC837x)
 537         printf("  PCIEXP1:             %-4s MHz\n", strmhz(buf, gd->pciexp1_clk));
 538         printf("  PCIEXP2:             %-4s MHz\n", strmhz(buf, gd->pciexp2_clk));
 539 #endif
 540 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
 541         printf("  SATA:                %-4s MHz\n", strmhz(buf, gd->sata_clk));
 542 #endif
 543         return 0;
 544 }
 545
 546 U_BOOT_CMD(clocks, 1, 0, do_clocks,
 547         "print clock configuration",
 548         "    clocks"
 549 );