arch/ppc/cpu/mpc85xx/interrupts.c

   1 /*
   2  * (C) Copyright 2000-2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2002 (440 port)
   6  * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
   7  *
   8  * (C) Copyright 2003 Motorola Inc. (MPC85xx port)
   9  * Xianghua Xiao (X.Xiao@motorola.com)
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <common.h>
  31 #include <watchdog.h>
  32 #include <command.h>
  33 #include <asm/processor.h>
  34 #include <asm/io.h>
  35
  36 int interrupt_init_cpu(unsigned int *decrementer_count)
  37 {
  38         ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC85xx_PIC_ADDR;
  39
  40         out_be32(&pic->gcr, MPC85xx_PICGCR_RST);
  41         while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST)
  42                 ;
  43         out_be32(&pic->gcr, MPC85xx_PICGCR_M);
  44         in_be32(&pic->gcr);
  45
  46         *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
  47
  48         /* PIE is same as DIE, dec interrupt enable */
  49         mtspr(SPRN_TCR, TCR_PIE);
  50
  51 #ifdef CONFIG_INTERRUPTS
  52         pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */
  53         debug("iivpr1@%x = %x\n", (uint)&pic->iivpr1, pic->iivpr1);
  54
  55         pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
  56         debug("iivpr2@%x = %x\n", (uint)&pic->iivpr2, pic->iivpr2);
  57
  58         pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
  59         debug("iivpr3@%x = %x\n", (uint)&pic->iivpr3, pic->iivpr3);
  60
  61 #ifdef CONFIG_PCI1
  62         pic->iivpr8 = 0x810008; /* enable pci1 interrupts */
  63         debug("iivpr8@%x = %x\n", (uint)&pic->iivpr8, pic->iivpr8);
  64 #endif
  65 #if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
  66         pic->iivpr9 = 0x810009; /* enable pci1 interrupts */
  67         debug("iivpr9@%x = %x\n", (uint)&pic->iivpr9, pic->iivpr9);
  68 #endif
  69 #ifdef CONFIG_PCIE1
  70         pic->iivpr10 = 0x81000a;        /* enable pcie1 interrupts */
  71         debug("iivpr10@%x = %x\n", (uint)&pic->iivpr10, pic->iivpr10);
  72 #endif
  73 #ifdef CONFIG_PCIE3
  74         pic->iivpr11 = 0x81000b;        /* enable pcie3 interrupts */
  75         debug("iivpr11@%x = %x\n", (uint)&pic->iivpr11, pic->iivpr11);
  76 #endif
  77
  78         pic->ctpr=0;            /* 40080 clear current task priority register */
  79 #endif
  80
  81         return (0);
  82 }
  83
  84 /* Install and free a interrupt handler. Not implemented yet. */
  85
  86 void
  87 irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
  88 {
  89         return;
  90 }
  91
  92 void
  93 irq_free_handler(int vec)
  94 {
  95         return;
  96 }
  97
  98 void timer_interrupt_cpu(struct pt_regs *regs)
  99 {
 100         /* PIS is same as DIS, dec interrupt status */
 101         mtspr(SPRN_TSR, TSR_PIS);
 102 }
 103
 104 #if defined(CONFIG_CMD_IRQ)
 105 /* irqinfo - print information about PCI devices,not implemented. */
 106 int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 107 {
 108         return 0;
 109 }
 110 #endif