arch/ppc/cpu/mpc8xx/lcd.c

   1 /*
   2  * (C) Copyright 2001-2002
   3  * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /************************************************************************/
  25 /* ** HEADER FILES                                                      */
  26 /************************************************************************/
  27
  28 /* #define DEBUG */
  29
  30 #include <config.h>
  31 #include <common.h>
  32 #include <command.h>
  33 #include <watchdog.h>
  34 #include <version.h>
  35 #include <stdarg.h>
  36 #include <lcdvideo.h>
  37 #include <linux/types.h>
  38 #include <stdio_dev.h>
  39 #if defined(CONFIG_POST)
  40 #include <post.h>
  41 #endif
  42 #include <lcd.h>
  43
  44 #ifdef CONFIG_LCD
  45
  46 /************************************************************************/
  47 /* ** CONFIG STUFF -- should be moved to board config file              */
  48 /************************************************************************/
  49 #ifndef CONFIG_LCD_INFO
  50 #define CONFIG_LCD_INFO         /* Display Logo, (C) and system info    */
  51 #endif
  52
  53 #if defined(CONFIG_V37) || defined(CONFIG_EDT32F10)
  54 #undef CONFIG_LCD_LOGO
  55 #undef CONFIG_LCD_INFO
  56 #endif
  57
  58 /*----------------------------------------------------------------------*/
  59 #ifdef CONFIG_KYOCERA_KCS057QV1AJ
  60 /*
  61  *  Kyocera KCS057QV1AJ-G23. Passive, color, single scan.
  62  */
  63 #define LCD_BPP LCD_COLOR4
  64
  65 vidinfo_t panel_info = {
  66     640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
  67     LCD_BPP, 1, 0, 1, 0,  5, 0, 0, 0
  68                 /* wbl, vpw, lcdac, wbf */
  69 };
  70 #endif /* CONFIG_KYOCERA_KCS057QV1AJ */
  71 /*----------------------------------------------------------------------*/
  72
  73 /*----------------------------------------------------------------------*/
  74 #ifdef CONFIG_HITACHI_SP19X001_Z1A
  75 /*
  76  *  Hitachi SP19X001-. Active, color, single scan.
  77  */
  78 vidinfo_t panel_info = {
  79     640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
  80     LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0
  81                 /* wbl, vpw, lcdac, wbf */
  82 };
  83 #endif /* CONFIG_HITACHI_SP19X001_Z1A */
  84 /*----------------------------------------------------------------------*/
  85
  86 /*----------------------------------------------------------------------*/
  87 #ifdef CONFIG_NEC_NL6448AC33
  88 /*
  89  *  NEC NL6448AC33-18. Active, color, single scan.
  90  */
  91 vidinfo_t panel_info = {
  92     640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
  93     3, 0, 0, 1, 1, 144, 2, 0, 33
  94                 /* wbl, vpw, lcdac, wbf */
  95 };
  96 #endif /* CONFIG_NEC_NL6448AC33 */
  97 /*----------------------------------------------------------------------*/
  98
  99 #ifdef CONFIG_NEC_NL6448BC20
 100 /*
 101  *  NEC NL6448BC20-08.  6.5", 640x480. Active, color, single scan.
 102  */
 103 vidinfo_t panel_info = {
 104     640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
 105     3, 0, 0, 1, 1, 144, 2, 0, 33
 106                 /* wbl, vpw, lcdac, wbf */
 107 };
 108 #endif /* CONFIG_NEC_NL6448BC20 */
 109 /*----------------------------------------------------------------------*/
 110
 111 #ifdef CONFIG_NEC_NL6448BC33_54
 112 /*
 113  *  NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan.
 114  */
 115 vidinfo_t panel_info = {
 116     640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
 117     3, 0, 0, 1, 1, 144, 2, 0, 33
 118                 /* wbl, vpw, lcdac, wbf */
 119 };
 120 #endif /* CONFIG_NEC_NL6448BC33_54 */
 121 /*----------------------------------------------------------------------*/
 122
 123 #ifdef CONFIG_SHARP_LQ104V7DS01
 124 /*
 125  *  SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan.
 126  */
 127 vidinfo_t panel_info = {
 128     640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
 129     3, 0, 0, 1, 1, 25, 1, 0, 33
 130                 /* wbl, vpw, lcdac, wbf */
 131 };
 132 #endif /* CONFIG_SHARP_LQ104V7DS01 */
 133 /*----------------------------------------------------------------------*/
 134
 135 #ifdef CONFIG_SHARP_16x9
 136 /*
 137  * Sharp 320x240. Active, color, single scan.  It isn't 16x9, and I am
 138  * not sure what it is.......
 139  */
 140 vidinfo_t panel_info = {
 141     320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
 142     3, 0, 0, 1, 1, 15, 4, 0, 3
 143 };
 144 #endif /* CONFIG_SHARP_16x9 */
 145 /*----------------------------------------------------------------------*/
 146
 147 #ifdef CONFIG_SHARP_LQ057Q3DC02
 148 /*
 149  * Sharp LQ057Q3DC02 display. Active, color, single scan.
 150  */
 151 #undef LCD_DF
 152 #define LCD_DF 12
 153
 154 vidinfo_t panel_info = {
 155     320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
 156     3, 0, 0, 1, 1, 15, 4, 0, 3
 157                 /* wbl, vpw, lcdac, wbf */
 158 };
 159 #define CONFIG_LCD_INFO_BELOW_LOGO
 160 #endif /* CONFIG_SHARP_LQ057Q3DC02 */
 161 /*----------------------------------------------------------------------*/
 162
 163 #ifdef CONFIG_SHARP_LQ64D341
 164 /*
 165  * Sharp LQ64D341 display, 640x480. Active, color, single scan.
 166  */
 167 vidinfo_t panel_info = {
 168     640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
 169     3, 0, 0, 1, 1, 128, 16, 0, 32
 170                 /* wbl, vpw, lcdac, wbf */
 171 };
 172 #endif /* CONFIG_SHARP_LQ64D341 */
 173
 174 #ifdef CONFIG_SHARP_LQ065T9DR51U
 175 /*
 176  * Sharp LQ065T9DR51U display, 400x240. Active, color, single scan.
 177  */
 178 vidinfo_t panel_info = {
 179     400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
 180     3, 0, 0, 1, 1, 248, 4, 0, 35
 181                 /* wbl, vpw, lcdac, wbf */
 182 };
 183 #define CONFIG_LCD_INFO_BELOW_LOGO
 184 #endif /* CONFIG_SHARP_LQ065T9DR51U */
 185
 186 #ifdef CONFIG_SHARP_LQ084V1DG21
 187 /*
 188  * Sharp LQ084V1DG21 display, 640x480. Active, color, single scan.
 189  */
 190 vidinfo_t panel_info = {
 191     640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
 192     3, 0, 0, 1, 1, 160, 3, 0, 48
 193                 /* wbl, vpw, lcdac, wbf */
 194 };
 195 #endif /* CONFIG_SHARP_LQ084V1DG21 */
 196
 197 /*----------------------------------------------------------------------*/
 198
 199 #ifdef CONFIG_HLD1045
 200 /*
 201  * HLD1045 display, 640x480. Active, color, single scan.
 202  */
 203 vidinfo_t panel_info = {
 204     640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
 205     3, 0, 0, 1, 1, 160, 3, 0, 48
 206                 /* wbl, vpw, lcdac, wbf */
 207 };
 208 #endif /* CONFIG_HLD1045 */
 209 /*----------------------------------------------------------------------*/
 210
 211 #ifdef CONFIG_PRIMEVIEW_V16C6448AC
 212 /*
 213  * Prime View V16C6448AC
 214  */
 215 vidinfo_t panel_info = {
 216     640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
 217     3, 0, 0, 1, 1, 144, 2, 0, 35
 218                 /* wbl, vpw, lcdac, wbf */
 219 };
 220 #endif /* CONFIG_PRIMEVIEW_V16C6448AC */
 221
 222 /*----------------------------------------------------------------------*/
 223
 224 #ifdef CONFIG_OPTREX_BW
 225 /*
 226  * Optrex   CBL50840-2 NF-FW 99 22 M5
 227  * or
 228  * Hitachi  LMG6912RPFC-00T
 229  * or
 230  * Hitachi  SP14Q002
 231  *
 232  * 320x240. Black & white.
 233  */
 234 #define OPTREX_BPP      0       /* 0 - monochrome,     1 bpp */
 235                                 /* 1 -  4 grey levels, 2 bpp */
 236                                 /* 2 - 16 grey levels, 4 bpp */
 237 vidinfo_t panel_info = {
 238     320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
 239     OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4
 240 };
 241 #endif /* CONFIG_OPTREX_BW */
 242
 243 /*-----------------------------------------------------------------*/
 244 #ifdef CONFIG_EDT32F10
 245 /*
 246  * Emerging Display Technologies 320x240. Passive, monochrome, single scan.
 247  */
 248 #define LCD_BPP         LCD_MONOCHROME
 249 #define LCD_DF          10
 250
 251 vidinfo_t panel_info = {
 252     320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
 253     LCD_BPP,  0, 0, 0, 0, 33, 0, 0, 0
 254 };
 255 #endif
 256 /*----------------------------------------------------------------------*/
 257
 258
 259 int lcd_line_length;
 260
 261 int lcd_color_fg;
 262 int lcd_color_bg;
 263
 264 /*
 265  * Frame buffer memory information
 266  */
 267 void *lcd_base;                 /* Start of framebuffer memory  */
 268 void *lcd_console_address;      /* Start of console buffer      */
 269
 270 short console_col;
 271 short console_row;
 272
 273 /************************************************************************/
 274
 275 void lcd_ctrl_init (void *lcdbase);
 276 void lcd_enable (void);
 277 #if LCD_BPP == LCD_COLOR8
 278 void lcd_setcolreg (ushort regno,
 279                                 ushort red, ushort green, ushort blue);
 280 #endif
 281 #if LCD_BPP == LCD_MONOCHROME
 282 void lcd_initcolregs (void);
 283 #endif
 284
 285 #if defined(CONFIG_RBC823)
 286 void lcd_disable (void);
 287 #endif
 288
 289 /************************************************************************/
 290
 291 /************************************************************************/
 292 /* ----------------- chipset specific functions ----------------------- */
 293 /************************************************************************/
 294
 295 /*
 296  * Calculate fb size for VIDEOLFB_ATAG.
 297  */
 298 ulong calc_fbsize (void)
 299 {
 300         ulong size;
 301         int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
 302
 303         size = line_length * panel_info.vl_row;
 304
 305         return size;
 306 }
 307
 308 void lcd_ctrl_init (void *lcdbase)
 309 {
 310         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 311         volatile lcd823_t *lcdp = &immr->im_lcd;
 312
 313         uint lccrtmp;
 314         uint lchcr_hpc_tmp;
 315
 316         /* Initialize the LCD control register according to the LCD
 317          * parameters defined.  We do everything here but enable
 318          * the controller.
 319          */
 320
 321 #ifdef CONFIG_RPXLITE
 322         /* This is special for RPXlite_DW Software Development Platform **[Sam]** */
 323         panel_info.vl_dp = CONFIG_SYS_LOW;
 324 #endif
 325
 326         lccrtmp  = LCDBIT (LCCR_BNUM_BIT,
 327                    (((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128));
 328
 329         lccrtmp |= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp)   |
 330                    LCDBIT (LCCR_OEP_BIT,  panel_info.vl_oep)    |
 331                    LCDBIT (LCCR_HSP_BIT,  panel_info.vl_hsp)    |
 332                    LCDBIT (LCCR_VSP_BIT,  panel_info.vl_vsp)    |
 333                    LCDBIT (LCCR_DP_BIT,   panel_info.vl_dp)     |
 334                    LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix)   |
 335                    LCDBIT (LCCR_LBW_BIT,  panel_info.vl_lbw)    |
 336                    LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt)   |
 337                    LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor)   |
 338                    LCDBIT (LCCR_TFT_BIT,  panel_info.vl_tft);
 339
 340 #if 0
 341         lccrtmp |= ((SIU_LEVEL5 / 2) << 12);
 342         lccrtmp |= LCCR_EIEN;
 343 #endif
 344
 345         lcdp->lcd_lccr = lccrtmp;
 346         lcdp->lcd_lcsr = 0xFF;          /* Clear pending interrupts */
 347
 348         /* Initialize LCD controller bus priorities.
 349          */
 350 #ifdef CONFIG_RBC823
 351         immr->im_siu_conf.sc_sdcr = (immr->im_siu_conf.sc_sdcr & ~0x0f) | 1;    /* RAID = 01, LAID = 00 */
 352 #else
 353         immr->im_siu_conf.sc_sdcr &= ~0x0f;     /* RAID = LAID = 0 */
 354
 355         /* set SHFT/CLOCK division factor 4
 356          * This needs to be set based upon display type and processor
 357          * speed.  The TFT displays run about 20 to 30 MHz.
 358          * I was running 64 MHz processor speed.
 359          * The value for this divider must be chosen so the result is
 360          * an integer of the processor speed (i.e., divide by 3 with
 361          * 64 MHz would be bad).
 362          */
 363         immr->im_clkrst.car_sccr &= ~0x1F;
 364         immr->im_clkrst.car_sccr |= LCD_DF;     /* was 8 */
 365
 366 #endif /* CONFIG_RBC823 */
 367
 368 #if defined(CONFIG_RBC823)
 369         /* Enable LCD on port D.
 370          */
 371         immr->im_ioport.iop_pddat &= 0x0300;
 372         immr->im_ioport.iop_pdpar |= 0x1CFF;
 373         immr->im_ioport.iop_pddir |= 0x1CFF;
 374
 375         /* Configure LCD_ON, VEE_ON, CCFL_ON on port B.
 376          */
 377         immr->im_cpm.cp_pbdat &= ~0x00005001;
 378         immr->im_cpm.cp_pbpar &= ~0x00005001;
 379         immr->im_cpm.cp_pbdir |=  0x00005001;
 380 #elif !defined(CONFIG_EDT32F10)
 381         /* Enable LCD on port D.
 382          */
 383         immr->im_ioport.iop_pdpar |= 0x1FFF;
 384         immr->im_ioport.iop_pddir |= 0x1FFF;
 385
 386         /* Enable LCD_A/B/C on port B.
 387          */
 388         immr->im_cpm.cp_pbpar |= 0x00005001;
 389         immr->im_cpm.cp_pbdir |= 0x00005001;
 390 #else
 391         /* Enable LCD on port D.
 392          */
 393         immr->im_ioport.iop_pdpar |= 0x1DFF;
 394         immr->im_ioport.iop_pdpar &= ~0x0200;
 395         immr->im_ioport.iop_pddir |= 0x1FFF;
 396         immr->im_ioport.iop_pddat |= 0x0200;
 397 #endif
 398
 399         /* Load the physical address of the linear frame buffer
 400          * into the LCD controller.
 401          * BIG NOTE:  This has to be modified to load A and B depending
 402          * upon the split mode of the LCD.
 403          */
 404         lcdp->lcd_lcfaa = (ulong)lcd_base;
 405         lcdp->lcd_lcfba = (ulong)lcd_base;
 406
 407         /* MORE HACKS...This must be updated according to 823 manual
 408          * for different panels.
 409          * Udi Finkelstein - done - see below:
 410          * Note: You better not try unsupported combinations such as
 411          * 4-bit wide passive dual scan LCD at 4/8 Bit color.
 412          */
 413         lchcr_hpc_tmp =
 414                 (panel_info.vl_col *
 415                  (panel_info.vl_tft ? 8 :
 416                         (((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */
 417                          /* use << to mult by: single scan = 1, dual scan = 2 */
 418                           panel_info.vl_splt) *
 419                          (panel_info.vl_bpix | 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */
 420
 421         lcdp->lcd_lchcr = LCHCR_BO |
 422                           LCDBIT (LCHCR_AT_BIT, 4) |
 423                           LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) |
 424                           panel_info.vl_wbl;
 425
 426         lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) |
 427                           LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) |
 428                           LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) |
 429                           panel_info.vl_wbf;
 430
 431 }
 432
 433 /*----------------------------------------------------------------------*/
 434
 435 #ifdef  NOT_USED_SO_FAR
 436 static void
 437 lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue)
 438 {
 439         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 440         volatile cpm8xx_t *cp = &(immr->im_cpm);
 441         unsigned short colreg, *cmap_ptr;
 442
 443         cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2];
 444
 445         colreg = *cmap_ptr;
 446 #ifdef  CONFIG_SYS_INVERT_COLORS
 447         colreg ^= 0x0FFF;
 448 #endif
 449
 450         *red   = (colreg >> 8) & 0x0F;
 451         *green = (colreg >> 4) & 0x0F;
 452         *blue  =  colreg       & 0x0F;
 453 }
 454 #endif  /* NOT_USED_SO_FAR */
 455
 456 /*----------------------------------------------------------------------*/
 457
 458 #if LCD_BPP == LCD_COLOR8
 459 void
 460 lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
 461 {
 462         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 463         volatile cpm8xx_t *cp = &(immr->im_cpm);
 464         unsigned short colreg, *cmap_ptr;
 465
 466         cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2];
 467
 468         colreg = ((red   & 0x0F) << 8) |
 469                  ((green & 0x0F) << 4) |
 470                   (blue  & 0x0F) ;
 471 #ifdef  CONFIG_SYS_INVERT_COLORS
 472         colreg ^= 0x0FFF;
 473 #endif
 474         *cmap_ptr = colreg;
 475
 476         debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n",
 477                 regno, &(cp->lcd_cmap[regno * 2]),
 478                 red, green, blue,
 479                 cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]);
 480 }
 481 #endif  /* LCD_COLOR8 */
 482
 483 /*----------------------------------------------------------------------*/
 484
 485 #if LCD_BPP == LCD_MONOCHROME
 486 static
 487 void lcd_initcolregs (void)
 488 {
 489         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 490         volatile cpm8xx_t *cp = &(immr->im_cpm);
 491         ushort regno;
 492
 493         for (regno = 0; regno < 16; regno++) {
 494                 cp->lcd_cmap[regno * 2] = 0;
 495                 cp->lcd_cmap[(regno * 2) + 1] = regno & 0x0f;
 496         }
 497 }
 498 #endif
 499
 500 /*----------------------------------------------------------------------*/
 501
 502 void lcd_enable (void)
 503 {
 504         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 505         volatile lcd823_t *lcdp = &immr->im_lcd;
 506
 507         /* Enable the LCD panel */
 508 #ifndef CONFIG_RBC823
 509         immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25));          /* LAM = 1 */
 510 #endif
 511         lcdp->lcd_lccr |= LCCR_PON;
 512
 513 #ifdef CONFIG_V37
 514         /* Turn on display backlight */
 515         immr->im_cpm.cp_pbpar |= 0x00008000;
 516         immr->im_cpm.cp_pbdir |= 0x00008000;
 517 #elif defined(CONFIG_RBC823)
 518         /* Turn on display backlight */
 519         immr->im_cpm.cp_pbdat |= 0x00004000;
 520 #endif
 521
 522 #if defined(CONFIG_LWMON)
 523     {   uchar c = pic_read (0x60);
 524 #if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CONFIG_SYS_POST_SYSMON)
 525         /* Enable LCD later in sysmon test, only if temperature is OK */
 526 #else
 527         c |= 0x07;      /* Power on CCFL, Enable CCFL, Chip Enable LCD */
 528 #endif
 529         pic_write (0x60, c);
 530     }
 531 #endif /* CONFIG_LWMON */
 532
 533 #if defined(CONFIG_R360MPI)
 534     {
 535         extern void r360_i2c_lcd_write (uchar data0, uchar data1);
 536         unsigned long bgi, ctr;
 537         char *p;
 538
 539         if ((p = getenv("lcdbgi")) != NULL) {
 540                 bgi = simple_strtoul (p, 0, 10) & 0xFFF;
 541         } else {
 542                 bgi = 0xFFF;
 543         }
 544
 545         if ((p = getenv("lcdctr")) != NULL) {
 546                 ctr = simple_strtoul (p, 0, 10) & 0xFFF;
 547         } else {
 548                 ctr=0x7FF;
 549         }
 550
 551         r360_i2c_lcd_write(0x10, 0x01);
 552         r360_i2c_lcd_write(0x20, 0x01);
 553         r360_i2c_lcd_write(0x30 | ((bgi>>8) & 0xF), bgi & 0xFF);
 554         r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF);
 555     }
 556 #endif /* CONFIG_R360MPI */
 557 #ifdef CONFIG_RBC823
 558         udelay(200000); /* wait 200ms */
 559         /* Turn VEE_ON first */
 560         immr->im_cpm.cp_pbdat |= 0x00000001;
 561         udelay(200000); /* wait 200ms */
 562         /* Now turn on LCD_ON */
 563         immr->im_cpm.cp_pbdat |= 0x00001000;
 564 #endif
 565 #ifdef CONFIG_RRVISION
 566         debug ("PC4->Output(1): enable LVDS\n");
 567         debug ("PC5->Output(0): disable PAL clock\n");
 568         immr->im_ioport.iop_pddir |=  0x1000;
 569         immr->im_ioport.iop_pcpar &= ~(0x0C00);
 570         immr->im_ioport.iop_pcdir |=   0x0C00 ;
 571         immr->im_ioport.iop_pcdat |=   0x0800 ;
 572         immr->im_ioport.iop_pcdat &= ~(0x0400);
 573         debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n",
 574                immr->im_ioport.iop_pdpar,
 575                immr->im_ioport.iop_pddir,
 576                immr->im_ioport.iop_pddat);
 577         debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n",
 578                immr->im_ioport.iop_pcpar,
 579                immr->im_ioport.iop_pcdir,
 580                immr->im_ioport.iop_pcdat);
 581 #endif
 582 }
 583
 584 /*----------------------------------------------------------------------*/
 585
 586 #if defined (CONFIG_RBC823)
 587 void lcd_disable (void)
 588 {
 589         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 590         volatile lcd823_t *lcdp = &immr->im_lcd;
 591
 592 #if defined(CONFIG_LWMON)
 593     {   uchar c = pic_read (0x60);
 594         c &= ~0x07;     /* Power off CCFL, Disable CCFL, Chip Disable LCD */
 595         pic_write (0x60, c);
 596     }
 597 #elif defined(CONFIG_R360MPI)
 598     {
 599         extern void r360_i2c_lcd_write (uchar data0, uchar data1);
 600
 601         r360_i2c_lcd_write(0x10, 0x00);
 602         r360_i2c_lcd_write(0x20, 0x00);
 603         r360_i2c_lcd_write(0x30, 0x00);
 604         r360_i2c_lcd_write(0x40, 0x00);
 605     }
 606 #endif /* CONFIG_LWMON */
 607         /* Disable the LCD panel */
 608         lcdp->lcd_lccr &= ~LCCR_PON;
 609 #ifdef CONFIG_RBC823
 610         /* Turn off display backlight, VEE and LCD_ON */
 611         immr->im_cpm.cp_pbdat &= ~0x00005001;
 612 #else
 613         immr->im_siu_conf.sc_sdcr &= ~(1 << (31 - 25)); /* LAM = 0 */
 614 #endif /* CONFIG_RBC823 */
 615 }
 616 #endif  /* NOT_USED_SO_FAR || CONFIG_RBC823 */
 617
 618
 619 /************************************************************************/
 620
 621 #endif /* CONFIG_LCD */