arch/ppc/include/asm/immap_8260.h

   1 /*
   2  * MPC8260 Internal Memory Map
   3  * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
   4  *
   5  * The Internal Memory Map of the 8260.  I don't know how generic
   6  * this will be, as I don't have any knowledge of the subsequent
   7  * parts at this time.  I copied this from the 8xx_immap.h.
   8  */
   9 #ifndef __IMMAP_82XX__
  10 #define __IMMAP_82XX__
  11
  12 /* System configuration registers.
  13 */
  14 typedef struct sys_conf {
  15         uint    sc_siumcr;
  16         uint    sc_sypcr;
  17         char    res1[6];
  18         ushort  sc_swsr;
  19         char    res2[20];
  20         uint    sc_bcr;
  21         u_char  sc_ppc_acr;
  22         char    res3[3];
  23         uint    sc_ppc_alrh;
  24         uint    sc_ppc_alrl;
  25         u_char  sc_lcl_acr;
  26         char    res4[3];
  27         uint    sc_lcl_alrh;
  28         uint    sc_lcl_alrl;
  29         uint    sc_tescr1;
  30         uint    sc_tescr2;
  31         uint    sc_ltescr1;
  32         uint    sc_ltescr2;
  33         uint    sc_pdtea;
  34         u_char  sc_pdtem;
  35         char    res5[3];
  36         uint    sc_ldtea;
  37         u_char  sc_ldtem;
  38         char    res6[163];
  39 } sysconf8260_t;
  40
  41
  42 /* Memory controller registers.
  43 */
  44 typedef struct  mem_ctlr {
  45         uint    memc_br0;
  46         uint    memc_or0;
  47         uint    memc_br1;
  48         uint    memc_or1;
  49         uint    memc_br2;
  50         uint    memc_or2;
  51         uint    memc_br3;
  52         uint    memc_or3;
  53         uint    memc_br4;
  54         uint    memc_or4;
  55         uint    memc_br5;
  56         uint    memc_or5;
  57         uint    memc_br6;
  58         uint    memc_or6;
  59         uint    memc_br7;
  60         uint    memc_or7;
  61         uint    memc_br8;
  62         uint    memc_or8;
  63         uint    memc_br9;
  64         uint    memc_or9;
  65         uint    memc_br10;
  66         uint    memc_or10;
  67         uint    memc_br11;
  68         uint    memc_or11;
  69         char    res1[8];
  70         uint    memc_mar;
  71         char    res2[4];
  72         uint    memc_mamr;
  73         uint    memc_mbmr;
  74         uint    memc_mcmr;
  75         char    res3[8];
  76         ushort  memc_mptpr;
  77         char    res4[2];
  78         uint    memc_mdr;
  79         char    res5[4];
  80         uint    memc_psdmr;
  81         uint    memc_lsdmr;
  82         u_char  memc_purt;
  83         char    res6[3];
  84         u_char  memc_psrt;
  85         char    res7[3];
  86         u_char  memc_lurt;
  87         char    res8[3];
  88         u_char  memc_lsrt;
  89         char    res9[3];
  90         uint    memc_immr;
  91         uint    memc_pcibr0;
  92         uint    memc_pcibr1;
  93         char    res10[16];
  94         uint    memc_pcimsk0;
  95         uint    memc_pcimsk1;
  96         char    res11[52];
  97 } memctl8260_t;
  98
  99 /* System Integration Timers.
 100 */
 101 typedef struct  sys_int_timers {
 102         char    res1[32];
 103         ushort  sit_tmcntsc;
 104         char    res2[2];
 105         uint    sit_tmcnt;
 106         char    res3[4];
 107         uint    sit_tmcntal;
 108         char    res4[16];
 109         ushort  sit_piscr;
 110         char    res5[2];
 111         uint    sit_pitc;
 112         uint    sit_pitr;
 113         char    res6[94];
 114         char    res7[390];
 115 } sit8260_t;
 116
 117 /* PCI
 118  */
 119 typedef struct pci_config {
 120         uint    pci_omisr;
 121         uint    pci_ominr;
 122         char    res1[8];
 123         uint    pci_ifqpr;
 124         uint    pci_ofqpr;
 125         char    res2[8];
 126         uint    pci_imr0;
 127         uint    pci_imr1;
 128         uint    pci_omr0;
 129         uint    pci_omr1;
 130         uint    pci_odr;
 131         char    res3[4];
 132         uint    pci_idr;
 133         char    res4[20];
 134         uint    pci_imisr;
 135         uint    pci_imimr;
 136         char    res5[24];
 137         uint    pci_ifhpr;
 138         char    res5_2[4];
 139         uint    pci_iftpr;
 140         char    res6[4];
 141         uint    pci_iphpr;
 142         char    res6_2[4];
 143         uint    pci_iptpr;
 144         char    res7[4];
 145         uint    pci_ofhpr;
 146         char    res7_2[4];
 147         uint    pci_oftpr;
 148         char    res8[4];
 149         uint    pci_ophpr;
 150         char    res8_2[4];
 151         uint    pci_optpr;
 152         char    res9[8];
 153         uint    pci_mucr;
 154         char    res10[8];
 155         uint    pci_qbar;
 156         char    res11[12];
 157         uint    pci_dmamr0;
 158         uint    pci_dmasr0;
 159         uint    pci_dmacdar0;
 160         char    res12[4];
 161         uint    pci_dmasar0;
 162         char    res13[4];
 163         uint    pci_dmadar0;
 164         char    res14[4];
 165         uint    pci_dmabcr0;
 166         uint    pci_dmandar0;
 167         char    res15[88];
 168         uint    pci_dmamr1;
 169         uint    pci_dmasr1;
 170         uint    pci_dmacdar1;
 171         char    res16[4];
 172         uint    pci_dmasar1;
 173         char    res17[4];
 174         uint    pci_dmadar1;
 175         char    res18[4];
 176         uint    pci_dmabcr1;
 177         uint    pci_dmandar1;
 178         char    res19[88];
 179         uint    pci_dmamr2;
 180         uint    pci_dmasr2;
 181         uint    pci_dmacdar2;
 182         char    res20[4];
 183         uint    pci_dmasar2;
 184         char    res21[4];
 185         uint    pci_dmadar2;
 186         char    res22[4];
 187         uint    pci_dmabcr2;
 188         uint    pci_dmandar2;
 189         char    res23[88];
 190         uint    pci_dmamr3;
 191         uint    pci_dmasr3;
 192         uint    pci_dmacdar3;
 193         char    res24[4];
 194         uint    pci_dmasar3;
 195         char    res25[4];
 196         uint    pci_dmadar3;
 197         char    res26[4];
 198         uint    pci_dmabcr3;
 199         uint    pci_dmandar3;
 200         char    res27[344];
 201         uint    pci_potar0;
 202         char    res28[4];
 203         uint    pci_pobar0;
 204         char    res29[4];
 205         uint    pci_pocmr0;
 206         char    res30[4];
 207         uint    pci_potar1;
 208         char    res31[4];
 209         uint    pci_pobar1;
 210         char    res32[4];
 211         uint    pci_pocmr1;
 212         char    res33[4];
 213         uint    pci_potar2;
 214         char    res34[4];
 215         uint    pci_pobar2;
 216         char    res35[4];
 217         uint    pci_pocmr2;
 218         char    res36[52];
 219         uint    pci_ptcr;
 220         uint    pci_gpcr;
 221         uint    pci_gcr;
 222         uint    pci_esr;
 223         uint    pci_emr;
 224         uint    pci_ecr;
 225         uint    pci_eacr;
 226         char    res37[4];
 227         uint    pci_edcr;
 228         char    res38[4];
 229         uint    pci_eccr;
 230         char    res39[44];
 231         uint    pci_pitar1;
 232         char    res40[4];
 233         uint    pci_pibar1;
 234         char    res41[4];
 235         uint    pci_picmr1;
 236         char    res42[4];
 237         uint    pci_pitar0;
 238         char    res43[4];
 239         uint    pci_pibar0;
 240         char    res44[4];
 241         uint    pci_picmr0;
 242         char    res45[4];
 243         uint    pci_cfg_addr;
 244         uint    pci_cfg_data;
 245         uint    pci_int_ack;
 246         char    res46[756];
 247 }pci8260_t;
 248 #define PISCR_PIRQ_MASK         ((ushort)0xff00)
 249 #define PISCR_PS                ((ushort)0x0080)
 250 #define PISCR_PIE               ((ushort)0x0004)
 251 #define PISCR_PTF               ((ushort)0x0002)
 252 #define PISCR_PTE               ((ushort)0x0001)
 253
 254 /* Interrupt Controller.
 255 */
 256 typedef struct interrupt_controller {
 257         ushort  ic_sicr;
 258         char    res1[2];
 259         uint    ic_sivec;
 260         uint    ic_sipnrh;
 261         uint    ic_sipnrl;
 262         uint    ic_siprr;
 263         uint    ic_scprrh;
 264         uint    ic_scprrl;
 265         uint    ic_simrh;
 266         uint    ic_simrl;
 267         uint    ic_siexr;
 268         char    res2[88];
 269 } intctl8260_t;
 270
 271 /* Clocks and Reset.
 272 */
 273 typedef struct clk_and_reset {
 274         uint    car_sccr;
 275         char    res1[4];
 276         uint    car_scmr;
 277         char    res2[4];
 278         uint    car_rsr;
 279         uint    car_rmr;
 280         char    res[104];
 281 } car8260_t;
 282
 283 /* Input/Output Port control/status registers.
 284  * Names consistent with processor manual, although they are different
 285  * from the original 8xx names.......
 286  */
 287 typedef struct io_port {
 288         uint    iop_pdira;
 289         uint    iop_ppara;
 290         uint    iop_psora;
 291         uint    iop_podra;
 292         uint    iop_pdata;
 293         char    res1[12];
 294         uint    iop_pdirb;
 295         uint    iop_pparb;
 296         uint    iop_psorb;
 297         uint    iop_podrb;
 298         uint    iop_pdatb;
 299         char    res2[12];
 300         uint    iop_pdirc;
 301         uint    iop_pparc;
 302         uint    iop_psorc;
 303         uint    iop_podrc;
 304         uint    iop_pdatc;
 305         char    res3[12];
 306         uint    iop_pdird;
 307         uint    iop_ppard;
 308         uint    iop_psord;
 309         uint    iop_podrd;
 310         uint    iop_pdatd;
 311         char    res4[12];
 312 } iop8260_t;
 313
 314 /* Communication Processor Module Timers
 315 */
 316 typedef struct cpm_timers {
 317         u_char  cpmt_tgcr1;
 318         char    res1[3];
 319         u_char  cpmt_tgcr2;
 320         char    res2[11];
 321         ushort  cpmt_tmr1;
 322         ushort  cpmt_tmr2;
 323         ushort  cpmt_trr1;
 324         ushort  cpmt_trr2;
 325         ushort  cpmt_tcr1;
 326         ushort  cpmt_tcr2;
 327         ushort  cpmt_tcn1;
 328         ushort  cpmt_tcn2;
 329         ushort  cpmt_tmr3;
 330         ushort  cpmt_tmr4;
 331         ushort  cpmt_trr3;
 332         ushort  cpmt_trr4;
 333         ushort  cpmt_tcr3;
 334         ushort  cpmt_tcr4;
 335         ushort  cpmt_tcn3;
 336         ushort  cpmt_tcn4;
 337         ushort  cpmt_ter1;
 338         ushort  cpmt_ter2;
 339         ushort  cpmt_ter3;
 340         ushort  cpmt_ter4;
 341         char    res3[584];
 342 } cpmtimer8260_t;
 343
 344 /* DMA control/status registers.
 345 */
 346 typedef struct sdma_csr {
 347         char    res0[24];
 348         u_char  sdma_sdsr;
 349         char    res1[3];
 350         u_char  sdma_sdmr;
 351         char    res2[3];
 352         u_char  sdma_idsr1;
 353         char    res3[3];
 354         u_char  sdma_idmr1;
 355         char    res4[3];
 356         u_char  sdma_idsr2;
 357         char    res5[3];
 358         u_char  sdma_idmr2;
 359         char    res6[3];
 360         u_char  sdma_idsr3;
 361         char    res7[3];
 362         u_char  sdma_idmr3;
 363         char    res8[3];
 364         u_char  sdma_idsr4;
 365         char    res9[3];
 366         u_char  sdma_idmr4;
 367         char    res10[707];
 368 } sdma8260_t;
 369
 370 /* Fast controllers
 371 */
 372 typedef struct fcc {
 373         uint    fcc_gfmr;
 374         uint    fcc_fpsmr;
 375         ushort  fcc_ftodr;
 376         char    res1[2];
 377         ushort  fcc_fdsr;
 378         char    res2[2];
 379         ushort  fcc_fcce;
 380         char    res3[2];
 381         ushort  fcc_fccm;
 382         char    res4[2];
 383         u_char  fcc_fccs;
 384         char    res5[3];
 385         u_char  fcc_ftirr_phy[4];
 386 } fcc_t;
 387
 388 /* Fast controllers continued
 389  */
 390 typedef struct fcc_c {
 391         uint    fcc_firper;
 392         uint    fcc_firer;
 393         uint    fcc_firsr_hi;
 394         uint    fcc_firsr_lo;
 395         u_char  fcc_gfemr;
 396         char    res1[15];
 397 } fcc_c_t;
 398
 399 /* TC Layer
 400  */
 401 typedef struct tclayer {
 402         ushort  tc_tcmode;
 403         ushort  tc_cdsmr;
 404         ushort  tc_tcer;
 405         ushort  tc_rcc;
 406         ushort  tc_tcmr;
 407         ushort  tc_fcc;
 408         ushort  tc_ccc;
 409         ushort  tc_icc;
 410         ushort  tc_tcc;
 411         ushort  tc_ecc;
 412         char    res1[12];
 413 } tclayer_t;
 414
 415 /* I2C
 416 */
 417 typedef struct i2c {
 418         u_char  i2c_i2mod;
 419         char    res1[3];
 420         u_char  i2c_i2add;
 421         char    res2[3];
 422         u_char  i2c_i2brg;
 423         char    res3[3];
 424         u_char  i2c_i2com;
 425         char    res4[3];
 426         u_char  i2c_i2cer;
 427         char    res5[3];
 428         u_char  i2c_i2cmr;
 429         char    res6[331];
 430 } i2c8260_t;
 431
 432 typedef struct scc {            /* Serial communication channels */
 433         uint    scc_gsmrl;
 434         uint    scc_gsmrh;
 435         ushort  scc_psmr;
 436         char    res1[2];
 437         ushort  scc_todr;
 438         ushort  scc_dsr;
 439         ushort  scc_scce;
 440         char    res2[2];
 441         ushort  scc_sccm;
 442         char    res3;
 443         u_char  scc_sccs;
 444         char    res4[8];
 445 } scc_t;
 446
 447 typedef struct smc {            /* Serial management channels */
 448         char    res1[2];
 449         ushort  smc_smcmr;
 450         char    res2[2];
 451         u_char  smc_smce;
 452         char    res3[3];
 453         u_char  smc_smcm;
 454         char    res4[5];
 455 } smc_t;
 456
 457 /* Serial Peripheral Interface.
 458 */
 459 typedef struct im_spi {
 460         ushort  spi_spmode;
 461         char    res1[4];
 462         u_char  spi_spie;
 463         char    res2[3];
 464         u_char  spi_spim;
 465         char    res3[2];
 466         u_char  spi_spcom;
 467         char    res4[82];
 468 } im_spi_t;
 469
 470 /* CPM Mux.
 471 */
 472 typedef struct cpmux {
 473         u_char  cmx_si1cr;
 474         char    res1;
 475         u_char  cmx_si2cr;
 476         char    res2;
 477         uint    cmx_fcr;
 478         uint    cmx_scr;
 479         u_char  cmx_smr;
 480         char    res3;
 481         ushort  cmx_uar;
 482         char    res4[16];
 483 } cpmux_t;
 484
 485 /* SIRAM control
 486 */
 487 typedef struct siram {
 488         ushort  si_amr;
 489         ushort  si_bmr;
 490         ushort  si_cmr;
 491         ushort  si_dmr;
 492         u_char  si_gmr;
 493         char    res1;
 494         u_char  si_cmdr;
 495         char    res2;
 496         u_char  si_str;
 497         char    res3;
 498         ushort  si_rsr;
 499 } siramctl_t;
 500
 501 typedef struct mcc {
 502         ushort  mcc_mcce;
 503         char    res1[2];
 504         ushort  mcc_mccm;
 505         char    res2[2];
 506         u_char  mcc_mccf;
 507         char    res3[7];
 508 } mcc_t;
 509
 510 typedef struct comm_proc {
 511         uint    cp_cpcr;
 512         uint    cp_rccr;
 513         char    res1[14];
 514         ushort  cp_rter;
 515         char    res2[2];
 516         ushort  cp_rtmr;
 517         ushort  cp_rtscr;
 518         char    res3[2];
 519         uint    cp_rtsr;
 520         char    res4[12];
 521 } cpm8260_t;
 522
 523 /* ...and the whole thing wrapped up....
 524 */
 525 typedef struct immap {
 526         /* Some references are into the unique and known dpram spaces,
 527          * others are from the generic base.
 528          */
 529 #define im_dprambase    im_dpram1
 530         u_char          im_dpram1[16*1024];
 531         char            res1[16*1024];
 532         u_char          im_dpram2[4*1024];
 533         char            res2[8*1024];
 534         u_char          im_dpram3[4*1024];
 535         char            res3[16*1024];
 536
 537         sysconf8260_t   im_siu_conf;    /* SIU Configuration */
 538         memctl8260_t    im_memctl;      /* Memory Controller */
 539         sit8260_t       im_sit;         /* System Integration Timers */
 540         pci8260_t       im_pci;         /* PCI Configuration */
 541         intctl8260_t    im_intctl;      /* Interrupt Controller */
 542         car8260_t       im_clkrst;      /* Clocks and reset */
 543         iop8260_t       im_ioport;      /* IO Port control/status */
 544         cpmtimer8260_t  im_cpmtimer;    /* CPM timers */
 545         sdma8260_t      im_sdma;        /* SDMA control/status */
 546
 547         fcc_t           im_fcc[3];      /* Three FCCs */
 548
 549         char            res4[32];
 550         fcc_c_t         im_fcc_c[3];    /* Continued FCCs */
 551         char            res4a[32];
 552
 553         tclayer_t       im_tclayer[8];  /* Eight TCLayers */
 554         ushort          tc_tcgsr;
 555         ushort          tc_tcger;
 556
 557         /* First set of baud rate generators.
 558         */
 559         char            res4b[236];
 560         uint            im_brgc5;
 561         uint            im_brgc6;
 562         uint            im_brgc7;
 563         uint            im_brgc8;
 564
 565         char            res5[608];
 566
 567         i2c8260_t       im_i2c;         /* I2C control/status */
 568         cpm8260_t       im_cpm;         /* Communication processor */
 569
 570         /* Second set of baud rate generators.
 571         */
 572         uint            im_brgc1;
 573         uint            im_brgc2;
 574         uint            im_brgc3;
 575         uint            im_brgc4;
 576
 577         scc_t           im_scc[4];      /* Four SCCs */
 578         smc_t           im_smc[2];      /* Couple of SMCs */
 579         im_spi_t        im_spi;         /* A SPI */
 580         cpmux_t         im_cpmux;       /* CPM clock route mux */
 581         siramctl_t      im_siramctl1;   /* First SI RAM Control */
 582         mcc_t           im_mcc1;        /* First MCC */
 583         siramctl_t      im_siramctl2;   /* Second SI RAM Control */
 584         mcc_t           im_mcc2;        /* Second MCC */
 585
 586         char            res6[1184];
 587
 588         ushort          im_si1txram[256];
 589         char            res7[512];
 590         ushort          im_si1rxram[256];
 591         char            res8[512];
 592         ushort          im_si2txram[256];
 593         char            res9[512];
 594         ushort          im_si2rxram[256];
 595         char            res10[512];
 596         char            res11[4096];
 597 } immap_t;
 598
 599 #endif /* __IMMAP_82XX__ */