arch/ppc/include/asm/immap_83xx.h

   1 /*
   2  * Copyright 2004-2009 Freescale Semiconductor, Inc.
   3  *
   4  * MPC83xx Internal Memory Map
   5  *
   6  * Contributors:
   7  *      Dave Liu <daveliu@freescale.com>
   8  *      Tanya Jiang <tanya.jiang@freescale.com>
   9  *      Mandy Lavi <mandy.lavi@freescale.com>
  10  *      Eran Liberty <liberty@freescale.com>
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  *
  27  */
  28 #ifndef __IMMAP_83xx__
  29 #define __IMMAP_83xx__
  30
  31 #include <asm/types.h>
  32 #include <asm/fsl_i2c.h>
  33 #include <asm/mpc8xxx_spi.h>
  34 #include <asm/fsl_lbc.h>
  35 #include <asm/fsl_dma.h>
  36
  37 /*
  38  * Local Access Window
  39  */
  40 typedef struct law83xx {
  41         u32 bar;                /* LBIU local access window base address register */
  42         u32 ar;                 /* LBIU local access window attribute register */
  43 } law83xx_t;
  44
  45 /*
  46  * System configuration registers
  47  */
  48 typedef struct sysconf83xx {
  49         u32 immrbar;            /* Internal memory map base address register */
  50         u8 res0[0x04];
  51         u32 altcbar;            /* Alternate configuration base address register */
  52         u8 res1[0x14];
  53         law83xx_t lblaw[4];     /* LBIU local access window */
  54         u8 res2[0x20];
  55         law83xx_t pcilaw[2];    /* PCI local access window */
  56         u8 res3[0x10];
  57         law83xx_t pcielaw[2];   /* PCI Express local access window */
  58         u8 res4[0x10];
  59         law83xx_t ddrlaw[2];    /* DDR local access window */
  60         u8 res5[0x50];
  61         u32 sgprl;              /* System General Purpose Register Low */
  62         u32 sgprh;              /* System General Purpose Register High */
  63         u32 spridr;             /* System Part and Revision ID Register */
  64         u8 res6[0x04];
  65         u32 spcr;               /* System Priority Configuration Register */
  66         u32 sicrl;              /* System I/O Configuration Register Low */
  67         u32 sicrh;              /* System I/O Configuration Register High */
  68         u8 res7[0x04];
  69         u32 sidcr0;             /* System I/O Delay Configuration Register 0 */
  70         u32 sidcr1;             /* System I/O Delay Configuration Register 1 */
  71         u32 ddrcdr;             /* DDR Control Driver Register */
  72         u32 ddrdsr;             /* DDR Debug Status Register */
  73         u32 obir;               /* Output Buffer Impedance Register */
  74         u8 res8[0xC];
  75         u32 pecr1;              /* PCI Express control register 1 */
  76         u32 pecr2;              /* PCI Express control register 2 */
  77         u8 res9[0xB8];
  78 } sysconf83xx_t;
  79
  80 /*
  81  * Watch Dog Timer (WDT) Registers
  82  */
  83 typedef struct wdt83xx {
  84         u8 res0[4];
  85         u32 swcrr;              /* System watchdog control register */
  86         u32 swcnr;              /* System watchdog count register */
  87         u8 res1[2];
  88         u16 swsrr;              /* System watchdog service register */
  89         u8 res2[0xF0];
  90 } wdt83xx_t;
  91
  92 /*
  93  * RTC/PIT Module Registers
  94  */
  95 typedef struct rtclk83xx {
  96         u32 cnr;                /* control register */
  97         u32 ldr;                /* load register */
  98         u32 psr;                /* prescale register */
  99         u32 ctr;                /* counter value field register */
 100         u32 evr;                /* event register */
 101         u32 alr;                /* alarm register */
 102         u8 res0[0xE8];
 103 } rtclk83xx_t;
 104
 105 /*
 106  * Global timer module
 107  */
 108 typedef struct gtm83xx {
 109         u8 cfr1;                /* Timer1/2 Configuration */
 110         u8 res0[3];
 111         u8 cfr2;                /* Timer3/4 Configuration */
 112         u8 res1[10];
 113         u16 mdr1;               /* Timer1 Mode Register */
 114         u16 mdr2;               /* Timer2 Mode Register */
 115         u16 rfr1;               /* Timer1 Reference Register */
 116         u16 rfr2;               /* Timer2 Reference Register */
 117         u16 cpr1;               /* Timer1 Capture Register */
 118         u16 cpr2;               /* Timer2 Capture Register */
 119         u16 cnr1;               /* Timer1 Counter Register */
 120         u16 cnr2;               /* Timer2 Counter Register */
 121         u16 mdr3;               /* Timer3 Mode Register */
 122         u16 mdr4;               /* Timer4 Mode Register */
 123         u16 rfr3;               /* Timer3 Reference Register */
 124         u16 rfr4;               /* Timer4 Reference Register */
 125         u16 cpr3;               /* Timer3 Capture Register */
 126         u16 cpr4;               /* Timer4 Capture Register */
 127         u16 cnr3;               /* Timer3 Counter Register */
 128         u16 cnr4;               /* Timer4 Counter Register */
 129         u16 evr1;               /* Timer1 Event Register */
 130         u16 evr2;               /* Timer2 Event Register */
 131         u16 evr3;               /* Timer3 Event Register */
 132         u16 evr4;               /* Timer4 Event Register */
 133         u16 psr1;               /* Timer1 Prescaler Register */
 134         u16 psr2;               /* Timer2 Prescaler Register */
 135         u16 psr3;               /* Timer3 Prescaler Register */
 136         u16 psr4;               /* Timer4 Prescaler Register */
 137         u8 res[0xC0];
 138 } gtm83xx_t;
 139
 140 /*
 141  * Integrated Programmable Interrupt Controller
 142  */
 143 typedef struct ipic83xx {
 144         u32 sicfr;              /* System Global Interrupt Configuration Register */
 145         u32 sivcr;              /* System Global Interrupt Vector Register */
 146         u32 sipnr_h;            /* System Internal Interrupt Pending Register - High */
 147         u32 sipnr_l;            /* System Internal Interrupt Pending Register - Low */
 148         u32 siprr_a;            /* System Internal Interrupt Group A Priority Register */
 149         u8 res0[8];
 150         u32 siprr_d;            /* System Internal Interrupt Group D Priority Register */
 151         u32 simsr_h;            /* System Internal Interrupt Mask Register - High */
 152         u32 simsr_l;            /* System Internal Interrupt Mask Register - Low */
 153         u8 res1[4];
 154         u32 sepnr;              /* System External Interrupt Pending Register */
 155         u32 smprr_a;            /* System Mixed Interrupt Group A Priority Register */
 156         u32 smprr_b;            /* System Mixed Interrupt Group B Priority Register */
 157         u32 semsr;              /* System External Interrupt Mask Register */
 158         u32 secnr;              /* System External Interrupt Control Register */
 159         u32 sersr;              /* System Error Status Register */
 160         u32 sermr;              /* System Error Mask Register */
 161         u32 sercr;              /* System Error Control Register */
 162         u8 res2[4];
 163         u32 sifcr_h;            /* System Internal Interrupt Force Register - High */
 164         u32 sifcr_l;            /* System Internal Interrupt Force Register - Low */
 165         u32 sefcr;              /* System External Interrupt Force Register */
 166         u32 serfr;              /* System Error Force Register */
 167         u32 scvcr;              /* System Critical Interrupt Vector Register */
 168         u32 smvcr;              /* System Management Interrupt Vector Register */
 169         u8 res3[0x98];
 170 } ipic83xx_t;
 171
 172 /*
 173  * System Arbiter Registers
 174  */
 175 typedef struct arbiter83xx {
 176         u32 acr;                /* Arbiter Configuration Register */
 177         u32 atr;                /* Arbiter Timers Register */
 178         u8 res[4];
 179         u32 aer;                /* Arbiter Event Register */
 180         u32 aidr;               /* Arbiter Interrupt Definition Register */
 181         u32 amr;                /* Arbiter Mask Register */
 182         u32 aeatr;              /* Arbiter Event Attributes Register */
 183         u32 aeadr;              /* Arbiter Event Address Register */
 184         u32 aerr;               /* Arbiter Event Response Register */
 185         u8 res1[0xDC];
 186 } arbiter83xx_t;
 187
 188 /*
 189  * Reset Module
 190  */
 191 typedef struct reset83xx {
 192         u32 rcwl;               /* Reset Configuration Word Low Register */
 193         u32 rcwh;               /* Reset Configuration Word High Register */
 194         u8 res0[8];
 195         u32 rsr;                /* Reset Status Register */
 196         u32 rmr;                /* Reset Mode Register */
 197         u32 rpr;                /* Reset protection Register */
 198         u32 rcr;                /* Reset Control Register */
 199         u32 rcer;               /* Reset Control Enable Register */
 200         u8 res1[0xDC];
 201 } reset83xx_t;
 202
 203 /*
 204  * Clock Module
 205  */
 206 typedef struct clk83xx {
 207         u32 spmr;               /* system PLL mode Register */
 208         u32 occr;               /* output clock control Register */
 209         u32 sccr;               /* system clock control Register */
 210         u8 res0[0xF4];
 211 } clk83xx_t;
 212
 213 /*
 214  * Power Management Control Module
 215  */
 216 typedef struct pmc83xx {
 217         u32 pmccr;              /* PMC Configuration Register */
 218         u32 pmcer;              /* PMC Event Register */
 219         u32 pmcmr;              /* PMC Mask Register */
 220         u32 pmccr1;             /* PMC Configuration Register 1 */
 221         u32 pmccr2;             /* PMC Configuration Register 2 */
 222         u8 res0[0xEC];
 223 } pmc83xx_t;
 224
 225 /*
 226  * General purpose I/O module
 227  */
 228 typedef struct gpio83xx {
 229         u32 dir;                /* direction register */
 230         u32 odr;                /* open drain register */
 231         u32 dat;                /* data register */
 232         u32 ier;                /* interrupt event register */
 233         u32 imr;                /* interrupt mask register */
 234         u32 icr;                /* external interrupt control register */
 235         u8 res0[0xE8];
 236 } gpio83xx_t;
 237
 238 /*
 239  * QE Ports Interrupts Registers
 240  */
 241 typedef struct qepi83xx {
 242         u8 res0[0xC];
 243         u32 qepier;             /* QE Ports Interrupt Event Register */
 244         u32 qepimr;             /* QE Ports Interrupt Mask Register */
 245         u32 qepicr;             /* QE Ports Interrupt Control Register */
 246         u8 res1[0xE8];
 247 } qepi83xx_t;
 248
 249 /*
 250  * QE Parallel I/O Ports
 251  */
 252 typedef struct gpio_n {
 253         u32 podr;               /* Open Drain Register */
 254         u32 pdat;               /* Data Register */
 255         u32 dir1;               /* direction register 1 */
 256         u32 dir2;               /* direction register 2 */
 257         u32 ppar1;              /* Pin Assignment Register 1 */
 258         u32 ppar2;              /* Pin Assignment Register 2 */
 259 } gpio_n_t;
 260
 261 typedef struct qegpio83xx {
 262         gpio_n_t ioport[0x7];
 263         u8 res0[0x358];
 264 } qepio83xx_t;
 265
 266 /*
 267  * QE Secondary Bus Access Windows
 268  */
 269 typedef struct qesba83xx {
 270         u32 lbmcsar;            /* Local bus memory controller start address */
 271         u32 sdmcsar;            /* Secondary DDR memory controller start address */
 272         u8 res0[0x38];
 273         u32 lbmcear;            /* Local bus memory controller end address */
 274         u32 sdmcear;            /* Secondary DDR memory controller end address */
 275         u8 res1[0x38];
 276         u32 lbmcar;             /* Local bus memory controller attributes */
 277         u32 sdmcar;             /* Secondary DDR memory controller attributes */
 278         u8 res2[0x378];
 279 } qesba83xx_t;
 280
 281 /*
 282  * DDR Memory Controller Memory Map
 283  */
 284 typedef struct ddr_cs_bnds {
 285         u32 csbnds;
 286         u8 res0[4];
 287 } ddr_cs_bnds_t;
 288
 289 typedef struct ddr83xx {
 290         ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
 291         u8 res0[0x60];
 292         u32 cs_config[4];       /* Chip Select x Configuration */
 293         u8 res1[0x70];
 294         u32 timing_cfg_3;       /* SDRAM Timing Configuration 3 */
 295         u32 timing_cfg_0;       /* SDRAM Timing Configuration 0 */
 296         u32 timing_cfg_1;       /* SDRAM Timing Configuration 1 */
 297         u32 timing_cfg_2;       /* SDRAM Timing Configuration 2 */
 298         u32 sdram_cfg;          /* SDRAM Control Configuration */
 299         u32 sdram_cfg2;         /* SDRAM Control Configuration 2 */
 300         u32 sdram_mode;         /* SDRAM Mode Configuration */
 301         u32 sdram_mode2;        /* SDRAM Mode Configuration 2 */
 302         u32 sdram_md_cntl;      /* SDRAM Mode Control */
 303         u32 sdram_interval;     /* SDRAM Interval Configuration */
 304         u32 ddr_data_init;      /* SDRAM Data Initialization */
 305         u8 res2[4];
 306         u32 sdram_clk_cntl;     /* SDRAM Clock Control */
 307         u8 res3[0x14];
 308         u32 ddr_init_addr;      /* DDR training initialization address */
 309         u32 ddr_init_ext_addr;  /* DDR training initialization extended address */
 310         u8 res4[0xAA8];
 311         u32 ddr_ip_rev1;        /* DDR IP block revision 1 */
 312         u32 ddr_ip_rev2;        /* DDR IP block revision 2 */
 313         u8 res5[0x200];
 314         u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */
 315         u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */
 316         u32 ecc_err_inject;     /* Memory Data Path Error Injection Mask ECC */
 317         u8 res6[0x14];
 318         u32 capture_data_hi;    /* Memory Data Path Read Capture High */
 319         u32 capture_data_lo;    /* Memory Data Path Read Capture Low */
 320         u32 capture_ecc;        /* Memory Data Path Read Capture ECC */
 321         u8 res7[0x14];
 322         u32 err_detect;         /* Memory Error Detect */
 323         u32 err_disable;        /* Memory Error Disable */
 324         u32 err_int_en;         /* Memory Error Interrupt Enable */
 325         u32 capture_attributes; /* Memory Error Attributes Capture */
 326         u32 capture_address;    /* Memory Error Address Capture */
 327         u32 capture_ext_address;/* Memory Error Extended Address Capture */
 328         u32 err_sbe;            /* Memory Single-Bit ECC Error Management */
 329         u8 res8[0xA4];
 330         u32 debug_reg;
 331         u8 res9[0xFC];
 332 } ddr83xx_t;
 333
 334 /*
 335  * DUART
 336  */
 337 typedef struct duart83xx {
 338         u8 urbr_ulcr_udlb;      /* combined register for URBR, UTHR and UDLB */
 339         u8 uier_udmb;           /* combined register for UIER and UDMB */
 340         u8 uiir_ufcr_uafr;      /* combined register for UIIR, UFCR and UAFR */
 341         u8 ulcr;                /* line control register */
 342         u8 umcr;                /* MODEM control register */
 343         u8 ulsr;                /* line status register */
 344         u8 umsr;                /* MODEM status register */
 345         u8 uscr;                /* scratch register */
 346         u8 res0[8];
 347         u8 udsr;                /* DMA status register */
 348         u8 res1[3];
 349         u8 res2[0xEC];
 350 } duart83xx_t;
 351
 352 /*
 353  * DMA/Messaging Unit
 354  */
 355 typedef struct dma83xx {
 356         u32 res0[0xC];          /* 0x0-0x29 reseverd */
 357         u32 omisr;              /* 0x30 Outbound message interrupt status register */
 358         u32 omimr;              /* 0x34 Outbound message interrupt mask register */
 359         u32 res1[0x6];          /* 0x38-0x49 reserved */
 360         u32 imr0;               /* 0x50 Inbound message register 0 */
 361         u32 imr1;               /* 0x54 Inbound message register 1 */
 362         u32 omr0;               /* 0x58 Outbound message register 0 */
 363         u32 omr1;               /* 0x5C Outbound message register 1 */
 364         u32 odr;                /* 0x60 Outbound doorbell register */
 365         u32 res2;               /* 0x64-0x67 reserved */
 366         u32 idr;                /* 0x68 Inbound doorbell register */
 367         u32 res3[0x5];          /* 0x6C-0x79 reserved */
 368         u32 imisr;              /* 0x80 Inbound message interrupt status register */
 369         u32 imimr;              /* 0x84 Inbound message interrupt mask register */
 370         u32 res4[0x1E];         /* 0x88-0x99 reserved */
 371         struct fsl_dma dma[4];
 372 } dma83xx_t;
 373
 374 /*
 375  * PCI Software Configuration Registers
 376  */
 377 typedef struct pciconf83xx {
 378         u32 config_address;
 379         u32 config_data;
 380         u32 int_ack;
 381         u8 res[116];
 382 } pciconf83xx_t;
 383
 384 /*
 385  * PCI Outbound Translation Register
 386  */
 387 typedef struct pci_outbound_window {
 388         u32 potar;
 389         u8 res0[4];
 390         u32 pobar;
 391         u8 res1[4];
 392         u32 pocmr;
 393         u8 res2[4];
 394 } pot83xx_t;
 395
 396 /*
 397  * Sequencer
 398  */
 399 typedef struct ios83xx {
 400         pot83xx_t pot[6];
 401         u8 res0[0x60];
 402         u32 pmcr;
 403         u8 res1[4];
 404         u32 dtcr;
 405         u8 res2[4];
 406 } ios83xx_t;
 407
 408 /*
 409  * PCI Controller Control and Status Registers
 410  */
 411 typedef struct pcictrl83xx {
 412         u32 esr;
 413         u32 ecdr;
 414         u32 eer;
 415         u32 eatcr;
 416         u32 eacr;
 417         u32 eeacr;
 418         u32 edlcr;
 419         u32 edhcr;
 420         u32 gcr;
 421         u32 ecr;
 422         u32 gsr;
 423         u8 res0[12];
 424         u32 pitar2;
 425         u8 res1[4];
 426         u32 pibar2;
 427         u32 piebar2;
 428         u32 piwar2;
 429         u8 res2[4];
 430         u32 pitar1;
 431         u8 res3[4];
 432         u32 pibar1;
 433         u32 piebar1;
 434         u32 piwar1;
 435         u8 res4[4];
 436         u32 pitar0;
 437         u8 res5[4];
 438         u32 pibar0;
 439         u8 res6[4];
 440         u32 piwar0;
 441         u8 res7[132];
 442 } pcictrl83xx_t;
 443
 444 /*
 445  * USB
 446  */
 447 typedef struct usb83xx {
 448         u8 fixme[0x1000];
 449 } usb83xx_t;
 450
 451 /*
 452  * TSEC
 453  */
 454 typedef struct tsec83xx {
 455         u8 fixme[0x1000];
 456 } tsec83xx_t;
 457
 458 /*
 459  * Security
 460  */
 461 typedef struct security83xx {
 462         u8 fixme[0x10000];
 463 } security83xx_t;
 464
 465 /*
 466  *  PCI Express
 467  */
 468 struct pex_inbound_window {
 469         u32 ar;
 470         u32 tar;
 471         u32 barl;
 472         u32 barh;
 473 };
 474
 475 struct pex_outbound_window {
 476         u32 ar;
 477         u32 bar;
 478         u32 tarl;
 479         u32 tarh;
 480 };
 481
 482 struct pex_csb_bridge {
 483         u32 pex_csb_ver;
 484         u32 pex_csb_cab;
 485         u32 pex_csb_ctrl;
 486         u8 res0[8];
 487         u32 pex_dms_dstmr;
 488         u8 res1[4];
 489         u32 pex_cbs_stat;
 490         u8 res2[0x20];
 491         u32 pex_csb_obctrl;
 492         u32 pex_csb_obstat;
 493         u8 res3[0x98];
 494         u32 pex_csb_ibctrl;
 495         u32 pex_csb_ibstat;
 496         u8 res4[0xb8];
 497         u32 pex_wdma_ctrl;
 498         u32 pex_wdma_addr;
 499         u32 pex_wdma_stat;
 500         u8 res5[0x94];
 501         u32 pex_rdma_ctrl;
 502         u32 pex_rdma_addr;
 503         u32 pex_rdma_stat;
 504         u8 res6[0xd4];
 505         u32 pex_ombcr;
 506         u32 pex_ombdr;
 507         u8 res7[0x38];
 508         u32 pex_imbcr;
 509         u32 pex_imbdr;
 510         u8 res8[0x38];
 511         u32 pex_int_enb;
 512         u32 pex_int_stat;
 513         u32 pex_int_apio_vec1;
 514         u32 pex_int_apio_vec2;
 515         u8 res9[0x10];
 516         u32 pex_int_ppio_vec1;
 517         u32 pex_int_ppio_vec2;
 518         u32 pex_int_wdma_vec1;
 519         u32 pex_int_wdma_vec2;
 520         u32 pex_int_rdma_vec1;
 521         u32 pex_int_rdma_vec2;
 522         u32 pex_int_misc_vec;
 523         u8 res10[4];
 524         u32 pex_int_axi_pio_enb;
 525         u32 pex_int_axi_wdma_enb;
 526         u32 pex_int_axi_rdma_enb;
 527         u32 pex_int_axi_misc_enb;
 528         u32 pex_int_axi_pio_stat;
 529         u32 pex_int_axi_wdma_stat;
 530         u32 pex_int_axi_rdma_stat;
 531         u32 pex_int_axi_misc_stat;
 532         u8 res11[0xa0];
 533         struct pex_outbound_window pex_outbound_win[4];
 534         u8 res12[0x100];
 535         u32 pex_epiwtar0;
 536         u32 pex_epiwtar1;
 537         u32 pex_epiwtar2;
 538         u32 pex_epiwtar3;
 539         u8 res13[0x70];
 540         struct pex_inbound_window pex_inbound_win[4];
 541 };
 542
 543 typedef struct pex83xx {
 544         u8 pex_cfg_header[0x404];
 545         u32 pex_ltssm_stat;
 546         u8 res0[0x30];
 547         u32 pex_ack_replay_timeout;
 548         u8 res1[4];
 549         u32 pex_gclk_ratio;
 550         u8 res2[0xc];
 551         u32 pex_pm_timer;
 552         u32 pex_pme_timeout;
 553         u8 res3[4];
 554         u32 pex_aspm_req_timer;
 555         u8 res4[0x18];
 556         u32 pex_ssvid_update;
 557         u8 res5[0x34];
 558         u32 pex_cfg_ready;
 559         u8 res6[0x24];
 560         u32 pex_bar_sizel;
 561         u8 res7[4];
 562         u32 pex_bar_sel;
 563         u8 res8[0x20];
 564         u32 pex_bar_pf;
 565         u8 res9[0x88];
 566         u32 pex_pme_to_ack_tor;
 567         u8 res10[0xc];
 568         u32 pex_ss_intr_mask;
 569         u8 res11[0x25c];
 570         struct pex_csb_bridge bridge;
 571         u8 res12[0x160];
 572 } pex83xx_t;
 573
 574 /*
 575  * SATA
 576  */
 577 typedef struct sata83xx {
 578         u8 fixme[0x1000];
 579 } sata83xx_t;
 580
 581 /*
 582  * eSDHC
 583  */
 584 typedef struct sdhc83xx {
 585         u8 fixme[0x1000];
 586 } sdhc83xx_t;
 587
 588 /*
 589  * SerDes
 590  */
 591 typedef struct serdes83xx {
 592         u8 fixme[0x100];
 593 } serdes83xx_t;
 594
 595 /*
 596  * On Chip ROM
 597  */
 598 typedef struct rom83xx {
 599         u8 mem[0x10000];
 600 } rom83xx_t;
 601
 602 /*
 603  * TDM
 604  */
 605 typedef struct tdm83xx {
 606         u8 fixme[0x200];
 607 } tdm83xx_t;
 608
 609 /*
 610  * TDM DMAC
 611  */
 612 typedef struct tdmdmac83xx {
 613         u8 fixme[0x2000];
 614 } tdmdmac83xx_t;
 615
 616 #if defined(CONFIG_MPC834x)
 617 typedef struct immap {
 618         sysconf83xx_t           sysconf;        /* System configuration */
 619         wdt83xx_t               wdt;            /* Watch Dog Timer (WDT) Registers */
 620         rtclk83xx_t             rtc;            /* Real Time Clock Module Registers */
 621         rtclk83xx_t             pit;            /* Periodic Interval Timer */
 622         gtm83xx_t               gtm[2];         /* Global Timers Module */
 623         ipic83xx_t              ipic;           /* Integrated Programmable Interrupt Controller */
 624         arbiter83xx_t           arbiter;        /* System Arbiter Registers */
 625         reset83xx_t             reset;          /* Reset Module */
 626         clk83xx_t               clk;            /* System Clock Module */
 627         pmc83xx_t               pmc;            /* Power Management Control Module */
 628         gpio83xx_t              gpio[2];        /* General purpose I/O module */
 629         u8                      res0[0x200];
 630         u8                      dll_ddr[0x100];
 631         u8                      dll_lbc[0x100];
 632         u8                      res1[0xE00];
 633         ddr83xx_t               ddr;            /* DDR Memory Controller Memory */
 634         fsl_i2c_t               i2c[2];         /* I2C Controllers */
 635         u8                      res2[0x1300];
 636         duart83xx_t             duart[2];       /* DUART */
 637         u8                      res3[0x900];
 638         fsl_lbus_t              lbus;   /* Local Bus Controller Registers */
 639         u8                      res4[0x1000];
 640         spi8xxx_t               spi;            /* Serial Peripheral Interface */
 641         dma83xx_t               dma;            /* DMA */
 642         pciconf83xx_t           pci_conf[2];    /* PCI Software Configuration Registers */
 643         ios83xx_t               ios;            /* Sequencer */
 644         pcictrl83xx_t           pci_ctrl[2];    /* PCI Controller Control and Status Registers */
 645         u8                      res5[0x19900];
 646         usb83xx_t               usb[2];
 647         tsec83xx_t              tsec[2];
 648         u8                      res6[0xA000];
 649         security83xx_t          security;
 650         u8                      res7[0xC0000];
 651 } immap_t;
 652
 653 #ifdef CONFIG_HAS_FSL_MPH_USB
 654 #define CONFIG_SYS_MPC83xx_USB_OFFSET  0x22000  /* use the MPH controller */
 655 #else
 656 #define CONFIG_SYS_MPC83xx_USB_OFFSET  0x23000  /* use the DR controller */
 657 #endif
 658
 659 #elif defined(CONFIG_MPC8313)
 660 typedef struct immap {
 661         sysconf83xx_t           sysconf;        /* System configuration */
 662         wdt83xx_t               wdt;            /* Watch Dog Timer (WDT) Registers */
 663         rtclk83xx_t             rtc;            /* Real Time Clock Module Registers */
 664         rtclk83xx_t             pit;            /* Periodic Interval Timer */
 665         gtm83xx_t               gtm[2];         /* Global Timers Module */
 666         ipic83xx_t              ipic;           /* Integrated Programmable Interrupt Controller */
 667         arbiter83xx_t           arbiter;        /* System Arbiter Registers */
 668         reset83xx_t             reset;          /* Reset Module */
 669         clk83xx_t               clk;            /* System Clock Module */
 670         pmc83xx_t               pmc;            /* Power Management Control Module */
 671         gpio83xx_t              gpio[1];        /* General purpose I/O module */
 672         u8                      res0[0x1300];
 673         ddr83xx_t               ddr;            /* DDR Memory Controller Memory */
 674         fsl_i2c_t               i2c[2];         /* I2C Controllers */
 675         u8                      res1[0x1300];
 676         duart83xx_t             duart[2];       /* DUART */
 677         u8                      res2[0x900];
 678         fsl_lbus_t              lbus;   /* Local Bus Controller Registers */
 679         u8                      res3[0x1000];
 680         spi8xxx_t               spi;            /* Serial Peripheral Interface */
 681         dma83xx_t               dma;            /* DMA */
 682         pciconf83xx_t           pci_conf[1];    /* PCI Software Configuration Registers */
 683         u8                      res4[0x80];
 684         ios83xx_t               ios;            /* Sequencer */
 685         pcictrl83xx_t           pci_ctrl[1];    /* PCI Controller Control and Status Registers */
 686         u8                      res5[0x1aa00];
 687         usb83xx_t               usb[1];
 688         tsec83xx_t              tsec[2];
 689         u8                      res6[0xA000];
 690         security83xx_t          security;
 691         u8                      res7[0xC0000];
 692 } immap_t;
 693
 694 #elif defined(CONFIG_MPC8315)
 695 typedef struct immap {
 696         sysconf83xx_t           sysconf;        /* System configuration */
 697         wdt83xx_t               wdt;            /* Watch Dog Timer (WDT) Registers */
 698         rtclk83xx_t             rtc;            /* Real Time Clock Module Registers */
 699         rtclk83xx_t             pit;            /* Periodic Interval Timer */
 700         gtm83xx_t               gtm[2];         /* Global Timers Module */
 701         ipic83xx_t              ipic;           /* Integrated Programmable Interrupt Controller */
 702         arbiter83xx_t           arbiter;        /* System Arbiter Registers */
 703         reset83xx_t             reset;          /* Reset Module */
 704         clk83xx_t               clk;            /* System Clock Module */
 705         pmc83xx_t               pmc;            /* Power Management Control Module */
 706         gpio83xx_t              gpio[1];        /* General purpose I/O module */
 707         u8                      res0[0x1300];
 708         ddr83xx_t               ddr;            /* DDR Memory Controller Memory */
 709         fsl_i2c_t               i2c[2];         /* I2C Controllers */
 710         u8                      res1[0x1300];
 711         duart83xx_t             duart[2];       /* DUART */
 712         u8                      res2[0x900];
 713         fsl_lbus_t              lbus;   /* Local Bus Controller Registers */
 714         u8                      res3[0x1000];
 715         spi8xxx_t               spi;            /* Serial Peripheral Interface */
 716         dma83xx_t               dma;            /* DMA */
 717         pciconf83xx_t           pci_conf[1];    /* PCI Software Configuration Registers */
 718         u8                      res4[0x80];
 719         ios83xx_t               ios;            /* Sequencer */
 720         pcictrl83xx_t           pci_ctrl[1];    /* PCI Controller Control and Status Registers */
 721         u8                      res5[0xa00];
 722         pex83xx_t               pciexp[2];      /* PCI Express Controller */
 723         u8                      res6[0xb000];
 724         tdm83xx_t               tdm;            /* TDM Controller */
 725         u8                      res7[0x1e00];
 726         sata83xx_t              sata[2];        /* SATA Controller */
 727         u8                      res8[0x9000];
 728         usb83xx_t               usb[1];         /* USB DR Controller */
 729         tsec83xx_t              tsec[2];
 730         u8                      res9[0x6000];
 731         tdmdmac83xx_t           tdmdmac;        /* TDM DMAC */
 732         u8                      res10[0x2000];
 733         security83xx_t          security;
 734         u8                      res11[0xA3000];
 735         serdes83xx_t            serdes[1];      /* SerDes Registers */
 736         u8                      res12[0x1CF00];
 737 } immap_t;
 738
 739 #elif defined(CONFIG_MPC837x)
 740 typedef struct immap {
 741         sysconf83xx_t           sysconf;        /* System configuration */
 742         wdt83xx_t               wdt;            /* Watch Dog Timer (WDT) Registers */
 743         rtclk83xx_t             rtc;            /* Real Time Clock Module Registers */
 744         rtclk83xx_t             pit;            /* Periodic Interval Timer */
 745         gtm83xx_t               gtm[2];         /* Global Timers Module */
 746         ipic83xx_t              ipic;           /* Integrated Programmable Interrupt Controller */
 747         arbiter83xx_t           arbiter;        /* System Arbiter Registers */
 748         reset83xx_t             reset;          /* Reset Module */
 749         clk83xx_t               clk;            /* System Clock Module */
 750         pmc83xx_t               pmc;            /* Power Management Control Module */
 751         gpio83xx_t              gpio[2];        /* General purpose I/O module */
 752         u8                      res0[0x1200];
 753         ddr83xx_t               ddr;            /* DDR Memory Controller Memory */
 754         fsl_i2c_t               i2c[2];         /* I2C Controllers */
 755         u8                      res1[0x1300];
 756         duart83xx_t             duart[2];       /* DUART */
 757         u8                      res2[0x900];
 758         fsl_lbus_t              lbus;   /* Local Bus Controller Registers */
 759         u8                      res3[0x1000];
 760         spi8xxx_t               spi;            /* Serial Peripheral Interface */
 761         dma83xx_t               dma;            /* DMA */
 762         pciconf83xx_t           pci_conf[1];    /* PCI Software Configuration Registers */
 763         u8                      res4[0x80];
 764         ios83xx_t               ios;            /* Sequencer */
 765         pcictrl83xx_t           pci_ctrl[1];    /* PCI Controller Control and Status Registers */
 766         u8                      res5[0xa00];
 767         pex83xx_t               pciexp[2];      /* PCI Express Controller */
 768         u8                      res6[0xd000];
 769         sata83xx_t              sata[4];        /* SATA Controller */
 770         u8                      res7[0x7000];
 771         usb83xx_t               usb[1];         /* USB DR Controller */
 772         tsec83xx_t              tsec[2];
 773         u8                      res8[0x8000];
 774         sdhc83xx_t              sdhc;           /* SDHC Controller */
 775         u8                      res9[0x1000];
 776         security83xx_t          security;
 777         u8                      res10[0xA3000];
 778         serdes83xx_t            serdes[2];      /* SerDes Registers */
 779         u8                      res11[0xCE00];
 780         rom83xx_t               rom;            /* On Chip ROM */
 781 } immap_t;
 782
 783 #elif defined(CONFIG_MPC8360)
 784 typedef struct immap {
 785         sysconf83xx_t           sysconf;        /* System configuration */
 786         wdt83xx_t               wdt;            /* Watch Dog Timer (WDT) Registers */
 787         rtclk83xx_t             rtc;            /* Real Time Clock Module Registers */
 788         rtclk83xx_t             pit;            /* Periodic Interval Timer */
 789         u8                      res0[0x200];
 790         ipic83xx_t              ipic;           /* Integrated Programmable Interrupt Controller */
 791         arbiter83xx_t           arbiter;        /* System Arbiter Registers */
 792         reset83xx_t             reset;          /* Reset Module */
 793         clk83xx_t               clk;            /* System Clock Module */
 794         pmc83xx_t               pmc;            /* Power Management Control Module */
 795         qepi83xx_t              qepi;           /* QE Ports Interrupts Registers */
 796         u8                      res1[0x300];
 797         u8                      dll_ddr[0x100];
 798         u8                      dll_lbc[0x100];
 799         u8                      res2[0x200];
 800         qepio83xx_t             qepio;          /* QE Parallel I/O ports */
 801         qesba83xx_t             qesba;          /* QE Secondary Bus Access Windows */
 802         u8                      res3[0x400];
 803         ddr83xx_t               ddr;            /* DDR Memory Controller Memory */
 804         fsl_i2c_t               i2c[2];         /* I2C Controllers */
 805         u8                      res4[0x1300];
 806         duart83xx_t             duart[2];       /* DUART */
 807         u8                      res5[0x900];
 808         fsl_lbus_t              lbus;   /* Local Bus Controller Registers */
 809         u8                      res6[0x2000];
 810         dma83xx_t               dma;            /* DMA */
 811         pciconf83xx_t           pci_conf[1];    /* PCI Software Configuration Registers */
 812         u8                      res7[128];
 813         ios83xx_t               ios;            /* Sequencer (IOS) */
 814         pcictrl83xx_t           pci_ctrl[1];    /* PCI Controller Control and Status Registers */
 815         u8                      res8[0x4A00];
 816         ddr83xx_t               ddr_secondary;  /* Secondary DDR Memory Controller Memory Map */
 817         u8                      res9[0x22000];
 818         security83xx_t          security;
 819         u8                      res10[0xC0000];
 820         u8                      qe[0x100000];   /* QE block */
 821 } immap_t;
 822
 823 #elif defined(CONFIG_MPC832x)
 824 typedef struct immap {
 825         sysconf83xx_t           sysconf;        /* System configuration */
 826         wdt83xx_t               wdt;            /* Watch Dog Timer (WDT) Registers */
 827         rtclk83xx_t             rtc;            /* Real Time Clock Module Registers */
 828         rtclk83xx_t             pit;            /* Periodic Interval Timer */
 829         gtm83xx_t               gtm[2];         /* Global Timers Module */
 830         ipic83xx_t              ipic;           /* Integrated Programmable Interrupt Controller */
 831         arbiter83xx_t           arbiter;        /* System Arbiter Registers */
 832         reset83xx_t             reset;          /* Reset Module */
 833         clk83xx_t               clk;            /* System Clock Module */
 834         pmc83xx_t               pmc;            /* Power Management Control Module */
 835         qepi83xx_t              qepi;           /* QE Ports Interrupts Registers */
 836         u8                      res0[0x300];
 837         u8                      dll_ddr[0x100];
 838         u8                      dll_lbc[0x100];
 839         u8                      res1[0x200];
 840         qepio83xx_t             qepio;          /* QE Parallel I/O ports */
 841         u8                      res2[0x800];
 842         ddr83xx_t               ddr;            /* DDR Memory Controller Memory */
 843         fsl_i2c_t               i2c[2];         /* I2C Controllers */
 844         u8                      res3[0x1300];
 845         duart83xx_t             duart[2];       /* DUART */
 846         u8                      res4[0x900];
 847         fsl_lbus_t              lbus;   /* Local Bus Controller Registers */
 848         u8                      res5[0x2000];
 849         dma83xx_t               dma;            /* DMA */
 850         pciconf83xx_t           pci_conf[1];    /* PCI Software Configuration Registers */
 851         u8                      res6[128];
 852         ios83xx_t               ios;            /* Sequencer (IOS) */
 853         pcictrl83xx_t           pci_ctrl[1];    /* PCI Controller Control and Status Registers */
 854         u8                      res7[0x27A00];
 855         security83xx_t          security;
 856         u8                      res8[0xC0000];
 857         u8                      qe[0x100000];   /* QE block */
 858 } immap_t;
 859 #endif
 860
 861 #define CONFIG_SYS_MPC83xx_DMA_OFFSET   (0x8000)
 862 #define CONFIG_SYS_MPC83xx_DMA_ADDR     (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
 863 #define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
 864 #define CONFIG_SYS_MPC83xx_ESDHC_ADDR   (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
 865
 866 #ifndef CONFIG_SYS_MPC83xx_USB_OFFSET
 867 #define CONFIG_SYS_MPC83xx_USB_OFFSET  0x23000
 868 #endif
 869 #define CONFIG_SYS_MPC83xx_USB_ADDR \
 870                         (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
 871
 872 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
 873 #define CONFIG_SYS_MDIO1_OFFSET         0x24000
 874
 875 #define TSEC_BASE_ADDR          (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 876 #define MDIO_BASE_ADDR          (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
 877 #endif                          /* __IMMAP_83xx__ */