arch/sh/include/asm/cpu_sh7750.h

   1 /*
   2  * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
   3  *
   4  * SH7750/SH7750S/SH7750R/SH7751/SH7751R
   5  *  Internal I/O register
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #ifndef _ASM_CPU_SH7750_H_
  24 #define _ASM_CPU_SH7750_H_
  25
  26 #ifdef CONFIG_CPU_TYPE_R
  27 #define CACHE_OC_NUM_WAYS     2
  28 #define CCR_CACHE_INIT   0x8000090D     /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */
  29 #else
  30 #define CACHE_OC_NUM_WAYS     1
  31 #define CCR_CACHE_INIT   0x0000090B
  32 #endif
  33
  34 /*      OCN     */
  35 #define PTEH    0xFF000000
  36 #define PTEL    0xFF000004
  37 #define TTB     0xFF000008
  38 #define TEA     0xFF00000C
  39 #define MMUCR   0xFF000010
  40 #define BASRA   0xFF000014
  41 #define BASRB   0xFF000018
  42 #define CCR     0xFF00001C
  43 #define TRA     0xFF000020
  44 #define EXPEVT  0xFF000024
  45 #define INTEVT  0xFF000028
  46 #define PTEA    0xFF000034
  47 #define QACR0   0xFF000038
  48 #define QACR1   0xFF00003C
  49
  50 /*      UBC     */
  51 #define BARA    0xFF200000
  52 #define BAMRA   0xFF200004
  53 #define BBRA    0xFF200008
  54 #define BARB    0xFF20000C
  55 #define BAMRB   0xFF200010
  56 #define BBRB    0xFF200014
  57 #define BDRB    0xFF200018
  58 #define BDMRB   0xFF20001C
  59 #define BRCR    0xFF200020
  60
  61 /*      BSC     */
  62 #define BCR1    0xFF800000
  63 #define BCR2    0xFF800004
  64 #define BCR3    0xFF800050
  65 #define BCR4    0xFE0A00F0
  66 #define WCR1    0xFF800008
  67 #define WCR2    0xFF80000C
  68 #define WCR3    0xFF800010
  69 #define MCR     0xFF800014
  70 #define PCR     0xFF800018
  71 #define RTCSR   0xFF80001C
  72 #define RTCNT   0xFF800020
  73 #define RTCOR   0xFF800024
  74 #define RFCR    0xFF800028
  75 #define PCTRA   0xFF80002C
  76 #define PDTRA   0xFF800030
  77 #define PCTRB   0xFF800040
  78 #define PDTRB   0xFF800044
  79 #define GPIOIC  0xFF800048
  80
  81 /*      DMAC    */
  82 #define SAR0    0xFFA00000
  83 #define DAR0    0xFFA00004
  84 #define DMATCR0 0xFFA00008
  85 #define CHCR0   0xFFA0000C
  86 #define SAR1    0xFFA00010
  87 #define DAR1    0xFFA00014
  88 #define DMATCR1 0xFFA00018
  89 #define CHCR1   0xFFA0001C
  90 #define SAR2    0xFFA00020
  91 #define DAR2    0xFFA00024
  92 #define DMATCR2 0xFFA00028
  93 #define CHCR2   0xFFA0002C
  94 #define SAR3    0xFFA00030
  95 #define DAR3    0xFFA00034
  96 #define DMATCR3 0xFFA00038
  97 #define CHCR3   0xFFA0003C
  98 #define DMAOR   0xFFA00040
  99 #define SAR4    0xFFA00050
 100 #define DAR4    0xFFA00054
 101 #define DMATCR4 0xFFA00058
 102
 103 /*      CPG     */
 104 #define FRQCR   0xFFC00000
 105 #define STBCR   0xFFC00004
 106 #define WTCNT   0xFFC00008
 107 #define WTCSR   0xFFC0000C
 108 #define STBCR2  0xFFC00010
 109
 110 /*      RTC     */
 111 #define R64CNT  0xFFC80000
 112 #define RSECCNT 0xFFC80004
 113 #define RMINCNT 0xFFC80008
 114 #define RHRCNT  0xFFC8000C
 115 #define RWKCNT  0xFFC80010
 116 #define RDAYCNT 0xFFC80014
 117 #define RMONCNT 0xFFC80018
 118 #define RYRCNT  0xFFC8001C
 119 #define RSECAR  0xFFC80020
 120 #define RMINAR  0xFFC80024
 121 #define RHRAR   0xFFC80028
 122 #define RWKAR   0xFFC8002C
 123 #define RDAYAR  0xFFC80030
 124 #define RMONAR  0xFFC80034
 125 #define RCR1    0xFFC80038
 126 #define RCR2    0xFFC8003C
 127 #define RCR3    0xFFC80050
 128 #define RYRAR   0xFFC80054
 129
 130 /*      ICR     */
 131 #define ICR     0xFFD00000
 132 #define IPRA    0xFFD00004
 133 #define IPRB    0xFFD00008
 134 #define IPRC    0xFFD0000C
 135 #define IPRD    0xFFD00010
 136 #define INTPRI  0xFE080000
 137 #define INTREQ  0xFE080020
 138 #define INTMSK  0xFE080040
 139 #define INTMSKCL        0xFE080060
 140
 141 /*      CPG     */
 142 #define CLKSTP          0xFE0A0000
 143 #define CLKSTPCLR       0xFE0A0008
 144
 145 /*      TMU     */
 146 #define TSTR2   0xFE100004
 147 #define TCOR3   0xFE100008
 148 #define TCNT3   0xFE10000C
 149 #define TCR3    0xFE100010
 150 #define TCOR4   0xFE100014
 151 #define TCNT4   0xFE100018
 152 #define TCR4    0xFE10001C
 153 #define TOCR    0xFFD80000
 154 #define TSTR0   0xFFD80004
 155 #define TCOR0   0xFFD80008
 156 #define TCNT0   0xFFD8000C
 157 #define TCR0    0xFFD80010
 158 #define TCOR1   0xFFD80014
 159 #define TCNT1   0xFFD80018
 160 #define TCR1    0xFFD8001C
 161 #define TCOR2   0xFFD80020
 162 #define TCNT2   0xFFD80024
 163 #define TCR2    0xFFD80028
 164 #define TCPR2   0xFFD8002C
 165 #define TSTR    TSTR0
 166
 167 /*      SCI     */
 168 #define SCSMR1  0xFFE00000
 169 #define SCBRR1  0xFFE00004
 170 #define SCSCR1  0xFFE00008
 171 #define SCTDR1  0xFFE0000C
 172 #define SCSSR1  0xFFE00010
 173 #define SCRDR1  0xFFE00014
 174 #define SCSCMR1 0xFFE00018
 175 #define SCSPTR1 0xFFE0001C
 176 #define SCF0_BASE       SCSMR1
 177
 178 /*      SCIF    */
 179 #define SCSMR2  0xFFE80000
 180 #define SCBRR2  0xFFE80004
 181 #define SCSCR2  0xFFE80008
 182 #define SCFTDR2 0xFFE8000C
 183 #define SCFSR2  0xFFE80010
 184 #define SCFRDR2 0xFFE80014
 185 #define SCFCR2  0xFFE80018
 186 #define SCFDR2  0xFFE8001C
 187 #define SCSPTR2 0xFFE80020
 188 #define SCLSR2  0xFFE80024
 189 #define SCIF1_BASE      SCSMR2
 190
 191 /*      H-UDI   */
 192 #define SDIR    0xFFF00000
 193 #define SDDR    0xFFF00008
 194 #define SDINT   0xFFF00014
 195
 196 #endif  /* _ASM_CPU_SH7750_H_ */