arch/sh/include/asm/cpu_sh7785.h

   1 #ifndef _ASM_CPU_SH7785_H_
   2 #define _ASM_CPU_SH7785_H_
   3
   4 /*
   5  * Copyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
   6  * Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com>
   7  * Copyright (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #define CACHE_OC_NUM_WAYS       1
  13 #define CCR_CACHE_INIT          0x0000090b
  14
  15 /*      Exceptions      */
  16 #define TRA             0xFF000020
  17 #define EXPEVT  0xFF000024
  18 #define INTEVT  0xFF000028
  19
  20 /* Cache Controller */
  21 #define CCR     0xFF00001C
  22 #define QACR0   0xFF000038
  23 #define QACR1   0xFF00003C
  24 #define RAMCR   0xFF000074
  25
  26 /* Watchdog Timer and Reset */
  27 #define WTCNT   WDTCNT
  28 #define WDTST   0xFFCC0000
  29 #define WDTCSR  0xFFCC0004
  30 #define WDTBST  0xFFCC0008
  31 #define WDTCNT  0xFFCC0010
  32 #define WDTBCNT 0xFFCC0018
  33
  34 /* Timer Unit */
  35 #define TMU_BASE        0xFFD80000
  36
  37 /* Serial Communication Interface with FIFO */
  38 #define SCIF1_BASE      0xffeb0000
  39
  40 /* LBSC */
  41 #define MMSELR          0xfc400020
  42 #define LBSC_BASE       0xff800000
  43 #define BCR             (LBSC_BASE + 0x1000)
  44 #define CS0BCR          (LBSC_BASE + 0x2000)
  45 #define CS1BCR          (LBSC_BASE + 0x2010)
  46 #define CS2BCR          (LBSC_BASE + 0x2020)
  47 #define CS3BCR          (LBSC_BASE + 0x2030)
  48 #define CS4BCR          (LBSC_BASE + 0x2040)
  49 #define CS5BCR          (LBSC_BASE + 0x2050)
  50 #define CS6BCR          (LBSC_BASE + 0x2060)
  51 #define CS0WCR          (LBSC_BASE + 0x2008)
  52 #define CS1WCR          (LBSC_BASE + 0x2018)
  53 #define CS2WCR          (LBSC_BASE + 0x2028)
  54 #define CS3WCR          (LBSC_BASE + 0x2038)
  55 #define CS4WCR          (LBSC_BASE + 0x2048)
  56 #define CS5WCR          (LBSC_BASE + 0x2058)
  57 #define CS6WCR          (LBSC_BASE + 0x2068)
  58 #define CS5PCR          (LBSC_BASE + 0x2070)
  59 #define CS6PCR          (LBSC_BASE + 0x2080)
  60
  61 /* PCI  Controller */
  62 #define SH7780_PCIECR           0xFE000008
  63 #define SH7780_PCIVID           0xFE040000
  64 #define SH7780_PCIDID           0xFE040002
  65 #define SH7780_PCICMD           0xFE040004
  66 #define SH7780_PCISTATUS        0xFE040006
  67 #define SH7780_PCIRID           0xFE040008
  68 #define SH7780_PCIPIF           0xFE040009
  69 #define SH7780_PCISUB           0xFE04000A
  70 #define SH7780_PCIBCC           0xFE04000B
  71 #define SH7780_PCICLS           0xFE04000C
  72 #define SH7780_PCILTM           0xFE04000D
  73 #define SH7780_PCIHDR           0xFE04000E
  74 #define SH7780_PCIBIST          0xFE04000F
  75 #define SH7780_PCIIBAR          0xFE040010
  76 #define SH7780_PCIMBAR0         0xFE040014
  77 #define SH7780_PCIMBAR1         0xFE040018
  78 #define SH7780_PCISVID          0xFE04002C
  79 #define SH7780_PCISID           0xFE04002E
  80 #define SH7780_PCICP            0xFE040034
  81 #define SH7780_PCIINTLINE       0xFE04003C
  82 #define SH7780_PCIINTPIN        0xFE04003D
  83 #define SH7780_PCIMINGNT        0xFE04003E
  84 #define SH7780_PCIMAXLAT        0xFE04003F
  85 #define SH7780_PCICID           0xFE040040
  86 #define SH7780_PCINIP           0xFE040041
  87 #define SH7780_PCIPMC           0xFE040042
  88 #define SH7780_PCIPMCSR         0xFE040044
  89 #define SH7780_PCIPMCSRBSE      0xFE040046
  90 #define SH7780_PCI_CDD          0xFE040047
  91 #define SH7780_PCICR            0xFE040100
  92 #define SH7780_PCILSR0          0xFE040104
  93 #define SH7780_PCILSR1          0xFE040108
  94 #define SH7780_PCILAR0          0xFE04010C
  95 #define SH7780_PCILAR1          0xFE040110
  96 #define SH7780_PCIIR            0xFE040114
  97 #define SH7780_PCIIMR           0xFE040118
  98 #define SH7780_PCIAIR           0xFE04011C
  99 #define SH7780_PCICIR           0xFE040120
 100 #define SH7780_PCIAINT          0xFE040130
 101 #define SH7780_PCIAINTM         0xFE040134
 102 #define SH7780_PCIBMIR          0xFE040138
 103 #define SH7780_PCIPAR           0xFE0401C0
 104 #define SH7780_PCIPINT          0xFE0401CC
 105 #define SH7780_PCIPINTM         0xFE0401D0
 106 #define SH7780_PCIMBR0          0xFE0401E0
 107 #define SH7780_PCIMBMR0         0xFE0401E4
 108 #define SH7780_PCIMBR1          0xFE0401E8
 109 #define SH7780_PCIMBMR1         0xFE0401EC
 110 #define SH7780_PCIMBR2          0xFE0401F0
 111 #define SH7780_PCIMBMR2         0xFE0401F4
 112 #define SH7780_PCIIOBR          0xFE0401F8
 113 #define SH7780_PCIIOBMR         0xFE0401FC
 114 #define SH7780_PCICSCR0         0xFE040210
 115 #define SH7780_PCICSCR1         0xFE040214
 116 #define SH7780_PCICSAR0         0xFE040218
 117 #define SH7780_PCICSAR1         0xFE04021C
 118 #define SH7780_PCIPDR           0xFE040220
 119
 120 #endif  /* _ASM_CPU_SH7780_H_ */