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git.ipfire.org Git - people/ms/u-boot.git/blob - arch/sparc/cpu/leon2/cpu_init.c
1 /* Initializes CPU and basic hardware such as memory
2 * controllers, IRQ controller and system timer 0.
4 * (C) Copyright 2007, 2015
5 * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com
7 * SPDX-License-Identifier: GPL-2.0+
17 DECLARE_GLOBAL_DATA_PTR
;
20 * Breath some life into the CPU...
22 * Set up the memory map,
23 * initialize a bunch of registers.
25 * Run from FLASH/PROM:
26 * - until memory controller is set up, only registers available
27 * - no global variables available for writing
28 * - constants available
33 LEON2_regs
*leon2
= (LEON2_regs
*) LEON2_PREGS
;
35 /* initialize the IRQMP */
36 leon2
->Interrupt_Force
= 0;
37 leon2
->Interrupt_Pending
= 0;
38 leon2
->Interrupt_Clear
= 0xfffe; /* clear all old pending interrupts */
39 leon2
->Interrupt_Mask
= 0xfffe0000; /* mask all IRQs */
44 #ifdef LEON2_IO_PORT_DIR
45 leon2
->PIO_Direction
= LEON2_IO_PORT_DIR
;
47 #ifdef LEON2_IO_PORT_DATA
48 leon2
->PIO_Data
= LEON2_IO_PORT_DATA
;
50 #ifdef LEON2_IO_PORT_INT
51 leon2
->PIO_Interrupt
= LEON2_IO_PORT_INT
;
53 leon2
->PIO_Interrupt
= 0;
57 leon2
->Timer_Control_1
= leon2
->Timer_Control_2
= 0;
60 int arch_cpu_init(void)
62 gd
->cpu_clk
= CONFIG_SYS_CLK_FREQ
;
63 gd
->bus_clk
= CONFIG_SYS_CLK_FREQ
;
64 gd
->ram_size
= CONFIG_SYS_SDRAM_SIZE
;
70 * initialize higher level parts of CPU
77 /* initiate and setup timer0 to configured HZ. Base clock is 1MHz.
81 LEON2_regs
*leon2
= (LEON2_regs
*)LEON2_PREGS
;
83 /* initialize prescaler common to all timers to 1MHz */
84 leon2
->Scaler_Counter
= leon2
->Scaler_Reload
=
85 (((CONFIG_SYS_CLK_FREQ
/ 1000) + 500) / 1000) - 1;
87 /* SYS_HZ ticks per second */
88 leon2
->Timer_Counter_1
= 0;
89 leon2
->Timer_Reload_1
= (CONFIG_SYS_TIMER_RATE
/ CONFIG_SYS_HZ
) - 1;
90 leon2
->Timer_Control_1
= LEON2_TIMER_CTRL_EN
| LEON2_TIMER_CTRL_RS
|
93 CONFIG_SYS_TIMER_COUNTER
= (void *)&leon2
->Timer_Counter_1
;