arch/x86/Kconfig

   1 menu "x86 architecture"
   2         depends on X86
   3
   4 config SYS_ARCH
   5         default "x86"
   6
   7 choice
   8         prompt "Run U-Boot in 32/64-bit mode"
   9         default X86_RUN_32BIT
  10         help
  11           U-Boot can be built as a 32-bit binary which runs in 32-bit mode
  12           even on 64-bit machines. In this case SPL is not used, and U-Boot
  13           runs directly from the reset vector (via 16-bit start-up).
  14
  15           Alternatively it can be run as a 64-bit binary, thus requiring a
  16           64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
  17           start-up) then jumps to U-Boot in 64-bit mode.
  18
  19           For now, 32-bit mode is recommended, as 64-bit is still
  20           experimental and is missing a lot of features.
  21
  22 config X86_RUN_32BIT
  23         bool "32-bit"
  24         help
  25           Build U-Boot as a 32-bit binary with no SPL. This is the currently
  26           supported normal setup. U-Boot will stay in 32-bit mode even on
  27           64-bit machines. When booting a 64-bit kernel, U-Boot will switch
  28           to 64-bit just before starting the kernel. Only the bottom 4GB of
  29           memory can be accessed through normal means, although
  30           arch_phys_memset() can be used for basic access to other memory.
  31
  32 config X86_RUN_64BIT
  33         bool "64-bit"
  34         select X86_64
  35         select SUPPORT_SPL
  36         select SPL
  37         select SPL_SEPARATE_BSS
  38         help
  39           Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
  40           experimental and many features are missing. U-Boot SPL starts up,
  41           runs through the 16-bit and 32-bit init, then switches to 64-bit
  42           mode and jumps to U-Boot proper.
  43
  44 endchoice
  45
  46 config X86_64
  47         bool
  48
  49 config SPL_X86_64
  50         bool
  51         depends on SPL
  52
  53 choice
  54         prompt "Mainboard vendor"
  55         default VENDOR_EMULATION
  56
  57 config VENDOR_ADVANTECH
  58         bool "advantech"
  59
  60 config VENDOR_CONGATEC
  61         bool "congatec"
  62
  63 config VENDOR_COREBOOT
  64         bool "coreboot"
  65
  66 config VENDOR_DFI
  67         bool "dfi"
  68
  69 config VENDOR_EFI
  70         bool "efi"
  71
  72 config VENDOR_EMULATION
  73         bool "emulation"
  74
  75 config VENDOR_GOOGLE
  76         bool "Google"
  77
  78 config VENDOR_INTEL
  79         bool "Intel"
  80
  81 endchoice
  82
  83 # subarchitectures-specific options below
  84 config INTEL_MID
  85         bool "Intel MID platform support"
  86         select REGMAP
  87         select SYSCON
  88         help
  89           Select to build a U-Boot capable of supporting Intel MID
  90           (Mobile Internet Device) platform systems which do not have
  91           the PCI legacy interfaces.
  92
  93           If you are building for a PC class system say N here.
  94
  95           Intel MID platforms are based on an Intel processor and
  96           chipset which consume less power than most of the x86
  97           derivatives.
  98
  99 # board-specific options below
 100 source "board/advantech/Kconfig"
 101 source "board/congatec/Kconfig"
 102 source "board/coreboot/Kconfig"
 103 source "board/dfi/Kconfig"
 104 source "board/efi/Kconfig"
 105 source "board/emulation/Kconfig"
 106 source "board/google/Kconfig"
 107 source "board/intel/Kconfig"
 108
 109 # platform-specific options below
 110 source "arch/x86/cpu/baytrail/Kconfig"
 111 source "arch/x86/cpu/braswell/Kconfig"
 112 source "arch/x86/cpu/broadwell/Kconfig"
 113 source "arch/x86/cpu/coreboot/Kconfig"
 114 source "arch/x86/cpu/ivybridge/Kconfig"
 115 source "arch/x86/cpu/qemu/Kconfig"
 116 source "arch/x86/cpu/quark/Kconfig"
 117 source "arch/x86/cpu/queensbay/Kconfig"
 118 source "arch/x86/cpu/tangier/Kconfig"
 119
 120 # architecture-specific options below
 121
 122 config AHCI
 123         default y
 124
 125 config SYS_MALLOC_F_LEN
 126         default 0x800
 127
 128 config RAMBASE
 129         hex
 130         default 0x100000
 131
 132 config XIP_ROM_SIZE
 133         hex
 134         depends on X86_RESET_VECTOR
 135         default ROM_SIZE
 136
 137 config CPU_ADDR_BITS
 138         int
 139         default 36
 140
 141 config HPET_ADDRESS
 142         hex
 143         default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
 144
 145 config SMM_TSEG
 146         bool
 147         default n
 148
 149 config SMM_TSEG_SIZE
 150         hex
 151
 152 config X86_RESET_VECTOR
 153         bool
 154         default n
 155         select BINMAN
 156
 157 # The following options control where the 16-bit and 32-bit init lies
 158 # If SPL is enabled then it normally holds this init code, and U-Boot proper
 159 # is normally a 64-bit build.
 160 #
 161 # The 16-bit init refers to the reset vector and the small amount of code to
 162 # get the processor into 32-bit mode. It may be in SPL or in U-Boot proper,
 163 # or missing altogether if U-Boot is started from EFI or coreboot.
 164 #
 165 # The 32-bit init refers to processor init, running binary blobs including
 166 # FSP, setting up interrupts and anything else that needs to be done in
 167 # 32-bit code. It is normally in the same place as 16-bit init if that is
 168 # enabled (i.e. they are both in SPL, or both in U-Boot proper).
 169 config X86_16BIT_INIT
 170         bool
 171         depends on X86_RESET_VECTOR
 172         default y if X86_RESET_VECTOR && !SPL
 173         help
 174           This is enabled when 16-bit init is in U-Boot proper
 175
 176 config SPL_X86_16BIT_INIT
 177         bool
 178         depends on X86_RESET_VECTOR
 179         default y if X86_RESET_VECTOR && SPL
 180         help
 181           This is enabled when 16-bit init is in SPL
 182
 183 config X86_32BIT_INIT
 184         bool
 185         depends on X86_RESET_VECTOR
 186         default y if X86_RESET_VECTOR && !SPL
 187         help
 188           This is enabled when 32-bit init is in U-Boot proper
 189
 190 config SPL_X86_32BIT_INIT
 191         bool
 192         depends on X86_RESET_VECTOR
 193         default y if X86_RESET_VECTOR && SPL
 194         help
 195           This is enabled when 32-bit init is in SPL
 196
 197 config RESET_SEG_START
 198         hex
 199         depends on X86_RESET_VECTOR
 200         default 0xffff0000
 201
 202 config RESET_SEG_SIZE
 203         hex
 204         depends on X86_RESET_VECTOR
 205         default 0x10000
 206
 207 config RESET_VEC_LOC
 208         hex
 209         depends on X86_RESET_VECTOR
 210         default 0xfffffff0
 211
 212 config SYS_X86_START16
 213         hex
 214         depends on X86_RESET_VECTOR
 215         default 0xfffff800
 216
 217 config X86_LOAD_FROM_32_BIT
 218         bool "Boot from a 32-bit program"
 219         help
 220           Define this to boot U-Boot from a 32-bit program which sets
 221           the GDT differently. This can be used to boot directly from
 222           any stage of coreboot, for example, bypassing the normal
 223           payload-loading feature.
 224
 225 config BOARD_ROMSIZE_KB_512
 226         bool
 227 config BOARD_ROMSIZE_KB_1024
 228         bool
 229 config BOARD_ROMSIZE_KB_2048
 230         bool
 231 config BOARD_ROMSIZE_KB_4096
 232         bool
 233 config BOARD_ROMSIZE_KB_8192
 234         bool
 235 config BOARD_ROMSIZE_KB_16384
 236         bool
 237
 238 choice
 239         prompt "ROM chip size"
 240         depends on X86_RESET_VECTOR
 241         default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
 242         default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
 243         default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
 244         default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
 245         default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
 246         default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
 247         help
 248           Select the size of the ROM chip you intend to flash U-Boot on.
 249
 250           The build system will take care of creating a u-boot.rom file
 251           of the matching size.
 252
 253 config UBOOT_ROMSIZE_KB_512
 254         bool "512 KB"
 255         help
 256           Choose this option if you have a 512 KB ROM chip.
 257
 258 config UBOOT_ROMSIZE_KB_1024
 259         bool "1024 KB (1 MB)"
 260         help
 261           Choose this option if you have a 1024 KB (1 MB) ROM chip.
 262
 263 config UBOOT_ROMSIZE_KB_2048
 264         bool "2048 KB (2 MB)"
 265         help
 266           Choose this option if you have a 2048 KB (2 MB) ROM chip.
 267
 268 config UBOOT_ROMSIZE_KB_4096
 269         bool "4096 KB (4 MB)"
 270         help
 271           Choose this option if you have a 4096 KB (4 MB) ROM chip.
 272
 273 config UBOOT_ROMSIZE_KB_8192
 274         bool "8192 KB (8 MB)"
 275         help
 276           Choose this option if you have a 8192 KB (8 MB) ROM chip.
 277
 278 config UBOOT_ROMSIZE_KB_16384
 279         bool "16384 KB (16 MB)"
 280         help
 281           Choose this option if you have a 16384 KB (16 MB) ROM chip.
 282
 283 endchoice
 284
 285 # Map the config names to an integer (KB).
 286 config UBOOT_ROMSIZE_KB
 287         int
 288         default 512 if UBOOT_ROMSIZE_KB_512
 289         default 1024 if UBOOT_ROMSIZE_KB_1024
 290         default 2048 if UBOOT_ROMSIZE_KB_2048
 291         default 4096 if UBOOT_ROMSIZE_KB_4096
 292         default 8192 if UBOOT_ROMSIZE_KB_8192
 293         default 16384 if UBOOT_ROMSIZE_KB_16384
 294
 295 # Map the config names to a hex value (bytes).
 296 config ROM_SIZE
 297         hex
 298         default 0x80000 if UBOOT_ROMSIZE_KB_512
 299         default 0x100000 if UBOOT_ROMSIZE_KB_1024
 300         default 0x200000 if UBOOT_ROMSIZE_KB_2048
 301         default 0x400000 if UBOOT_ROMSIZE_KB_4096
 302         default 0x800000 if UBOOT_ROMSIZE_KB_8192
 303         default 0xc00000 if UBOOT_ROMSIZE_KB_12288
 304         default 0x1000000 if UBOOT_ROMSIZE_KB_16384
 305
 306 config HAVE_INTEL_ME
 307         bool "Platform requires Intel Management Engine"
 308         help
 309           Newer higher-end devices have an Intel Management Engine (ME)
 310           which is a very large binary blob (typically 1.5MB) which is
 311           required for the platform to work. This enforces a particular
 312           SPI flash format. You will need to supply the me.bin file in
 313           your board directory.
 314
 315 config X86_RAMTEST
 316         bool "Perform a simple RAM test after SDRAM initialisation"
 317         help
 318           If there is something wrong with SDRAM then the platform will
 319           often crash within U-Boot or the kernel. This option enables a
 320           very simple RAM test that quickly checks whether the SDRAM seems
 321           to work correctly. It is not exhaustive but can save time by
 322           detecting obvious failures.
 323
 324 config FLASH_DESCRIPTOR_FILE
 325         string "Flash descriptor binary filename"
 326         depends on HAVE_INTEL_ME
 327         default "descriptor.bin"
 328         help
 329           The filename of the file to use as flash descriptor in the
 330           board directory.
 331
 332 config INTEL_ME_FILE
 333         string "Intel Management Engine binary filename"
 334         depends on HAVE_INTEL_ME
 335         default "me.bin"
 336         help
 337           The filename of the file to use as Intel Management Engine in the
 338           board directory.
 339
 340 config HAVE_FSP
 341         bool "Add an Firmware Support Package binary"
 342         depends on !EFI
 343         help
 344           Select this option to add an Firmware Support Package binary to
 345           the resulting U-Boot image. It is a binary blob which U-Boot uses
 346           to set up SDRAM and other chipset specific initialization.
 347
 348           Note: Without this binary U-Boot will not be able to set up its
 349           SDRAM so will not boot.
 350
 351 config FSP_FILE
 352         string "Firmware Support Package binary filename"
 353         depends on HAVE_FSP
 354         default "fsp.bin"
 355         help
 356           The filename of the file to use as Firmware Support Package binary
 357           in the board directory.
 358
 359 config FSP_ADDR
 360         hex "Firmware Support Package binary location"
 361         depends on HAVE_FSP
 362         default 0xfffc0000
 363         help
 364           FSP is not Position Independent Code (PIC) and the whole FSP has to
 365           be rebased if it is placed at a location which is different from the
 366           perferred base address specified during the FSP build. Use Intel's
 367           Binary Configuration Tool (BCT) to do the rebase.
 368
 369           The default base address of 0xfffc0000 indicates that the binary must
 370           be located at offset 0xc0000 from the beginning of a 1MB flash device.
 371
 372 config FSP_TEMP_RAM_ADDR
 373         hex
 374         depends on HAVE_FSP
 375         default 0x2000000
 376         help
 377           Stack top address which is used in fsp_init() after DRAM is ready and
 378           CAR is disabled.
 379
 380 config FSP_SYS_MALLOC_F_LEN
 381         hex
 382         depends on HAVE_FSP
 383         default 0x100000
 384         help
 385           Additional size of malloc() pool before relocation.
 386
 387 config FSP_USE_UPD
 388         bool
 389         depends on HAVE_FSP
 390         default y
 391         help
 392           Most FSPs use UPD data region for some FSP customization. But there
 393           are still some FSPs that might not even have UPD. For such FSPs,
 394           override this to n in their platform Kconfig files.
 395
 396 config FSP_BROKEN_HOB
 397         bool
 398         depends on HAVE_FSP
 399         help
 400           Indicate some buggy FSPs that does not report memory used by FSP
 401           itself as reserved in the resource descriptor HOB. Select this to
 402           tell U-Boot to do some additional work to ensure U-Boot relocation
 403           do not overwrite the important boot service data which is used by
 404           FSP, otherwise the subsequent call to fsp_notify() will fail.
 405
 406 config ENABLE_MRC_CACHE
 407         bool "Enable MRC cache"
 408         depends on !EFI && !SYS_COREBOOT
 409         help
 410           Enable this feature to cause MRC data to be cached in NV storage
 411           to be used for speeding up boot time on future reboots and/or
 412           power cycles.
 413
 414           For platforms that use Intel FSP for the memory initialization,
 415           please check FSP output HOB via U-Boot command 'fsp hob' to see
 416           if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h).
 417           If such GUID does not exist, MRC cache is not avaiable on such
 418           platform (eg: Intel Queensbay), which means selecting this option
 419           here does not make any difference.
 420
 421 config HAVE_MRC
 422         bool "Add a System Agent binary"
 423         depends on !HAVE_FSP
 424         help
 425           Select this option to add a System Agent binary to
 426           the resulting U-Boot image. MRC stands for Memory Reference Code.
 427           It is a binary blob which U-Boot uses to set up SDRAM.
 428
 429           Note: Without this binary U-Boot will not be able to set up its
 430           SDRAM so will not boot.
 431
 432 config CACHE_MRC_BIN
 433         bool
 434         depends on HAVE_MRC
 435         default n
 436         help
 437           Enable caching for the memory reference code binary. This uses an
 438           MTRR (memory type range register) to turn on caching for the section
 439           of SPI flash that contains the memory reference code. This makes
 440           SDRAM init run faster.
 441
 442 config CACHE_MRC_SIZE_KB
 443         int
 444         depends on HAVE_MRC
 445         default 512
 446         help
 447           Sets the size of the cached area for the memory reference code.
 448           This ends at the end of SPI flash (address 0xffffffff) and is
 449           measured in KB. Typically this is set to 512, providing for 0.5MB
 450           of cached space.
 451
 452 config DCACHE_RAM_BASE
 453         hex
 454         depends on HAVE_MRC
 455         help
 456           Sets the base of the data cache area in memory space. This is the
 457           start address of the cache-as-RAM (CAR) area and the address varies
 458           depending on the CPU. Once CAR is set up, read/write memory becomes
 459           available at this address and can be used temporarily until SDRAM
 460           is working.
 461
 462 config DCACHE_RAM_SIZE
 463         hex
 464         depends on HAVE_MRC
 465         default 0x40000
 466         help
 467           Sets the total size of the data cache area in memory space. This
 468           sets the size of the cache-as-RAM (CAR) area. Note that much of the
 469           CAR space is required by the MRC. The CAR space available to U-Boot
 470           is normally at the start and typically extends to 1/4 or 1/2 of the
 471           available size.
 472
 473 config DCACHE_RAM_MRC_VAR_SIZE
 474         hex
 475         depends on HAVE_MRC
 476         help
 477           This is the amount of CAR (Cache as RAM) reserved for use by the
 478           memory reference code. This depends on the implementation of the
 479           memory reference code and must be set correctly or the board will
 480           not boot.
 481
 482 config HAVE_REFCODE
 483         bool "Add a Reference Code binary"
 484         help
 485           Select this option to add a Reference Code binary to the resulting
 486           U-Boot image. This is an Intel binary blob that handles system
 487           initialisation, in this case the PCH and System Agent.
 488
 489           Note: Without this binary (on platforms that need it such as
 490           broadwell) U-Boot will be missing some critical setup steps.
 491           Various peripherals may fail to work.
 492
 493 config SMP
 494         bool "Enable Symmetric Multiprocessing"
 495         default n
 496         help
 497           Enable use of more than one CPU in U-Boot and the Operating System
 498           when loaded. Each CPU will be started up and information can be
 499           obtained using the 'cpu' command. If this option is disabled, then
 500           only one CPU will be enabled regardless of the number of CPUs
 501           available.
 502
 503 config MAX_CPUS
 504         int "Maximum number of CPUs permitted"
 505         depends on SMP
 506         default 4
 507         help
 508           When using multi-CPU chips it is possible for U-Boot to start up
 509           more than one CPU. The stack memory used by all of these CPUs is
 510           pre-allocated so at present U-Boot wants to know the maximum
 511           number of CPUs that may be present. Set this to at least as high
 512           as the number of CPUs in your system (it uses about 4KB of RAM for
 513           each CPU).
 514
 515 config AP_STACK_SIZE
 516         hex
 517         depends on SMP
 518         default 0x1000
 519         help
 520           Each additional CPU started by U-Boot requires its own stack. This
 521           option sets the stack size used by each CPU and directly affects
 522           the memory used by this initialisation process. Typically 4KB is
 523           enough space.
 524
 525 config CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
 526         bool
 527         help
 528           This option indicates that the turbo mode setting is not package
 529           scoped. i.e. turbo_enable() needs to be called on not just the
 530           bootstrap processor (BSP).
 531
 532 config HAVE_VGA_BIOS
 533         bool "Add a VGA BIOS image"
 534         help
 535           Select this option if you have a VGA BIOS image that you would
 536           like to add to your ROM.
 537
 538 config VGA_BIOS_FILE
 539         string "VGA BIOS image filename"
 540         depends on HAVE_VGA_BIOS
 541         default "vga.bin"
 542         help
 543           The filename of the VGA BIOS image in the board directory.
 544
 545 config VGA_BIOS_ADDR
 546         hex "VGA BIOS image location"
 547         depends on HAVE_VGA_BIOS
 548         default 0xfff90000
 549         help
 550           The location of VGA BIOS image in the SPI flash. For example, base
 551           address of 0xfff90000 indicates that the image will be put at offset
 552           0x90000 from the beginning of a 1MB flash device.
 553
 554 config HAVE_VBT
 555         bool "Add a Video BIOS Table (VBT) image"
 556         depends on HAVE_FSP
 557         help
 558           Select this option if you have a Video BIOS Table (VBT) image that
 559           you would like to add to your ROM. This is normally required if you
 560           are using an Intel FSP firmware that is complaint with spec 1.1 or
 561           later to initialize the integrated graphics device (IGD).
 562
 563           Video BIOS Table, or VBT, provides platform and board specific
 564           configuration information to the driver that is not discoverable
 565           or available through other means. By other means the most used
 566           method here is to read EDID table from the attached monitor, over
 567           Display Data Channel (DDC) using two pin I2C serial interface. VBT
 568           configuration is related to display hardware and is available via
 569           the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM).
 570
 571 config VBT_FILE
 572         string "Video BIOS Table (VBT) image filename"
 573         depends on HAVE_VBT
 574         default "vbt.bin"
 575         help
 576           The filename of the file to use as Video BIOS Table (VBT) image
 577           in the board directory.
 578
 579 config VBT_ADDR
 580         hex "Video BIOS Table (VBT) image location"
 581         depends on HAVE_VBT
 582         default 0xfff90000
 583         help
 584           The location of Video BIOS Table (VBT) image in the SPI flash. For
 585           example, base address of 0xfff90000 indicates that the image will
 586           be put at offset 0x90000 from the beginning of a 1MB flash device.
 587
 588 config VIDEO_FSP
 589         bool "Enable FSP framebuffer driver support"
 590         depends on HAVE_VBT && DM_VIDEO
 591         help
 592           Turn on this option to enable a framebuffer driver when U-Boot is
 593           using Video BIOS Table (VBT) image for FSP firmware to initialize
 594           the integrated graphics device.
 595
 596 config ROM_TABLE_ADDR
 597         hex
 598         default 0xf0000
 599         help
 600           All x86 tables happen to like the address range from 0x0f0000
 601           to 0x100000. We use 0xf0000 as the starting address to store
 602           those tables, including PIRQ routing table, Multi-Processor
 603           table and ACPI table.
 604
 605 config ROM_TABLE_SIZE
 606         hex
 607         default 0x10000
 608
 609 menu "System tables"
 610         depends on !EFI && !SYS_COREBOOT
 611
 612 config GENERATE_PIRQ_TABLE
 613         bool "Generate a PIRQ table"
 614         default n
 615         help
 616           Generate a PIRQ routing table for this board. The PIRQ routing table
 617           is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
 618           at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
 619           It specifies the interrupt router information as well how all the PCI
 620           devices' interrupt pins are wired to PIRQs.
 621
 622 config GENERATE_SFI_TABLE
 623         bool "Generate a SFI (Simple Firmware Interface) table"
 624         help
 625           The Simple Firmware Interface (SFI) provides a lightweight method
 626           for platform firmware to pass information to the operating system
 627           via static tables in memory.  Kernel SFI support is required to
 628           boot on SFI-only platforms.  If you have ACPI tables then these are
 629           used instead.
 630
 631           U-Boot writes this table in write_sfi_table() just before booting
 632           the OS.
 633
 634           For more information, see http://simplefirmware.org
 635
 636 config GENERATE_MP_TABLE
 637         bool "Generate an MP (Multi-Processor) table"
 638         default n
 639         help
 640           Generate an MP (Multi-Processor) table for this board. The MP table
 641           provides a way for the operating system to support for symmetric
 642           multiprocessing as well as symmetric I/O interrupt handling with
 643           the local APIC and I/O APIC.
 644
 645 config GENERATE_ACPI_TABLE
 646         bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
 647         default n
 648         select QFW if QEMU
 649         help
 650           The Advanced Configuration and Power Interface (ACPI) specification
 651           provides an open standard for device configuration and management
 652           by the operating system. It defines platform-independent interfaces
 653           for configuration and power management monitoring.
 654
 655 endmenu
 656
 657 config HAVE_ACPI_RESUME
 658         bool "Enable ACPI S3 resume"
 659         select ENABLE_MRC_CACHE
 660         help
 661           Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping
 662           state where all system context is lost except system memory. U-Boot
 663           is responsible for restoring the machine state as it was before sleep.
 664           It needs restore the memory controller, without overwriting memory
 665           which is not marked as reserved. For the peripherals which lose their
 666           registers, U-Boot needs to write the original value. When everything
 667           is done, U-Boot needs to find out the wakeup vector provided by OSes
 668           and jump there.
 669
 670 config S3_VGA_ROM_RUN
 671         bool "Re-run VGA option ROMs on S3 resume"
 672         depends on HAVE_ACPI_RESUME
 673         help
 674           Execute VGA option ROMs in U-Boot when resuming from S3. Normally
 675           this is needed when graphics console is being used in the kernel.
 676
 677           Turning it off can reduce some resume time, but be aware that your
 678           graphics console won't work without VGA options ROMs. Set it to N
 679           if your kernel is only on a serial console.
 680
 681 config STACK_SIZE
 682         hex
 683         depends on HAVE_ACPI_RESUME
 684         default 0x1000
 685         help
 686           Estimated U-Boot's runtime stack size that needs to be reserved
 687           during an ACPI S3 resume.
 688
 689 config MAX_PIRQ_LINKS
 690         int
 691         default 8
 692         help
 693           This variable specifies the number of PIRQ interrupt links which are
 694           routable. On most older chipsets, this is 4, PIRQA through PIRQD.
 695           Some newer chipsets offer more than four links, commonly up to PIRQH.
 696
 697 config IRQ_SLOT_COUNT
 698         int
 699         default 128
 700         help
 701           U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
 702           which in turns forms a table of exact 4KiB. The default value 128
 703           should be enough for most boards. If this does not fit your board,
 704           change it according to your needs.
 705
 706 config PCIE_ECAM_BASE
 707         hex
 708         default 0xe0000000
 709         help
 710           This is the memory-mapped address of PCI configuration space, which
 711           is only available through the Enhanced Configuration Access
 712           Mechanism (ECAM) with PCI Express. It can be set up almost
 713           anywhere. Before it is set up, it is possible to access PCI
 714           configuration space through I/O access, but memory access is more
 715           convenient. Using this, PCI can be scanned and configured. This
 716           should be set to a region that does not conflict with memory
 717           assigned to PCI devices - i.e. the memory and prefetch regions, as
 718           passed to pci_set_region().
 719
 720 config PCIE_ECAM_SIZE
 721         hex
 722         default 0x10000000
 723         help
 724           This is the size of memory-mapped address of PCI configuration space,
 725           which is only available through the Enhanced Configuration Access
 726           Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
 727           so a default 0x10000000 size covers all of the 256 buses which is the
 728           maximum number of PCI buses as defined by the PCI specification.
 729
 730 config I8259_PIC
 731         bool
 732         default y
 733         help
 734           Intel 8259 ISA compatible chipset incorporates two 8259 (master and
 735           slave) interrupt controllers. Include this to have U-Boot set up
 736           the interrupt correctly.
 737
 738 config I8254_TIMER
 739         bool
 740         default y
 741         help
 742           Intel 8254 timer contains three counters which have fixed uses.
 743           Include this to have U-Boot set up the timer correctly.
 744
 745 config SEABIOS
 746         bool "Support booting SeaBIOS"
 747         help
 748           SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
 749           It can run in an emulator or natively on X86 hardware with the use
 750           of coreboot/U-Boot. By turning on this option, U-Boot prepares
 751           all the configuration tables that are necessary to boot SeaBIOS.
 752
 753           Check http://www.seabios.org/SeaBIOS for details.
 754
 755 config HIGH_TABLE_SIZE
 756         hex "Size of configuration tables which reside in high memory"
 757         default 0x10000
 758         depends on SEABIOS
 759         help
 760           SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
 761           configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
 762           puts a copy of configuration tables in high memory region which
 763           is reserved on the stack before relocation. The region size is
 764           determined by this option.
 765
 766           Increse it if the default size does not fit the board's needs.
 767           This is most likely due to a large ACPI DSDT table is used.
 768
 769 source "arch/x86/lib/efi/Kconfig"
 770
 771 endmenu