arch/x86/Kconfig

   1 menu "x86 architecture"
   2         depends on X86
   3
   4 config SYS_ARCH
   5         default "x86"
   6
   7 choice
   8         prompt "Mainboard vendor"
   9         default VENDOR_EMULATION
  10
  11 config VENDOR_COREBOOT
  12         bool "coreboot"
  13
  14 config VENDOR_EMULATION
  15         bool "emulation"
  16
  17 config VENDOR_GOOGLE
  18         bool "Google"
  19
  20 config VENDOR_INTEL
  21         bool "Intel"
  22
  23 endchoice
  24
  25 # board-specific options below
  26 source "board/coreboot/Kconfig"
  27 source "board/emulation/Kconfig"
  28 source "board/google/Kconfig"
  29 source "board/intel/Kconfig"
  30
  31 # platform-specific options below
  32 source "arch/x86/cpu/baytrail/Kconfig"
  33 source "arch/x86/cpu/coreboot/Kconfig"
  34 source "arch/x86/cpu/ivybridge/Kconfig"
  35 source "arch/x86/cpu/qemu/Kconfig"
  36 source "arch/x86/cpu/quark/Kconfig"
  37 source "arch/x86/cpu/queensbay/Kconfig"
  38
  39 # architecture-specific options below
  40
  41 config SYS_MALLOC_F_LEN
  42         default 0x800
  43
  44 config RAMBASE
  45         hex
  46         default 0x100000
  47
  48 config XIP_ROM_SIZE
  49         hex
  50         depends on X86_RESET_VECTOR
  51         default ROM_SIZE
  52
  53 config CPU_ADDR_BITS
  54         int
  55         default 36
  56
  57 config HPET_ADDRESS
  58         hex
  59         default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
  60
  61 config SMM_TSEG
  62         bool
  63         default n
  64
  65 config SMM_TSEG_SIZE
  66         hex
  67
  68 config X86_RESET_VECTOR
  69         bool
  70         default n
  71
  72 config RESET_SEG_START
  73         hex
  74         depends on X86_RESET_VECTOR
  75         default 0xffff0000
  76
  77 config RESET_SEG_SIZE
  78         hex
  79         depends on X86_RESET_VECTOR
  80         default 0x10000
  81
  82 config RESET_VEC_LOC
  83         hex
  84         depends on X86_RESET_VECTOR
  85         default 0xfffffff0
  86
  87 config SYS_X86_START16
  88         hex
  89         depends on X86_RESET_VECTOR
  90         default 0xfffff800
  91
  92 config BOARD_ROMSIZE_KB_512
  93         bool
  94 config BOARD_ROMSIZE_KB_1024
  95         bool
  96 config BOARD_ROMSIZE_KB_2048
  97         bool
  98 config BOARD_ROMSIZE_KB_4096
  99         bool
 100 config BOARD_ROMSIZE_KB_8192
 101         bool
 102 config BOARD_ROMSIZE_KB_16384
 103         bool
 104
 105 choice
 106         prompt "ROM chip size"
 107         depends on X86_RESET_VECTOR
 108         default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
 109         default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
 110         default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
 111         default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
 112         default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
 113         default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
 114         help
 115           Select the size of the ROM chip you intend to flash U-Boot on.
 116
 117           The build system will take care of creating a u-boot.rom file
 118           of the matching size.
 119
 120 config UBOOT_ROMSIZE_KB_512
 121         bool "512 KB"
 122         help
 123           Choose this option if you have a 512 KB ROM chip.
 124
 125 config UBOOT_ROMSIZE_KB_1024
 126         bool "1024 KB (1 MB)"
 127         help
 128           Choose this option if you have a 1024 KB (1 MB) ROM chip.
 129
 130 config UBOOT_ROMSIZE_KB_2048
 131         bool "2048 KB (2 MB)"
 132         help
 133           Choose this option if you have a 2048 KB (2 MB) ROM chip.
 134
 135 config UBOOT_ROMSIZE_KB_4096
 136         bool "4096 KB (4 MB)"
 137         help
 138           Choose this option if you have a 4096 KB (4 MB) ROM chip.
 139
 140 config UBOOT_ROMSIZE_KB_8192
 141         bool "8192 KB (8 MB)"
 142         help
 143           Choose this option if you have a 8192 KB (8 MB) ROM chip.
 144
 145 config UBOOT_ROMSIZE_KB_16384
 146         bool "16384 KB (16 MB)"
 147         help
 148           Choose this option if you have a 16384 KB (16 MB) ROM chip.
 149
 150 endchoice
 151
 152 # Map the config names to an integer (KB).
 153 config UBOOT_ROMSIZE_KB
 154         int
 155         default 512 if UBOOT_ROMSIZE_KB_512
 156         default 1024 if UBOOT_ROMSIZE_KB_1024
 157         default 2048 if UBOOT_ROMSIZE_KB_2048
 158         default 4096 if UBOOT_ROMSIZE_KB_4096
 159         default 8192 if UBOOT_ROMSIZE_KB_8192
 160         default 16384 if UBOOT_ROMSIZE_KB_16384
 161
 162 # Map the config names to a hex value (bytes).
 163 config ROM_SIZE
 164         hex
 165         default 0x80000 if UBOOT_ROMSIZE_KB_512
 166         default 0x100000 if UBOOT_ROMSIZE_KB_1024
 167         default 0x200000 if UBOOT_ROMSIZE_KB_2048
 168         default 0x400000 if UBOOT_ROMSIZE_KB_4096
 169         default 0x800000 if UBOOT_ROMSIZE_KB_8192
 170         default 0xc00000 if UBOOT_ROMSIZE_KB_12288
 171         default 0x1000000 if UBOOT_ROMSIZE_KB_16384
 172
 173 config HAVE_INTEL_ME
 174         bool "Platform requires Intel Management Engine"
 175         help
 176           Newer higher-end devices have an Intel Management Engine (ME)
 177           which is a very large binary blob (typically 1.5MB) which is
 178           required for the platform to work. This enforces a particular
 179           SPI flash format. You will need to supply the me.bin file in
 180           your board directory.
 181
 182 config X86_RAMTEST
 183         bool "Perform a simple RAM test after SDRAM initialisation"
 184         help
 185           If there is something wrong with SDRAM then the platform will
 186           often crash within U-Boot or the kernel. This option enables a
 187           very simple RAM test that quickly checks whether the SDRAM seems
 188           to work correctly. It is not exhaustive but can save time by
 189           detecting obvious failures.
 190
 191 config MARK_GRAPHICS_MEM_WRCOMB
 192         bool "Mark graphics memory as write-combining"
 193         default n
 194         help
 195           The graphics performance may increase if the graphics
 196           memory is set as write-combining cache type. This option
 197           enables marking the graphics memory as write-combining.
 198
 199 config HAVE_FSP
 200         bool "Add an Firmware Support Package binary"
 201         help
 202           Select this option to add an Firmware Support Package binary to
 203           the resulting U-Boot image. It is a binary blob which U-Boot uses
 204           to set up SDRAM and other chipset specific initialization.
 205
 206           Note: Without this binary U-Boot will not be able to set up its
 207           SDRAM so will not boot.
 208
 209 config FSP_FILE
 210         string "Firmware Support Package binary filename"
 211         depends on HAVE_FSP
 212         default "fsp.bin"
 213         help
 214           The filename of the file to use as Firmware Support Package binary
 215           in the board directory.
 216
 217 config FSP_ADDR
 218         hex "Firmware Support Package binary location"
 219         depends on HAVE_FSP
 220         default 0xfffc0000
 221         help
 222           FSP is not Position Independent Code (PIC) and the whole FSP has to
 223           be rebased if it is placed at a location which is different from the
 224           perferred base address specified during the FSP build. Use Intel's
 225           Binary Configuration Tool (BCT) to do the rebase.
 226
 227           The default base address of 0xfffc0000 indicates that the binary must
 228           be located at offset 0xc0000 from the beginning of a 1MB flash device.
 229
 230 config FSP_TEMP_RAM_ADDR
 231         hex
 232         depends on HAVE_FSP
 233         default 0x2000000
 234         help
 235           Stack top address which is used in FspInit after DRAM is ready and
 236           CAR is disabled.
 237
 238 config SMP
 239         bool "Enable Symmetric Multiprocessing"
 240         default n
 241         help
 242           Enable use of more than one CPU in U-Boot and the Operating System
 243           when loaded. Each CPU will be started up and information can be
 244           obtained using the 'cpu' command. If this option is disabled, then
 245           only one CPU will be enabled regardless of the number of CPUs
 246           available.
 247
 248 config MAX_CPUS
 249         int "Maximum number of CPUs permitted"
 250         depends on SMP
 251         default 4
 252         help
 253           When using multi-CPU chips it is possible for U-Boot to start up
 254           more than one CPU. The stack memory used by all of these CPUs is
 255           pre-allocated so at present U-Boot wants to know the maximum
 256           number of CPUs that may be present. Set this to at least as high
 257           as the number of CPUs in your system (it uses about 4KB of RAM for
 258           each CPU).
 259
 260 config AP_STACK_SIZE
 261         hex
 262         depends on SMP
 263         default 0x1000
 264         help
 265           Each additional CPU started by U-Boot requires its own stack. This
 266           option sets the stack size used by each CPU and directly affects
 267           the memory used by this initialisation process. Typically 4KB is
 268           enough space.
 269
 270 config TSC_CALIBRATION_BYPASS
 271         bool "Bypass Time-Stamp Counter (TSC) calibration"
 272         default n
 273         help
 274           By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
 275           running frequency via Model-Specific Register (MSR) and Programmable
 276           Interval Timer (PIT). If the calibration does not work on your board,
 277           select this option and provide a hardcoded TSC running frequency with
 278           CONFIG_TSC_FREQ_IN_MHZ below.
 279
 280           Normally this option should be turned on in a simulation environment
 281           like qemu.
 282
 283 config TSC_FREQ_IN_MHZ
 284         int "Time-Stamp Counter (TSC) running frequency in MHz"
 285         depends on TSC_CALIBRATION_BYPASS
 286         default 1000
 287         help
 288           The running frequency in MHz of Time-Stamp Counter (TSC).
 289
 290 config HAVE_VGA_BIOS
 291         bool "Add a VGA BIOS image"
 292         help
 293           Select this option if you have a VGA BIOS image that you would
 294           like to add to your ROM.
 295
 296 config VGA_BIOS_FILE
 297         string "VGA BIOS image filename"
 298         depends on HAVE_VGA_BIOS
 299         default "vga.bin"
 300         help
 301           The filename of the VGA BIOS image in the board directory.
 302
 303 config VGA_BIOS_ADDR
 304         hex "VGA BIOS image location"
 305         depends on HAVE_VGA_BIOS
 306         default 0xfff90000
 307         help
 308           The location of VGA BIOS image in the SPI flash. For example, base
 309           address of 0xfff90000 indicates that the image will be put at offset
 310           0x90000 from the beginning of a 1MB flash device.
 311
 312 menu "System tables"
 313
 314 config GENERATE_PIRQ_TABLE
 315         bool "Generate a PIRQ table"
 316         default n
 317         help
 318           Generate a PIRQ routing table for this board. The PIRQ routing table
 319           is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
 320           at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
 321           It specifies the interrupt router information as well how all the PCI
 322           devices' interrupt pins are wired to PIRQs.
 323
 324 config GENERATE_SFI_TABLE
 325         bool "Generate a SFI (Simple Firmware Interface) table"
 326         help
 327           The Simple Firmware Interface (SFI) provides a lightweight method
 328           for platform firmware to pass information to the operating system
 329           via static tables in memory.  Kernel SFI support is required to
 330           boot on SFI-only platforms.  If you have ACPI tables then these are
 331           used instead.
 332
 333           U-Boot writes this table in write_sfi_table() just before booting
 334           the OS.
 335
 336           For more information, see http://simplefirmware.org
 337
 338 config GENERATE_MP_TABLE
 339         bool "Generate an MP (Multi-Processor) table"
 340         default n
 341         help
 342           Generate an MP (Multi-Processor) table for this board. The MP table
 343           provides a way for the operating system to support for symmetric
 344           multiprocessing as well as symmetric I/O interrupt handling with
 345           the local APIC and I/O APIC.
 346
 347 endmenu
 348
 349 config MAX_PIRQ_LINKS
 350         int
 351         default 8
 352         help
 353           This variable specifies the number of PIRQ interrupt links which are
 354           routable. On most older chipsets, this is 4, PIRQA through PIRQD.
 355           Some newer chipsets offer more than four links, commonly up to PIRQH.
 356
 357 config IRQ_SLOT_COUNT
 358         int
 359         default 128
 360         help
 361           U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
 362           which in turns forms a table of exact 4KiB. The default value 128
 363           should be enough for most boards. If this does not fit your board,
 364           change it according to your needs.
 365
 366 config PCIE_ECAM_BASE
 367         hex
 368         default 0xe0000000
 369         help
 370           This is the memory-mapped address of PCI configuration space, which
 371           is only available through the Enhanced Configuration Access
 372           Mechanism (ECAM) with PCI Express. It can be set up almost
 373           anywhere. Before it is set up, it is possible to access PCI
 374           configuration space through I/O access, but memory access is more
 375           convenient. Using this, PCI can be scanned and configured. This
 376           should be set to a region that does not conflict with memory
 377           assigned to PCI devices - i.e. the memory and prefetch regions, as
 378           passed to pci_set_region().
 379
 380 endmenu