arch/x86/cpu/sc520/sc520_car.S

   1 /*
   2  * (C) Copyright 2010-2011
   3  * Graeme Russ, <graeme.russ@gmail.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <config.h>
  25 #include <asm/processor-flags.h>
  26 #include <asm/ic/sc520.h>
  27
  28 .section .text
  29
  30 .globl car_init
  31 car_init:
  32         /*
  33          * How to enable Cache-As-RAM for the AMD Elan SC520:
  34          *  1. Turn off the CPU Cache (may not be strictly required)
  35          *  2. Set code execution PAR (usually the BOOTCS region) to be
  36          *     non-cachable
  37          *  3. Create a Cachable PAR Region for an area of memory which is
  38          *       a) NOT where the code is being executed
  39          *       b) NOT SDRAM (Controller not initialised yet)
  40          *       c) WILL response to read requests
  41          *     The easiest way to do this is to create a second BOOTCS
  42          *     PAR mappnig with an address != the PAR in step 2
  43          *  4. Issue a wbinvd to invalidate the CPU cache
  44          *  5. Turn on the CPU Cache
  45          *  6. Read 16kB from the cached PAR region setup in step 3
  46          *  7. Turn off the CPU Cache (but DO NOT issue a wbinvd)
  47          *
  48          * The following code uses PAR2 as the cached PAR (PAR0 and PAR1
  49          * are avoided as these are the only two PARs which can be used
  50          * as PCI BUS Memory regions which the board might require)
  51          *
  52          * The configuration of PAR2 must be set in the board configuration
  53          * file as CONFIG_SYS_SC520_CAR_PAR
  54          */
  55
  56         /* Configure Cache-As-RAM PAR */
  57         movl    $CONFIG_SYS_SC520_CAR_PAR, %eax
  58         movl    $SC520_PAR2, %edi
  59         movl    %eax, (%edi)
  60
  61         /* Trash the cache then turn it on */
  62         wbinvd
  63         movl    %cr0, %eax
  64         andl    $~(X86_CR0_NW | X86_CR0_CD), %eax
  65         movl    %eax, %cr0
  66
  67         /*
  68          * The cache is now enabled and empty. Map a region of memory to
  69          * it by reading that region.
  70          */
  71         movl    $CONFIG_SYS_CAR_ADDR, %esi
  72         movl    $CONFIG_SYS_CAR_SIZE, %ecx
  73         shrl    $2, %ecx                        /* we are reading longs */
  74         cld
  75         rep     lodsl
  76
  77         /* Turn off the cache, but don't trash it */
  78         movl    %cr0, %eax
  79         orl     $(X86_CR0_NW | X86_CR0_CD), %eax
  80         movl    %eax, %cr0
  81
  82         /* Clear the CAR region */
  83         xorl    %eax, %eax
  84         movl    $CONFIG_SYS_CAR_ADDR, %edi
  85         movl    $CONFIG_SYS_CAR_SIZE, %ecx
  86         shrl    $2, %ecx                        /* we are writing longs */
  87         rep     stosl
  88
  89         /*
  90          * Done - We should now have CONFIG_SYS_CAR_SIZE bytes of
  91          * Cache-As-RAM
  92          */
  93         jmp     car_init_ret