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x86: qemu: Enable writing MP table
[people/ms/u-boot.git] / arch / x86 / dts / qemu-x86_q35.dts
1 /*
2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 /dts-v1/;
8
9 #include <dt-bindings/interrupt-router/intel-irq.h>
10
11 /* ICH9 IRQ router has discrete PIRQ control registers */
12 #undef PIRQE
13 #undef PIRQF
14 #undef PIRQG
15 #undef PIRQH
16 #define PIRQE 8
17 #define PIRQF 9
18 #define PIRQG 10
19 #define PIRQH 11
20
21 /include/ "skeleton.dtsi"
22 /include/ "serial.dtsi"
23 /include/ "rtc.dtsi"
24
25 / {
26 model = "QEMU x86 (Q35)";
27 compatible = "qemu,x86";
28
29 config {
30 silent_console = <0>;
31 u-boot,no-apm-finalize;
32 };
33
34 chosen {
35 stdout-path = "/serial";
36 };
37
38 cpus {
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 cpu@0 {
43 device_type = "cpu";
44 compatible = "cpu-x86";
45 reg = <0>;
46 intel,apic-id = <0>;
47 };
48 };
49
50 pci {
51 compatible = "pci-x86";
52 #address-cells = <3>;
53 #size-cells = <2>;
54 u-boot,dm-pre-reloc;
55 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
56 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
57 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
58
59 irq-router@1f,0 {
60 reg = <0x0000f800 0 0 0 0>;
61 compatible = "intel,irq-router";
62 intel,pirq-config = "pci";
63 intel,pirq-link = <0x60 8>;
64 intel,pirq-mask = <0x0e40>;
65 intel,pirq-routing = <
66 /* e1000 NIC */
67 PCI_BDF(0, 2, 0) INTA PIRQG
68 /* ICH9 UHCI */
69 PCI_BDF(0, 29, 0) INTA PIRQA
70 PCI_BDF(0, 29, 1) INTB PIRQB
71 PCI_BDF(0, 29, 2) INTC PIRQC
72 /* ICH9 EHCI */
73 PCI_BDF(0, 29, 7) INTD PIRQD
74 /* ICH9 SATA */
75 PCI_BDF(0, 31, 2) INTA PIRQA
76 >;
77 };
78 };
79
80 };