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1 /*
2 * (C) Copyright 2002
3 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 /*
9 * Support for type PCI configuration cycles.
10 * based on pci_indirect.c
11 */
12 #include <common.h>
13 #include <asm/io.h>
14 #include <pci.h>
15
16 #define cfg_read(val, addr, op) (*val = op((int)(addr)))
17 #define cfg_write(val, addr, op) op((val), (int)(addr))
18
19 #define TYPE1_PCI_OP(rw, size, type, op, mask) \
20 static int \
21 type1_##rw##_config_##size(struct pci_controller *hose, \
22 pci_dev_t dev, int offset, type val) \
23 { \
24 outl(dev | (offset & 0xfc) | 0x80000000, (int)hose->cfg_addr); \
25 cfg_##rw(val, hose->cfg_data + (offset & mask), op); \
26 return 0; \
27 }
28
29 TYPE1_PCI_OP(read, byte, u8 *, inb, 3)
30 TYPE1_PCI_OP(read, word, u16 *, inw, 2)
31 TYPE1_PCI_OP(read, dword, u32 *, inl, 0)
32
33 TYPE1_PCI_OP(write, byte, u8, outb, 3)
34 TYPE1_PCI_OP(write, word, u16, outw, 2)
35 TYPE1_PCI_OP(write, dword, u32, outl, 0)
36
37 /* bus mapping constants (used for PCI core initialization) */
38 #define PCI_REG_ADDR 0x00000cf8
39 #define PCI_REG_DATA 0x00000cfc
40
41 void pci_setup_type1(struct pci_controller *hose)
42 {
43 pci_set_ops(hose,
44 type1_read_config_byte,
45 type1_read_config_word,
46 type1_read_config_dword,
47 type1_write_config_byte,
48 type1_write_config_word,
49 type1_write_config_dword);
50
51 hose->cfg_addr = (unsigned int *)PCI_REG_ADDR;
52 hose->cfg_data = (unsigned char *)PCI_REG_DATA;
53 }