arch/xtensa/include/asm/regs.h

   1 /*
   2  * Copyright (c) 2006 Tensilica, Inc.  All Rights Reserved.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _XTENSA_REGS_H
   8 #define _XTENSA_REGS_H
   9
  10 /*  Special registers  */
  11
  12 #define IBREAKA         128
  13 #define DBREAKA         144
  14 #define DBREAKC         160
  15
  16 /*  Special names for read-only and write-only interrupt registers  */
  17
  18 #define INTREAD         226
  19 #define INTSET          226
  20 #define INTCLEAR        227
  21
  22 /*  EXCCAUSE register fields  */
  23
  24 #define EXCCAUSE_EXCCAUSE_SHIFT 0
  25 #define EXCCAUSE_EXCCAUSE_MASK  0x3F
  26
  27 #define EXCCAUSE_ILLEGAL_INSTRUCTION            0
  28 #define EXCCAUSE_SYSTEM_CALL                    1
  29 #define EXCCAUSE_INSTRUCTION_FETCH_ERROR        2
  30 #define EXCCAUSE_LOAD_STORE_ERROR               3
  31 #define EXCCAUSE_LEVEL1_INTERRUPT               4
  32 #define EXCCAUSE_ALLOCA                         5
  33 #define EXCCAUSE_INTEGER_DIVIDE_BY_ZERO         6
  34 #define EXCCAUSE_SPECULATION                    7
  35 #define EXCCAUSE_PRIVILEGED                     8
  36 #define EXCCAUSE_UNALIGNED                      9
  37 #define EXCCAUSE_INSTR_DATA_ERROR               12
  38 #define EXCCAUSE_LOAD_STORE_DATA_ERROR          13
  39 #define EXCCAUSE_INSTR_ADDR_ERROR               14
  40 #define EXCCAUSE_LOAD_STORE_ADDR_ERROR          15
  41 #define EXCCAUSE_ITLB_MISS                      16
  42 #define EXCCAUSE_ITLB_MULTIHIT                  17
  43 #define EXCCAUSE_ITLB_PRIVILEGE                 18
  44 #define EXCCAUSE_ITLB_SIZE_RESTRICTION          19
  45 #define EXCCAUSE_FETCH_CACHE_ATTRIBUTE          20
  46 #define EXCCAUSE_DTLB_MISS                      24
  47 #define EXCCAUSE_DTLB_MULTIHIT                  25
  48 #define EXCCAUSE_DTLB_PRIVILEGE                 26
  49 #define EXCCAUSE_DTLB_SIZE_RESTRICTION          27
  50 #define EXCCAUSE_LOAD_CACHE_ATTRIBUTE           28
  51 #define EXCCAUSE_STORE_CACHE_ATTRIBUTE          29
  52 #define EXCCAUSE_COPROCESSOR0_DISABLED          32
  53 #define EXCCAUSE_COPROCESSOR1_DISABLED          33
  54 #define EXCCAUSE_COPROCESSOR2_DISABLED          34
  55 #define EXCCAUSE_COPROCESSOR3_DISABLED          35
  56 #define EXCCAUSE_COPROCESSOR4_DISABLED          36
  57 #define EXCCAUSE_COPROCESSOR5_DISABLED          37
  58 #define EXCCAUSE_COPROCESSOR6_DISABLED          38
  59 #define EXCCAUSE_COPROCESSOR7_DISABLED          39
  60 #define EXCCAUSE_LAST                           63
  61
  62 /*  PS register fields  */
  63
  64 #define PS_WOE_BIT              18
  65 #define PS_CALLINC_SHIFT        16
  66 #define PS_CALLINC_MASK         0x00030000
  67 #define PS_OWB_SHIFT            8
  68 #define PS_OWB_MASK             0x00000F00
  69 #define PS_RING_SHIFT           6
  70 #define PS_RING_MASK            0x000000C0
  71 #define PS_UM_BIT               5
  72 #define PS_EXCM_BIT             4
  73 #define PS_INTLEVEL_SHIFT       0
  74 #define PS_INTLEVEL_MASK        0x0000000F
  75
  76 /*  DBREAKCn register fields  */
  77
  78 #define DBREAKC_MASK_BIT                0
  79 #define DBREAKC_MASK_MASK               0x0000003F
  80 #define DBREAKC_LOAD_BIT                30
  81 #define DBREAKC_LOAD_MASK               0x40000000
  82 #define DBREAKC_STOR_BIT                31
  83 #define DBREAKC_STOR_MASK               0x80000000
  84
  85 /*  DEBUGCAUSE register fields  */
  86
  87 #define DEBUGCAUSE_DEBUGINT_BIT         5       /* External debug interrupt */
  88 #define DEBUGCAUSE_BREAKN_BIT           4       /* BREAK.N instruction */
  89 #define DEBUGCAUSE_BREAK_BIT            3       /* BREAK instruction */
  90 #define DEBUGCAUSE_DBREAK_BIT           2       /* DBREAK match */
  91 #define DEBUGCAUSE_IBREAK_BIT           1       /* IBREAK match */
  92 #define DEBUGCAUSE_ICOUNT_BIT           0       /* ICOUNT would incr. to zero */
  93
  94 #endif /* _XTENSA_SPECREG_H */
  95