4 * Pinmux Setting for B&R LEIT Board(s)
6 * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
7 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
9 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/sys_proto.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/mux.h>
19 static struct module_pin_mux uart0_pin_mux
[] = {
21 {OFFSET(uart0_rtsn
), (MODE(0) | PULLUDEN
)},
23 {OFFSET(uart0_ctsn
), (MODE(0) | PULLUDEN
| PULLUP_EN
| RXACTIVE
)},
25 {OFFSET(uart0_rxd
), (MODE(0) | PULLUDEN
| PULLUP_EN
| RXACTIVE
)},
27 {OFFSET(uart0_txd
), (MODE(0) | PULLUDEN
)},
30 static struct module_pin_mux uart1_pin_mux
[] = {
31 /* UART1_RTS as I2C2-SCL */
32 {OFFSET(uart1_rtsn
), (MODE(3) | PULLUDEN
| PULLUP_EN
| RXACTIVE
)},
33 /* UART1_CTS as I2C2-SDA */
34 {OFFSET(uart1_ctsn
), (MODE(3) | PULLUDEN
| PULLUP_EN
| RXACTIVE
)},
36 {OFFSET(uart1_rxd
), (MODE(0) | PULLUDEN
| PULLUP_EN
| RXACTIVE
)},
38 {OFFSET(uart1_txd
), (MODE(0) | PULLUDEN
)},
42 static struct module_pin_mux mmc1_pin_mux
[] = {
43 {OFFSET(gpmc_ad7
), (MODE(1) | RXACTIVE
| PULLUP_EN
)}, /* MMC1_DAT7 */
44 {OFFSET(gpmc_ad6
), (MODE(1) | RXACTIVE
| PULLUP_EN
)}, /* MMC1_DAT6 */
45 {OFFSET(gpmc_ad5
), (MODE(1) | RXACTIVE
| PULLUP_EN
)}, /* MMC1_DAT5 */
46 {OFFSET(gpmc_ad4
), (MODE(1) | RXACTIVE
| PULLUP_EN
)}, /* MMC1_DAT4 */
48 {OFFSET(gpmc_ad3
), (MODE(1) | RXACTIVE
| PULLUP_EN
)}, /* MMC1_DAT3 */
49 {OFFSET(gpmc_ad2
), (MODE(1) | RXACTIVE
| PULLUP_EN
)}, /* MMC1_DAT2 */
50 {OFFSET(gpmc_ad1
), (MODE(1) | RXACTIVE
| PULLUP_EN
)}, /* MMC1_DAT1 */
51 {OFFSET(gpmc_ad0
), (MODE(1) | RXACTIVE
| PULLUP_EN
)}, /* MMC1_DAT0 */
52 {OFFSET(gpmc_csn1
), (MODE(2) | RXACTIVE
| PULLUP_EN
)}, /* MMC1_CLK */
53 {OFFSET(gpmc_csn2
), (MODE(2) | RXACTIVE
| PULLUP_EN
)}, /* MMC1_CMD */
54 {OFFSET(gpmc_csn0
), (MODE(7) | RXACTIVE
| PULLUP_EN
)}, /* MMC1_WP */
55 {OFFSET(gpmc_advn_ale
), (MODE(7) | RXACTIVE
| PULLUP_EN
)},/* MMC1_CD */
59 static struct module_pin_mux i2c0_pin_mux
[] = {
61 {OFFSET(i2c0_sda
), (MODE(0) | RXACTIVE
| PULLUDEN
| SLEWCTRL
)},
63 {OFFSET(i2c0_scl
), (MODE(0) | RXACTIVE
| PULLUDEN
| SLEWCTRL
)},
67 static struct module_pin_mux spi0_pin_mux
[] = {
69 {OFFSET(spi0_sclk
), (MODE(0) | RXACTIVE
| PULLUDEN
| PULLUP_EN
)},
71 {OFFSET(spi0_d0
), (MODE(0) | RXACTIVE
| PULLUDEN
| PULLUP_EN
)},
73 {OFFSET(spi0_d1
), (MODE(0) | RXACTIVE
| PULLUDEN
| PULLUP_EN
)},
75 {OFFSET(spi0_cs0
), (MODE(0) | RXACTIVE
| PULLUDEN
| PULLUP_EN
)},
79 static struct module_pin_mux mii1_pin_mux
[] = {
80 {OFFSET(mii1_crs
), MODE(0) | RXACTIVE
}, /* MII1_CRS */
81 {OFFSET(mii1_col
), MODE(0) | RXACTIVE
}, /* MII1_COL */
82 {OFFSET(mii1_rxerr
), MODE(0) | RXACTIVE
}, /* MII1_RXERR */
83 {OFFSET(mii1_txen
), MODE(0)}, /* MII1_TXEN */
84 {OFFSET(mii1_rxdv
), MODE(0) | RXACTIVE
}, /* MII1_RXDV */
85 {OFFSET(mii1_txd3
), MODE(0)}, /* MII1_TXD3 */
86 {OFFSET(mii1_txd2
), MODE(0)}, /* MII1_TXD2 */
87 {OFFSET(mii1_txd1
), MODE(0)}, /* MII1_TXD1 */
88 {OFFSET(mii1_txd0
), MODE(0)}, /* MII1_TXD0 */
89 {OFFSET(mii1_txclk
), MODE(0) | RXACTIVE
}, /* MII1_TXCLK */
90 {OFFSET(mii1_rxclk
), MODE(0) | RXACTIVE
}, /* MII1_RXCLK */
91 {OFFSET(mii1_rxd3
), MODE(0) | RXACTIVE
}, /* MII1_RXD3 */
92 {OFFSET(mii1_rxd2
), MODE(0) | RXACTIVE
}, /* MII1_RXD2 */
93 {OFFSET(mii1_rxd1
), MODE(0) | RXACTIVE
}, /* MII1_RXD1 */
94 {OFFSET(mii1_rxd0
), MODE(0) | RXACTIVE
}, /* MII1_RXD0 */
95 {OFFSET(mdio_data
), MODE(0) | RXACTIVE
| PULLUP_EN
},/* MDIO_DATA */
96 {OFFSET(mdio_clk
), MODE(0) | PULLUP_EN
}, /* MDIO_CLK */
100 static struct module_pin_mux mii2_pin_mux
[] = {
101 {OFFSET(gpmc_a0
), MODE(1)}, /* MII2_TXEN */
102 {OFFSET(gpmc_a1
), MODE(1) | RXACTIVE
}, /* MII2_RXDV */
103 {OFFSET(gpmc_a2
), MODE(1)}, /* MII2_TXD3 */
104 {OFFSET(gpmc_a3
), MODE(1)}, /* MII2_TXD2 */
105 {OFFSET(gpmc_a4
), MODE(1)}, /* MII2_TXD1 */
106 {OFFSET(gpmc_a5
), MODE(1)}, /* MII2_TXD0 */
107 {OFFSET(gpmc_a6
), MODE(1) | RXACTIVE
}, /* MII2_TXCLK */
108 {OFFSET(gpmc_a7
), MODE(1) | RXACTIVE
}, /* MII2_RXCLK */
109 {OFFSET(gpmc_a8
), MODE(1) | RXACTIVE
}, /* MII2_RXD3 */
110 {OFFSET(gpmc_a9
), MODE(1) | RXACTIVE
}, /* MII2_RXD2 */
111 {OFFSET(gpmc_a10
), MODE(1) | RXACTIVE
}, /* MII2_RXD1 */
112 {OFFSET(gpmc_a11
), MODE(1) | RXACTIVE
}, /* MII2_RXD0 */
113 {OFFSET(gpmc_wpn
), (MODE(1) | RXACTIVE
)},/* MII2_RXERR */
114 {OFFSET(gpmc_wait0
), (MODE(1) | RXACTIVE
| PULLUP_EN
)},
116 * MII2_CRS is shared with
119 {OFFSET(gpmc_be1n
), (MODE(1) | RXACTIVE
)},/* MII1_COL */
123 static struct module_pin_mux nand_pin_mux
[] = {
124 {OFFSET(gpmc_ad0
), (MODE(0) | PULLUP_EN
| RXACTIVE
)}, /* NAND AD0 */
125 {OFFSET(gpmc_ad1
), (MODE(0) | PULLUP_EN
| RXACTIVE
)}, /* NAND AD1 */
126 {OFFSET(gpmc_ad2
), (MODE(0) | PULLUP_EN
| RXACTIVE
)}, /* NAND AD2 */
127 {OFFSET(gpmc_ad3
), (MODE(0) | PULLUP_EN
| RXACTIVE
)}, /* NAND AD3 */
128 {OFFSET(gpmc_ad4
), (MODE(0) | PULLUP_EN
| RXACTIVE
)}, /* NAND AD4 */
129 {OFFSET(gpmc_ad5
), (MODE(0) | PULLUP_EN
| RXACTIVE
)}, /* NAND AD5 */
130 {OFFSET(gpmc_ad6
), (MODE(0) | PULLUP_EN
| RXACTIVE
)}, /* NAND AD6 */
131 {OFFSET(gpmc_ad7
), (MODE(0) | PULLUP_EN
| RXACTIVE
)}, /* NAND AD7 */
132 {OFFSET(gpmc_clk
), (MODE(2) | RXACTIVE
| PULLUP_EN
)}, /* NAND WAIT */
133 {OFFSET(gpmc_wpn
), (MODE(7) | PULLUP_EN
| RXACTIVE
)}, /* NAND_WPN */
134 {OFFSET(gpmc_csn0
), (MODE(0) | PULLUDEN
)}, /* NAND_CS0 */
135 {OFFSET(gpmc_advn_ale
), (MODE(0) | PULLUDEN
)}, /* NAND_ADV_ALE */
136 {OFFSET(gpmc_oen_ren
), (MODE(0) | PULLUDEN
)}, /* NAND_OE */
137 {OFFSET(gpmc_wen
), (MODE(0) | PULLUDEN
)}, /* NAND_WEN */
138 {OFFSET(gpmc_be0n_cle
), (MODE(0) | PULLUDEN
)}, /* NAND_BE_CLE */
142 static struct module_pin_mux gpIOs
[] = {
143 /* GPIO0_6 (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */
144 {OFFSET(spi0_cs1
), (MODE(7) | PULLUDEN
| PULLUP_EN
| RXACTIVE
)},
145 /* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */
146 {OFFSET(mmc0_dat3
), (MODE(3) | PULLUDEN
| RXACTIVE
)},
147 /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3 */
148 {OFFSET(mmc0_dat2
), (MODE(3) | PULLUDEN
| RXACTIVE
)},
149 /* GPIO2_28 (MMC0_DAT1) - MII_nNAND */
150 {OFFSET(mmc0_dat1
), (MODE(7) | PULLUDEN
| RXACTIVE
)},
151 /* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */
152 {OFFSET(mmc0_dat0
), (MODE(7) | PULLUDEN
| RXACTIVE
)},
153 /* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */
154 {OFFSET(mmc0_clk
), (MODE(7) | PULLUDEN
| PULLUP_EN
| RXACTIVE
)},
155 /* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */
156 {OFFSET(mcasp0_aclkr
), (MODE(7) | PULLUDEN
| PULLUP_EN
| RXACTIVE
)},
157 /* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */
158 {OFFSET(mcasp0_fsr
), (MODE(7) | PULLUDEN
| PULLUP_EN
| RXACTIVE
)},
159 /* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */
160 {OFFSET(mcasp0_axr1
), (MODE(7) | PULLUDEN
| PULLUP_EN
| RXACTIVE
)},
161 /* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */
162 {OFFSET(mcasp0_ahclkx
), (MODE(7) | PULLUDEN
| PULLUP_EN
| RXACTIVE
)},
163 /* GPIO2_0 (GPMC_nCS3) - DCOK */
164 {OFFSET(gpmc_csn3
), (MODE(7) | PULLUDDIS
| RXACTIVE
) },
165 /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
166 {OFFSET(rmii1_refclk
), (MODE(7) | PULLUDDIS
| RXACTIVE
) },
169 * DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
171 {OFFSET(ecap0_in_pwm0_out
), (MODE(7) | PULLUDEN
| RXACTIVE
)},
172 /* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */
173 {OFFSET(xdma_event_intr0
), (MODE(7) | PULLUDEN
| PULLUP_EN
| RXACTIVE
)},
174 /* GPIO0_20 (DMA_INTR1) - REP-Switch */
175 {OFFSET(xdma_event_intr1
), (MODE(7) | PULLUP_EN
| RXACTIVE
)},
176 /* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */
177 {OFFSET(mcasp0_aclkx
), (MODE(7) | PULLUDEN
| PULLUP_EN
| RXACTIVE
) },
178 /* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */
179 {OFFSET(mcasp0_fsx
), (MODE(7) | PULLUDEN
| PULLUP_EN
| RXACTIVE
) },
180 /* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */
181 {OFFSET(mcasp0_axr0
), (MODE(7) | PULLUDDIS
) },
182 /* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
183 {OFFSET(mcasp0_ahclkr
), (MODE(7) | PULLUDDIS
) },
185 /* GPIO2_3 - NAND_OE */
186 {OFFSET(gpmc_oen_ren
), (MODE(7) | PULLDOWN_EN
| RXACTIVE
)},
187 /* GPIO2_4 - NAND_WEN */
188 {OFFSET(gpmc_wen
), (MODE(7) | PULLDOWN_EN
| RXACTIVE
)},
189 /* GPIO2_5 - NAND_BE_CLE */
190 {OFFSET(gpmc_be0n_cle
), (MODE(7) | PULLDOWN_EN
| RXACTIVE
)},
195 static struct module_pin_mux lcd_pin_mux
[] = {
196 {OFFSET(lcd_data0
), (MODE(0) | PULLUDDIS
)}, /* LCD-Data(0) */
197 {OFFSET(lcd_data1
), (MODE(0) | PULLUDDIS
)}, /* LCD-Data(1) */
198 {OFFSET(lcd_data2
), (MODE(0) | PULLUDDIS
)}, /* LCD-Data(2) */
199 {OFFSET(lcd_data3
), (MODE(0) | PULLUDDIS
)}, /* LCD-Data(3) */
200 {OFFSET(lcd_data4
), (MODE(0) | PULLUDDIS
)}, /* LCD-Data(4) */
201 {OFFSET(lcd_data5
), (MODE(0) | PULLUDDIS
)}, /* LCD-Data(5) */
202 {OFFSET(lcd_data6
), (MODE(0) | PULLUDDIS
)}, /* LCD-Data(6) */
203 {OFFSET(lcd_data7
), (MODE(0) | PULLUDDIS
)}, /* LCD-Data(7) */
204 {OFFSET(lcd_data8
), (MODE(0) | PULLUDDIS
)}, /* LCD-Data(8) */
205 {OFFSET(lcd_data9
), (MODE(0) | PULLUDDIS
)}, /* LCD-Data(9) */
206 {OFFSET(lcd_data10
), (MODE(0) | PULLUDDIS
)}, /* LCD-Data(10) */
207 {OFFSET(lcd_data11
), (MODE(0) | PULLUDDIS
)}, /* LCD-Data(11) */
208 {OFFSET(lcd_data12
), (MODE(0) | PULLUDDIS
)}, /* LCD-Data(12) */
209 {OFFSET(lcd_data13
), (MODE(0) | PULLUDDIS
)}, /* LCD-Data(13) */
210 {OFFSET(lcd_data14
), (MODE(0) | PULLUDDIS
)}, /* LCD-Data(14) */
211 {OFFSET(lcd_data15
), (MODE(0) | PULLUDDIS
)}, /* LCD-Data(15) */
213 {OFFSET(gpmc_ad8
), (MODE(1) | PULLUDDIS
)}, /* LCD-Data(16) */
214 {OFFSET(gpmc_ad9
), (MODE(1) | PULLUDDIS
)}, /* LCD-Data(17) */
215 {OFFSET(gpmc_ad10
), (MODE(1) | PULLUDDIS
)}, /* LCD-Data(18) */
216 {OFFSET(gpmc_ad11
), (MODE(1) | PULLUDDIS
)}, /* LCD-Data(19) */
217 {OFFSET(gpmc_ad12
), (MODE(1) | PULLUDDIS
)}, /* LCD-Data(20) */
218 {OFFSET(gpmc_ad13
), (MODE(1) | PULLUDDIS
)}, /* LCD-Data(21) */
219 {OFFSET(gpmc_ad14
), (MODE(1) | PULLUDDIS
)}, /* LCD-Data(22) */
220 {OFFSET(gpmc_ad15
), (MODE(1) | PULLUDDIS
)}, /* LCD-Data(23) */
222 {OFFSET(lcd_vsync
), (MODE(0) | PULLUDDIS
)}, /* LCD-VSync */
223 {OFFSET(lcd_hsync
), (MODE(0) | PULLUDDIS
)}, /* LCD-HSync */
224 {OFFSET(lcd_ac_bias_en
), (MODE(0) | PULLUDDIS
)},/* LCD-DE */
225 {OFFSET(lcd_pclk
), (MODE(0) | PULLUDDIS
)}, /* LCD-CLK */
230 void enable_uart0_pin_mux(void)
232 configure_module_pin_mux(uart0_pin_mux
);
235 void enable_i2c_pin_mux(void)
237 configure_module_pin_mux(i2c0_pin_mux
);
240 void enable_board_pin_mux(void)
242 configure_module_pin_mux(i2c0_pin_mux
);
243 configure_module_pin_mux(mii1_pin_mux
);
244 configure_module_pin_mux(mii2_pin_mux
);
246 configure_module_pin_mux(nand_pin_mux
);
247 #elif defined(CONFIG_MMC)
248 configure_module_pin_mux(mmc1_pin_mux
);
250 configure_module_pin_mux(spi0_pin_mux
);
251 configure_module_pin_mux(lcd_pin_mux
);
252 configure_module_pin_mux(uart1_pin_mux
);
253 configure_module_pin_mux(gpIOs
);
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