board/BuS/EB+MCF-EV123/mii.c

   1 /*
   2  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   3  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/fec.h>
  26 #include <asm/immap.h>
  27
  28 #include <config.h>
  29 #include <net.h>
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
  34 #undef MII_DEBUG
  35 #undef ET_DEBUG
  36
  37 int fecpin_setclear(struct eth_device *dev, int setclear)
  38 {
  39         if (setclear) {
  40                 MCFGPIO_PASPAR |= 0x0F00;
  41                 MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
  42         } else {
  43                 MCFGPIO_PASPAR &= 0xF0FF;
  44                 MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
  45         }
  46         return 0;
  47 }
  48
  49 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
  50 #include <miiphy.h>
  51
  52 /* Make MII read/write commands for the FEC. */
  53 #define mk_mii_read(ADDR, REG)  (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
  54
  55 #define mk_mii_write(ADDR, REG, VAL)    (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
  56
  57 /* PHY identification */
  58 #define PHY_ID_LXT970           0x78100000      /* LXT970 */
  59 #define PHY_ID_LXT971           0x001378e0      /* LXT971 and 972 */
  60 #define PHY_ID_82555            0x02a80150      /* Intel 82555 */
  61 #define PHY_ID_QS6612           0x01814400      /* QS6612 */
  62 #define PHY_ID_AMD79C784        0x00225610      /* AMD 79C784 */
  63 #define PHY_ID_AMD79C874VC      0x0022561B      /* AMD 79C874 */
  64 #define PHY_ID_LSI80225         0x0016f870      /* LSI 80225 */
  65 #define PHY_ID_LSI80225B        0x0016f880      /* LSI 80225/B */
  66 #define PHY_ID_DP83848VV        0x20005C90      /* National 83848 */
  67 #define PHY_ID_DP83849          0x20005CA2      /* National 82849 */
  68
  69 #define STR_ID_LXT970           "LXT970"
  70 #define STR_ID_LXT971           "LXT971"
  71 #define STR_ID_82555            "Intel82555"
  72 #define STR_ID_QS6612           "QS6612"
  73 #define STR_ID_AMD79C784        "AMD79C784"
  74 #define STR_ID_AMD79C874VC      "AMD79C874VC"
  75 #define STR_ID_LSI80225         "LSI80225"
  76 #define STR_ID_LSI80225B        "LSI80225/B"
  77 #define STR_ID_DP83848VV        "N83848"
  78 #define STR_ID_DP83849          "N83849"
  79
  80 /****************************************************************************
  81  * mii_init -- Initialize the MII for MII command without ethernet
  82  * This function is a subset of eth_init
  83  ****************************************************************************
  84  */
  85 void mii_reset(struct fec_info_s *info)
  86 {
  87         volatile fec_t *fecp = (fec_t *) (info->miibase);
  88         int i;
  89
  90         fecp->ecr = FEC_ECR_RESET;
  91         for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
  92                 udelay(1);
  93         }
  94         if (i == FEC_RESET_DELAY) {
  95                 printf("FEC_RESET_DELAY timeout\n");
  96         }
  97 }
  98
  99 /* send command to phy using mii, wait for result */
 100 uint mii_send(uint mii_cmd)
 101 {
 102         struct fec_info_s *info;
 103         struct eth_device *dev;
 104         volatile fec_t *ep;
 105         uint mii_reply;
 106         int j = 0;
 107
 108         /* retrieve from register structure */
 109         dev = eth_get_dev();
 110         info = dev->priv;
 111
 112         ep = (fec_t *) info->miibase;
 113
 114         ep->mmfr = mii_cmd;     /* command to phy */
 115
 116         /* wait for mii complete */
 117         while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
 118                 udelay(1);
 119                 j++;
 120         }
 121         if (j >= MCFFEC_TOUT_LOOP) {
 122                 printf("MII not complete\n");
 123                 return -1;
 124         }
 125
 126         mii_reply = ep->mmfr;   /* result from phy */
 127         ep->eir = FEC_EIR_MII;  /* clear MII complete */
 128 #ifdef ET_DEBUG
 129         printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
 130                __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
 131 #endif
 132
 133         return (mii_reply & 0xffff);    /* data read from phy */
 134 }
 135 #endif                          /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
 136
 137 #if defined(CONFIG_SYS_DISCOVER_PHY)
 138 int mii_discover_phy(struct eth_device *dev)
 139 {
 140 #define MAX_PHY_PASSES 11
 141         struct fec_info_s *info = dev->priv;
 142         int phyaddr, pass;
 143         uint phyno, phytype;
 144
 145         if (info->phyname_init)
 146                 return info->phy_addr;
 147
 148         phyaddr = -1;           /* didn't find a PHY yet */
 149         for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
 150                 if (pass > 1) {
 151                         /* PHY may need more time to recover from reset.
 152                          * The LXT970 needs 50ms typical, no maximum is
 153                          * specified, so wait 10ms before try again.
 154                          * With 11 passes this gives it 100ms to wake up.
 155                          */
 156                         udelay(10000);  /* wait 10ms */
 157                 }
 158
 159                 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
 160
 161                         phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
 162 #ifdef ET_DEBUG
 163                         printf("PHY type 0x%x pass %d type\n", phytype, pass);
 164 #endif
 165                         if (phytype != 0xffff) {
 166                                 phyaddr = phyno;
 167                                 phytype <<= 16;
 168                                 phytype |=
 169                                     mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
 170
 171                                 switch (phytype & 0xffffffff) {
 172                                 case PHY_ID_AMD79C874VC:
 173                                         strcpy(info->phy_name,
 174                                                STR_ID_AMD79C874VC);
 175                                         info->phyname_init = 1;
 176                                         break;
 177                                 default:
 178                                         strcpy(info->phy_name, "unknown");
 179                                         info->phyname_init = 1;
 180                                         break;
 181                                 }
 182
 183 #ifdef ET_DEBUG
 184                                 printf("PHY @ 0x%x pass %d type ", phyno, pass);
 185                                 switch (phytype & 0xffffffff) {
 186                                 case PHY_ID_AMD79C874VC:
 187                                         printf(STR_ID_AMD79C874VC);
 188                                         break;
 189                                 default:
 190                                         printf("0x%08x\n", phytype);
 191                                         break;
 192                                 }
 193 #endif
 194                         }
 195                 }
 196         }
 197         if (phyaddr < 0)
 198                 printf("No PHY device found.\n");
 199
 200         return phyaddr;
 201 }
 202 #endif                          /* CONFIG_SYS_DISCOVER_PHY */
 203
 204 void mii_init(void) __attribute__((weak,alias("__mii_init")));
 205
 206 void __mii_init(void)
 207 {
 208         volatile fec_t *fecp;
 209         struct fec_info_s *info;
 210         struct eth_device *dev;
 211         int miispd = 0, i = 0;
 212         u16 autoneg = 0;
 213
 214         /* retrieve from register structure */
 215         dev = eth_get_dev();
 216         info = dev->priv;
 217
 218         fecp = (fec_t *) info->miibase;
 219
 220         fecpin_setclear(dev, 1);
 221
 222         mii_reset(info);
 223
 224         /* We use strictly polling mode only */
 225         fecp->eimr = 0;
 226
 227         /* Clear any pending interrupt */
 228         fecp->eir = 0xffffffff;
 229
 230         /* Set MII speed */
 231         miispd = (gd->bus_clk / 1000000) / 5;
 232         fecp->mscr = miispd << 1;
 233
 234         info->phy_addr = mii_discover_phy(dev);
 235
 236 #define AUTONEGLINK             (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
 237         while (i < MCFFEC_TOUT_LOOP) {
 238                 autoneg = 0;
 239                 miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
 240                 i++;
 241
 242                 if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
 243                         break;
 244
 245                 udelay(500);
 246         }
 247         if (i >= MCFFEC_TOUT_LOOP) {
 248                 printf("Auto Negotiation not complete\n");
 249         }
 250
 251         /* adapt to the half/full speed settings */
 252         info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
 253         info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
 254 }
 255
 256 /*****************************************************************************
 257  * Read and write a MII PHY register, routines used by MII Utilities
 258  *
 259  * FIXME: These routines are expected to return 0 on success, but mii_send
 260  *        does _not_ return an error code. Maybe 0xFFFF means error, i.e.
 261  *        no PHY connected...
 262  *        For now always return 0.
 263  * FIXME: These routines only work after calling eth_init() at least once!
 264  *        Otherwise they hang in mii_send() !!! Sorry!
 265  *****************************************************************************/
 266
 267 int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
 268                        unsigned short *value)
 269 {
 270         short rdreg;            /* register working value */
 271
 272 #ifdef MII_DEBUG
 273         printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
 274 #endif
 275         rdreg = mii_send(mk_mii_read(addr, reg));
 276
 277         *value = rdreg;
 278
 279 #ifdef MII_DEBUG
 280         printf("0x%04x\n", *value);
 281 #endif
 282
 283         return 0;
 284 }
 285
 286 int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
 287                         unsigned short value)
 288 {
 289         short rdreg;            /* register working value */
 290
 291 #ifdef MII_DEBUG
 292         printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
 293 #endif
 294
 295         rdreg = mii_send(mk_mii_write(addr, reg, value));
 296
 297 #ifdef MII_DEBUG
 298         printf("0x%04x\n", value);
 299 #endif
 300
 301         return 0;
 302 }
 303
 304 #endif                          /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */