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1 /*
2 * (C) Copyright 2001
3 * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 /*************************************************************************
25 * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
26 *
27 ************************************************************************/
28
29 /*
30 * mpsc.c - driver for console over the MPSC.
31 */
32
33
34 #include <common.h>
35 #include <config.h>
36 #include <asm/cache.h>
37
38 #include <malloc.h>
39 #include "mpsc.h"
40
41 #include "mv_regs.h"
42
43 #include "../include/memory.h"
44
45 /* Define this if you wish to use the MPSC as a register based UART.
46 * This will force the serial port to not use the SDMA engine at all.
47 */
48 #undef CONFIG_MPSC_DEBUG_PORT
49
50
51 int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
52 char (*mpsc_getchar) (void) = mpsc_getchar_debug;
53 int (*mpsc_test_char) (void) = mpsc_test_char_debug;
54
55
56 static volatile unsigned int *rx_desc_base = NULL;
57 static unsigned int rx_desc_index = 0;
58 static volatile unsigned int *tx_desc_base = NULL;
59 static unsigned int tx_desc_index = 0;
60
61 /* local function declarations */
62 static int galmpsc_connect (int channel, int connect);
63 static int galmpsc_route_rx_clock (int channel, int brg);
64 static int galmpsc_route_tx_clock (int channel, int brg);
65 static int galmpsc_write_config_regs (int mpsc, int mode);
66 static int galmpsc_config_channel_regs (int mpsc);
67 static int galmpsc_set_char_length (int mpsc, int value);
68 static int galmpsc_set_stop_bit_length (int mpsc, int value);
69 static int galmpsc_set_parity (int mpsc, int value);
70 static int galmpsc_enter_hunt (int mpsc);
71 static int galmpsc_set_brkcnt (int mpsc, int value);
72 static int galmpsc_set_tcschar (int mpsc, int value);
73 static int galmpsc_set_snoop (int mpsc, int value);
74 static int galmpsc_shutdown (int mpsc);
75
76 static int galsdma_set_RFT (int channel);
77 static int galsdma_set_SFM (int channel);
78 static int galsdma_set_rxle (int channel);
79 static int galsdma_set_txle (int channel);
80 static int galsdma_set_burstsize (int channel, unsigned int value);
81 static int galsdma_set_RC (int channel, unsigned int value);
82
83 static int galbrg_set_CDV (int channel, int value);
84 static int galbrg_enable (int channel);
85 static int galbrg_disable (int channel);
86 static int galbrg_set_clksrc (int channel, int value);
87 static int galbrg_set_CUV (int channel, int value);
88
89 static void galsdma_enable_rx (void);
90 static int galsdma_set_mem_space (unsigned int memSpace,
91 unsigned int memSpaceTarget,
92 unsigned int memSpaceAttr,
93 unsigned int baseAddress,
94 unsigned int size);
95
96
97 #define SOFTWARE_CACHE_MANAGEMENT
98
99 #ifdef SOFTWARE_CACHE_MANAGEMENT
100 #define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
101 #define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
102 #define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
103 #else
104 #define FLUSH_DCACHE(a,b)
105 #define FLUSH_AND_INVALIDATE_DCACHE(a,b)
106 #define INVALIDATE_DCACHE(a,b)
107 #endif
108
109 #ifdef CONFIG_MPSC_DEBUG_PORT
110 static void mpsc_debug_init (void)
111 {
112
113 volatile unsigned int temp;
114
115 /* Clear the CFR (CHR4) */
116 /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
117 temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_indent: Standard input:229: Warning:old style assignment ambiguity in "=&". Assuming "= &"
118
119 REG_GAP));
120 temp &= 0xffffff00;
121 temp |= BIT29;
122 GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
123 temp);
124
125 /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
126 temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
127 temp |= (BIT12 | BIT15);
128 GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
129 temp);
130
131 /* Set int mask */
132 temp = GTREGREAD (GALMPSC_0_INT_MASK);
133 temp |= BIT6;
134 GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
135 }
136 #endif
137
138 char mpsc_getchar_debug (void)
139 {
140 volatile int temp;
141 volatile unsigned int cause;
142
143 cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
144 while ((cause & BIT6) == 0) {
145 cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
146 }
147
148 temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
149 (CHANNEL * GALMPSC_REG_GAP));
150 /* By writing 1's to the set bits, the register is cleared */
151 GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
152 temp);
153 GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
154 return (temp >> 16) & 0xff;
155 }
156
157 /* special function for running out of flash. doesn't modify any
158 * global variables [josh] */
159 int mpsc_putchar_early (char ch)
160 {
161 DECLARE_GLOBAL_DATA_PTR;
162 int mpsc = CHANNEL;
163 int temp =
164 GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
165 galmpsc_set_tcschar (mpsc, ch);
166 GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
167 temp | 0x200);
168
169 #define MAGIC_FACTOR (10*1000000)
170
171 udelay (MAGIC_FACTOR / gd->baudrate);
172 return 0;
173 }
174
175 /* This is used after relocation, see serial.c and mpsc_init2 */
176 static int mpsc_putchar_sdma (char ch)
177 {
178 volatile unsigned int *p;
179 unsigned int temp;
180
181
182 /* align the descriptor */
183 p = tx_desc_base;
184 memset ((void *) p, 0, 8 * sizeof (unsigned int));
185
186 /* fill one 64 bit buffer */
187 /* word swap, pad with 0 */
188 p[4] = 0; /* x */
189 p[5] = (unsigned int) ch; /* x */
190
191 /* CHANGED completely according to GT64260A dox - NTL */
192 p[0] = 0x00010001; /* 0 */
193 p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */
194 p[2] = 0; /* 8 */
195 p[3] = (unsigned int) &p[4]; /* c */
196
197 #if 0
198 p[9] = DESC_FIRST | DESC_LAST;
199 p[10] = (unsigned int) &p[0];
200 p[11] = (unsigned int) &p[12];
201 #endif
202
203 FLUSH_DCACHE (&p[0], &p[8]);
204
205 GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
206 (unsigned int) &p[0]);
207 GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
208 (unsigned int) &p[0]);
209
210 temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
211 temp |= (TX_DEMAND | TX_STOP);
212 GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
213
214 INVALIDATE_DCACHE (&p[1], &p[2]);
215
216 while (p[1] & DESC_OWNER_BIT) {
217 udelay (100);
218 INVALIDATE_DCACHE (&p[1], &p[2]);
219 }
220 return 0;
221 }
222
223 char mpsc_getchar_sdma (void)
224 {
225 static unsigned int done = 0;
226 volatile char ch;
227 unsigned int len = 0, idx = 0, temp;
228
229 volatile unsigned int *p;
230
231
232 do {
233 p = &rx_desc_base[rx_desc_index * 8];
234
235 INVALIDATE_DCACHE (&p[0], &p[1]);
236 /* Wait for character */
237 while (p[1] & DESC_OWNER_BIT) {
238 udelay (100);
239 INVALIDATE_DCACHE (&p[0], &p[1]);
240 }
241
242 /* Handle error case */
243 if (p[1] & (1 << 15)) {
244 printf ("oops, error: %08x\n", p[1]);
245
246 temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
247 (CHANNEL * GALMPSC_REG_GAP));
248 temp |= (1 << 23);
249 GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
250 (CHANNEL * GALMPSC_REG_GAP), temp);
251
252 /* Can't poll on abort bit, so we just wait. */
253 udelay (100);
254
255 galsdma_enable_rx ();
256 }
257
258 /* Number of bytes left in this descriptor */
259 len = p[0] & 0xffff;
260
261 if (len) {
262 /* Where to look */
263 idx = 5;
264 if (done > 3)
265 idx = 4;
266 if (done > 7)
267 idx = 7;
268 if (done > 11)
269 idx = 6;
270
271 INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
272 ch = p[idx] & 0xff;
273 done++;
274 }
275
276 if (done < len) {
277 /* this descriptor has more bytes still
278 * shift down the char we just read, and leave the
279 * buffer in place for the next time around
280 */
281 p[idx] = p[idx] >> 8;
282 FLUSH_DCACHE (&p[idx], &p[idx + 1]);
283 }
284
285 if (done == len) {
286 /* nothing left in this descriptor.
287 * go to next one
288 */
289 p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
290 p[0] = 0x00100000;
291 FLUSH_DCACHE (&p[0], &p[1]);
292 /* Next descriptor */
293 rx_desc_index = (rx_desc_index + 1) % RX_DESC;
294 done = 0;
295 }
296 } while (len == 0); /* galileo bug.. len might be zero */
297
298 return ch;
299 }
300
301
302 int mpsc_test_char_debug (void)
303 {
304 if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
305 return 0;
306 else {
307 return 1;
308 }
309 }
310
311
312 int mpsc_test_char_sdma (void)
313 {
314 volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
315
316 INVALIDATE_DCACHE (&p[1], &p[2]);
317
318 if (p[1] & DESC_OWNER_BIT)
319 return 0;
320 else
321 return 1;
322 }
323
324 int mpsc_init (int baud)
325 {
326 /* BRG CONFIG */
327 galbrg_set_baudrate (CHANNEL, baud);
328 galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */
329 galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */
330 galbrg_enable (CHANNEL); /* Enable BRG */
331
332 /* Set up clock routing */
333 galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */
334
335 galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */
336 galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */
337
338 /* reset MPSC state */
339 galmpsc_shutdown (CHANNEL);
340
341 /* SDMA CONFIG */
342 galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */
343 galsdma_set_txle (CHANNEL);
344 galsdma_set_rxle (CHANNEL);
345 galsdma_set_RC (CHANNEL, 0xf);
346 galsdma_set_SFM (CHANNEL);
347 galsdma_set_RFT (CHANNEL);
348
349 /* MPSC CONFIG */
350 galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
351 galmpsc_config_channel_regs (CHANNEL);
352 galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */
353 galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */
354 galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */
355
356 #ifdef CONFIG_MPSC_DEBUG_PORT
357 mpsc_debug_init ();
358 #endif
359
360 /* COMM_MPSC CONFIG */
361 #ifdef SOFTWARE_CACHE_MANAGEMENT
362 galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */
363 #else
364 galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */
365 #endif
366
367 return 0;
368 }
369
370
371 void mpsc_sdma_init (void)
372 {
373 /* Setup SDMA channel0 SDMA_CONFIG_REG*/
374 GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
375
376 /* Enable MPSC-Window0 for DRAM Bank0 */
377 if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT,
378 MV64360_SDMA_DRAM_CS_0_TARGET,
379 0,
380 memoryGetBankBaseAddress
381 (CS_0_LOW_DECODE_ADDRESS),
382 memoryGetBankSize (BANK0)) != true)
383 printf ("%s: SDMA_Window0 memory setup failed !!! \n",
384 __FUNCTION__);
385
386
387 /* Disable MPSC-Window1 */
388 if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT,
389 MV64360_SDMA_DRAM_CS_0_TARGET,
390 0,
391 memoryGetBankBaseAddress
392 (CS_1_LOW_DECODE_ADDRESS),
393 memoryGetBankSize (BANK3)) != true)
394 printf ("%s: SDMA_Window1 memory setup failed !!! \n",
395 __FUNCTION__);
396
397
398 /* Disable MPSC-Window2 */
399 if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT,
400 MV64360_SDMA_DRAM_CS_0_TARGET,
401 0,
402 memoryGetBankBaseAddress
403 (CS_2_LOW_DECODE_ADDRESS),
404 memoryGetBankSize (BANK3)) != true)
405 printf ("%s: SDMA_Window2 memory setup failed !!! \n",
406 __FUNCTION__);
407
408
409 /* Disable MPSC-Window3 */
410 if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT,
411 MV64360_SDMA_DRAM_CS_0_TARGET,
412 0,
413 memoryGetBankBaseAddress
414 (CS_3_LOW_DECODE_ADDRESS),
415 memoryGetBankSize (BANK3)) != true)
416 printf ("%s: SDMA_Window3 memory setup failed !!! \n",
417 __FUNCTION__);
418
419 /* Setup MPSC0 access mode Window0 full access */
420 GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
421 (MV64360_SDMA_WIN_ACCESS_FULL <<
422 (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
423
424 /* Setup MPSC1 access mode Window1 full access */
425 GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
426 (MV64360_SDMA_WIN_ACCESS_FULL <<
427 (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
428
429 /* Setup MPSC internal address space base address */
430 GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
431
432 /* no high address remap*/
433 GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
434 GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
435
436 /* clear interrupt cause register for MPSC (fault register)*/
437 GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
438 }
439
440
441 void mpsc_init2 (void)
442 {
443 int i;
444
445 #ifndef CONFIG_MPSC_DEBUG_PORT
446 mpsc_putchar = mpsc_putchar_sdma;
447 mpsc_getchar = mpsc_getchar_sdma;
448 mpsc_test_char = mpsc_test_char_sdma;
449 #endif
450 /* RX descriptors */
451 rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
452 sizeof (unsigned int));
453
454 /* align descriptors */
455 rx_desc_base = (unsigned int *)
456 (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
457
458 rx_desc_index = 0;
459
460 memset ((void *) rx_desc_base, 0,
461 (RX_DESC * 8) * sizeof (unsigned int));
462
463 for (i = 0; i < RX_DESC; i++) {
464 rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */
465 rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */
466 rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */
467 rx_desc_base[i * 8] = 0x00100000;
468 }
469 rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
470
471 FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
472 GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
473 (unsigned int) &rx_desc_base[0]);
474
475 /* TX descriptors */
476 tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
477 sizeof (unsigned int));
478
479 /* align descriptors */
480 tx_desc_base = (unsigned int *)
481 (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
482
483 tx_desc_index = -1;
484
485 memset ((void *) tx_desc_base, 0,
486 (TX_DESC * 8) * sizeof (unsigned int));
487
488 for (i = 0; i < TX_DESC; i++) {
489 tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
490 tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
491 tx_desc_base[i * 8 + 3] =
492 (unsigned int) &tx_desc_base[i * 8 + 4];
493 tx_desc_base[i * 8 + 2] =
494 (unsigned int) &tx_desc_base[(i + 1) * 8];
495 tx_desc_base[i * 8 + 1] =
496 DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
497
498 /* set sbytecnt and shadow byte cnt to 1 */
499 tx_desc_base[i * 8] = 0x00010001;
500 }
501 tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
502
503 FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
504
505 udelay (100);
506
507 galsdma_enable_rx ();
508
509 return;
510 }
511
512 int galbrg_set_baudrate (int channel, int rate)
513 {
514 DECLARE_GLOBAL_DATA_PTR;
515 int clock;
516
517 galbrg_disable (channel); /*ok */
518
519 #ifdef ZUMA_NTL
520 /* from tclk */
521 clock = (CFG_TCLK / (16 * rate)) - 1;
522 #else
523 clock = (CFG_TCLK / (16 * rate)) - 1;
524 #endif
525
526 galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */
527
528 galbrg_enable (channel);
529
530 gd->baudrate = rate;
531
532 return 0;
533 }
534
535 /* ------------------------------------------------------------------ */
536
537 /* Below are all the private functions that no one else needs */
538
539 static int galbrg_set_CDV (int channel, int value)
540 {
541 unsigned int temp;
542
543 temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
544 temp &= 0xFFFF0000;
545 temp |= (value & 0x0000FFFF);
546 GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
547
548 return 0;
549 }
550
551 static int galbrg_enable (int channel)
552 {
553 unsigned int temp;
554
555 temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
556 temp |= 0x00010000;
557 GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
558
559 return 0;
560 }
561
562 static int galbrg_disable (int channel)
563 {
564 unsigned int temp;
565
566 temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
567 temp &= 0xFFFEFFFF;
568 GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
569
570 return 0;
571 }
572
573 static int galbrg_set_clksrc (int channel, int value)
574 {
575 unsigned int temp;
576
577 temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
578 temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */
579 temp |= (value << 18);
580 GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
581 return 0;
582 }
583
584 static int galbrg_set_CUV (int channel, int value)
585 {
586 /* set CountUpValue */
587 GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
588
589 return 0;
590 }
591
592 #if 0
593 static int galbrg_reset (int channel)
594 {
595 unsigned int temp;
596
597 temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
598 temp |= 0x20000;
599 GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
600
601 return 0;
602 }
603 #endif
604
605 static int galsdma_set_RFT (int channel)
606 {
607 unsigned int temp;
608
609 temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
610 temp |= 0x00000001;
611 GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
612 temp);
613
614 return 0;
615 }
616
617 static int galsdma_set_SFM (int channel)
618 {
619 unsigned int temp;
620
621 temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
622 temp |= 0x00000002;
623 GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
624 temp);
625
626 return 0;
627 }
628
629 static int galsdma_set_rxle (int channel)
630 {
631 unsigned int temp;
632
633 temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
634 temp |= 0x00000040;
635 GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
636 temp);
637
638 return 0;
639 }
640
641 static int galsdma_set_txle (int channel)
642 {
643 unsigned int temp;
644
645 temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
646 temp |= 0x00000080;
647 GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
648 temp);
649
650 return 0;
651 }
652
653 static int galsdma_set_RC (int channel, unsigned int value)
654 {
655 unsigned int temp;
656
657 temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
658 temp &= ~0x0000003c;
659 temp |= (value << 2);
660 GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
661 temp);
662
663 return 0;
664 }
665
666 static int galsdma_set_burstsize (int channel, unsigned int value)
667 {
668 unsigned int temp;
669
670 temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
671 temp &= 0xFFFFCFFF;
672 switch (value) {
673 case 8:
674 GT_REG_WRITE (GALSDMA_0_CONF_REG +
675 (channel * GALSDMA_REG_DIFF),
676 (temp | (0x3 << 12)));
677 break;
678
679 case 4:
680 GT_REG_WRITE (GALSDMA_0_CONF_REG +
681 (channel * GALSDMA_REG_DIFF),
682 (temp | (0x2 << 12)));
683 break;
684
685 case 2:
686 GT_REG_WRITE (GALSDMA_0_CONF_REG +
687 (channel * GALSDMA_REG_DIFF),
688 (temp | (0x1 << 12)));
689 break;
690
691 case 1:
692 GT_REG_WRITE (GALSDMA_0_CONF_REG +
693 (channel * GALSDMA_REG_DIFF),
694 (temp | (0x0 << 12)));
695 break;
696
697 default:
698 return -1;
699 break;
700 }
701
702 return 0;
703 }
704
705 static int galmpsc_connect (int channel, int connect)
706 {
707 unsigned int temp;
708
709 temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
710
711 if ((channel == 0) && connect)
712 temp &= ~0x00000007;
713 else if ((channel == 1) && connect)
714 temp &= ~(0x00000007 << 6);
715 else if ((channel == 0) && !connect)
716 temp |= 0x00000007;
717 else
718 temp |= (0x00000007 << 6);
719
720 /* Just in case... */
721 temp &= 0x3fffffff;
722
723 GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
724
725 return 0;
726 }
727
728 static int galmpsc_route_rx_clock (int channel, int brg)
729 {
730 unsigned int temp;
731
732 temp = GTREGREAD (GALMPSC_RxC_ROUTE);
733
734 if (channel == 0) {
735 temp &= ~0x0000000F;
736 temp |= brg;
737 } else {
738 temp &= ~0x00000F00;
739 temp |= (brg << 8);
740 }
741
742 GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
743
744 return 0;
745 }
746
747 static int galmpsc_route_tx_clock (int channel, int brg)
748 {
749 unsigned int temp;
750
751 temp = GTREGREAD (GALMPSC_TxC_ROUTE);
752
753 if (channel == 0) {
754 temp &= ~0x0000000F;
755 temp |= brg;
756 } else {
757 temp &= ~0x00000F00;
758 temp |= (brg << 8);
759 }
760
761 GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
762
763 return 0;
764 }
765
766 static int galmpsc_write_config_regs (int mpsc, int mode)
767 {
768 if (mode == GALMPSC_UART) {
769 /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
770 GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
771 0x000004c4);
772
773 /* Main config reg High (32x Rx/Tx clock mode, width=8bits */
774 GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
775 0x024003f8);
776 /* 22 2222 1111 */
777 /* 54 3210 9876 */
778 /* 0000 0010 0000 0000 */
779 /* 1 */
780 /* 098 7654 3210 */
781 /* 0000 0011 1111 1000 */
782 } else
783 return -1;
784
785 return 0;
786 }
787
788 static int galmpsc_config_channel_regs (int mpsc)
789 {
790 GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
791 GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
792 GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
793 GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
794 GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
795 GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
796 GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
797 GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
798 GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
799 GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
800
801 galmpsc_set_brkcnt (mpsc, 0x3);
802 galmpsc_set_tcschar (mpsc, 0xab);
803
804 return 0;
805 }
806
807 static int galmpsc_set_brkcnt (int mpsc, int value)
808 {
809 unsigned int temp;
810
811 temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
812 temp &= 0x0000FFFF;
813 temp |= (value << 16);
814 GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
815
816 return 0;
817 }
818
819 static int galmpsc_set_tcschar (int mpsc, int value)
820 {
821 unsigned int temp;
822
823 temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
824 temp &= 0xFFFF0000;
825 temp |= value;
826 GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
827
828 return 0;
829 }
830
831 static int galmpsc_set_char_length (int mpsc, int value)
832 {
833 unsigned int temp;
834
835 temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
836 temp &= 0xFFFFCFFF;
837 temp |= (value << 12);
838 GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
839
840 return 0;
841 }
842
843 static int galmpsc_set_stop_bit_length (int mpsc, int value)
844 {
845 unsigned int temp;
846
847 temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
848 temp &= 0xFFFFBFFF;
849 temp |= (value << 14);
850 GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
851
852 return 0;
853 }
854
855 static int galmpsc_set_parity (int mpsc, int value)
856 {
857 unsigned int temp;
858
859 temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
860 if (value != -1) {
861 temp &= 0xFFF3FFF3;
862 temp |= ((value << 18) | (value << 2));
863 temp |= ((value << 17) | (value << 1));
864 } else {
865 temp &= 0xFFF1FFF1;
866 }
867
868 GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
869
870 return 0;
871 }
872
873 static int galmpsc_enter_hunt (int mpsc)
874 {
875 int temp;
876
877 temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
878 temp |= 0x80000000;
879 GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
880
881 while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
882 MPSC_ENTER_HUNT) {
883 udelay (1);
884 }
885 return 0;
886 }
887
888
889 static int galmpsc_shutdown (int mpsc)
890 {
891 unsigned int temp;
892
893 /* cause RX abort (clears RX) */
894 temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
895 temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
896 temp &= ~MPSC_ENTER_HUNT;
897 GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
898
899 GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
900 GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
901
902 /* shut down the MPSC */
903 GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
904 GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
905 GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
906
907 udelay (100);
908
909 /* shut down the sdma engines. */
910 /* reset config to default */
911 GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
912
913 udelay (100);
914
915 /* clear the SDMA current and first TX and RX pointers */
916 GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
917 GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
918 GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
919
920 udelay (100);
921
922 return 0;
923 }
924
925 static void galsdma_enable_rx (void)
926 {
927 int temp;
928
929 /* Enable RX processing */
930 temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
931 temp |= RX_ENABLE;
932 GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
933
934 galmpsc_enter_hunt (CHANNEL);
935 }
936
937 static int galmpsc_set_snoop (int mpsc, int value)
938 {
939 int reg =
940 mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
941 MPSC_0_ADDRESS_CONTROL_LOW;
942 int temp = GTREGREAD (reg);
943
944 if (value)
945 temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
946 else
947 temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
948 GT_REG_WRITE (reg, temp);
949 return 0;
950 }
951
952 /*******************************************************************************
953 * galsdma_set_mem_space - Set MV64360 IDMA memory decoding map.
954 *
955 * DESCRIPTION:
956 * the MV64360 SDMA has its own address decoding map that is de-coupled
957 * from the CPU interface address decoding windows. The SDMA channels
958 * share four address windows. Each region can be individually configured
959 * by this function by associating it to a target interface and setting
960 * base and size values.
961 *
962 * NOTE!!!
963 * The size must be in 64Kbyte granularity.
964 * The base address must be aligned to the size.
965 * The size must be a series of 1s followed by a series of zeros
966 *
967 * OUTPUT:
968 * None.
969 *
970 * RETURN:
971 * True for success, false otherwise.
972 *
973 *******************************************************************************/
974
975 static int galsdma_set_mem_space (unsigned int memSpace,
976 unsigned int memSpaceTarget,
977 unsigned int memSpaceAttr,
978 unsigned int baseAddress, unsigned int size)
979 {
980 unsigned int temp;
981
982 if (size == 0) {
983 GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
984 1 << memSpace);
985 return true;
986 }
987
988 /* The base address must be aligned to the size. */
989 if (baseAddress % size != 0) {
990 return false;
991 }
992 if (size < 0x10000) {
993 return false;
994 }
995
996 /* Align size and base to 64K */
997 baseAddress &= 0xffff0000;
998 size &= 0xffff0000;
999 temp = size >> 16;
1000
1001 /* Checking that the size is a sequence of '1' followed by a
1002 sequence of '0' starting from LSB to MSB. */
1003 while ((temp > 0) && (temp & 0x1)) {
1004 temp = temp >> 1;
1005 }
1006
1007 if (temp != 0) {
1008 GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
1009 (baseAddress | memSpaceTarget | memSpaceAttr));
1010 GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8),
1011 (size - 1) & 0xffff0000);
1012 GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
1013 1 << memSpace);
1014 } else {
1015 /* An invalid size was specified */
1016 return false;
1017 }
1018 return true;
1019 }
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