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[people/ms/u-boot.git] / board / Marvell / db64360 / mv_eth.c
1 /*
2 * (C) Copyright 2003
3 * Ingo Assmus <ingo.assmus@keymile.com>
4 *
5 * based on - Driver for MV64360X ethernet ports
6 * Copyright (C) 2002 rabeeh@galileo.co.il
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 /*
12 * mv_eth.c - header file for the polled mode GT ethernet driver
13 */
14 #include <common.h>
15 #include <net.h>
16 #include <malloc.h>
17
18 #include "mv_eth.h"
19
20 /* enable Debug outputs */
21
22 #undef DEBUG_MV_ETH
23
24 #ifdef DEBUG_MV_ETH
25 #define DEBUG
26 #define DP(x) x
27 #else
28 #define DP(x)
29 #endif
30
31 #undef MV64360_CHECKSUM_OFFLOAD
32 /*************************************************************************
33 **************************************************************************
34 **************************************************************************
35 * The first part is the high level driver of the gigE ethernet ports. *
36 **************************************************************************
37 **************************************************************************
38 *************************************************************************/
39
40 /* Definition for configuring driver */
41 /* #define UPDATE_STATS_BY_SOFTWARE */
42 #undef MV64360_RX_QUEUE_FILL_ON_TASK
43
44
45 /* Constants */
46 #define MAGIC_ETH_RUNNING 8031971
47 #define MV64360_INTERNAL_SRAM_SIZE _256K
48 #define EXTRA_BYTES 32
49 #define WRAP ETH_HLEN + 2 + 4 + 16
50 #define BUFFER_MTU dev->mtu + WRAP
51 #define INT_CAUSE_UNMASK_ALL 0x0007ffff
52 #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
53 #ifdef MV64360_RX_FILL_ON_TASK
54 #define INT_CAUSE_MASK_ALL 0x00000000
55 #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
56 #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
57 #endif
58
59 /* Read/Write to/from MV64360 internal registers */
60 #define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
61 #define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
62 #define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
63 #define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
64
65 /* Static function declarations */
66 static int mv64360_eth_real_open (struct eth_device *eth);
67 static int mv64360_eth_real_stop (struct eth_device *eth);
68 static struct net_device_stats *mv64360_eth_get_stats (struct eth_device
69 *dev);
70 static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
71 static void mv64360_eth_update_stat (struct eth_device *dev);
72 bool db64360_eth_start (struct eth_device *eth);
73 unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
74 unsigned int mib_offset);
75 int mv64360_eth_receive (struct eth_device *dev);
76
77 int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length);
78
79 #ifndef UPDATE_STATS_BY_SOFTWARE
80 static void mv64360_eth_print_stat (struct eth_device *dev);
81 #endif
82
83 extern unsigned int INTERNAL_REG_BASE_ADDR;
84
85 /*************************************************
86 *Helper functions - used inside the driver only *
87 *************************************************/
88 #ifdef DEBUG_MV_ETH
89 void print_globals (struct eth_device *dev)
90 {
91 printf ("Ethernet PRINT_Globals-Debug function\n");
92 printf ("Base Address for ETH_PORT_INFO: %08x\n",
93 (unsigned int) dev->priv);
94 printf ("Base Address for mv64360_eth_priv: %08x\n",
95 (unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
96 port_private));
97
98 printf ("GT Internal Base Address: %08x\n",
99 INTERNAL_REG_BASE_ADDR);
100 printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE);
101 printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE);
102 printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n",
103 (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
104 p_rx_buffer_base[0],
105 (MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32);
106 printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n",
107 (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
108 p_tx_buffer_base[0],
109 (MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32);
110 }
111 #endif
112
113 #define my_cpu_to_le32(x) my_le32_to_cpu((x))
114
115 unsigned long my_le32_to_cpu (unsigned long x)
116 {
117 return (((x & 0x000000ffU) << 24) |
118 ((x & 0x0000ff00U) << 8) |
119 ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
120 }
121
122
123 /**********************************************************************
124 * mv64360_eth_print_phy_status
125 *
126 * Prints gigabit ethenret phy status
127 *
128 * Input : pointer to ethernet interface network device structure
129 * Output : N/A
130 **********************************************************************/
131
132 static void mv64360_eth_print_phy_status (struct eth_device *dev)
133 {
134 struct mv64360_eth_priv *port_private;
135 unsigned int port_num;
136 ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
137 unsigned int port_status, phy_reg_data;
138
139 port_private =
140 (struct mv64360_eth_priv *) ethernet_private->port_private;
141 port_num = port_private->port_num;
142
143 /* Check Link status on phy */
144 eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
145 if (!(phy_reg_data & 0x20)) {
146 printf ("Ethernet port changed link status to DOWN\n");
147 } else {
148 port_status =
149 MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
150 printf ("Ethernet status port %d: Link up", port_num);
151 printf (", %s",
152 (port_status & BIT2) ? "Full Duplex" : "Half Duplex");
153 if (port_status & BIT4)
154 printf (", Speed 1 Gbps");
155 else
156 printf (", %s",
157 (port_status & BIT5) ? "Speed 100 Mbps" :
158 "Speed 10 Mbps");
159 printf ("\n");
160 }
161 }
162
163 /**********************************************************************
164 * u-boot entry functions for mv64360_eth
165 *
166 **********************************************************************/
167 int db64360_eth_probe (struct eth_device *dev)
168 {
169 return ((int) db64360_eth_start (dev));
170 }
171
172 int db64360_eth_poll (struct eth_device *dev)
173 {
174 return mv64360_eth_receive (dev);
175 }
176
177 int db64360_eth_transmit(struct eth_device *dev, void *packet, int length)
178 {
179 mv64360_eth_xmit (dev, packet, length);
180 return 0;
181 }
182
183 void db64360_eth_disable (struct eth_device *dev)
184 {
185 mv64360_eth_stop (dev);
186 }
187
188
189 void mv6436x_eth_initialize (bd_t * bis)
190 {
191 struct eth_device *dev;
192 ETH_PORT_INFO *ethernet_private;
193 struct mv64360_eth_priv *port_private;
194 int devnum, x, temp;
195 char *s, *e, buf[64];
196
197 for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
198 dev = calloc (sizeof (*dev), 1);
199 if (!dev) {
200 printf ("%s: mv_enet%d allocation failure, %s\n",
201 __FUNCTION__, devnum, "eth_device structure");
202 return;
203 }
204
205 /* must be less than sizeof(dev->name) */
206 sprintf (dev->name, "mv_enet%d", devnum);
207
208 #ifdef DEBUG
209 printf ("Initializing %s\n", dev->name);
210 #endif
211
212 /* Extract the MAC address from the environment */
213 switch (devnum) {
214 case 0:
215 s = "ethaddr";
216 break;
217
218 case 1:
219 s = "eth1addr";
220 break;
221
222 case 2:
223 s = "eth2addr";
224 break;
225
226 default: /* this should never happen */
227 printf ("%s: Invalid device number %d\n",
228 __FUNCTION__, devnum);
229 return;
230 }
231
232 temp = getenv_f(s, buf, sizeof (buf));
233 s = (temp > 0) ? buf : NULL;
234
235 #ifdef DEBUG
236 printf ("Setting MAC %d to %s\n", devnum, s);
237 #endif
238 for (x = 0; x < 6; ++x) {
239 dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
240 if (s)
241 s = (*e) ? e + 1 : e;
242 }
243 /* ronen - set the MAC addr in the HW */
244 eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
245
246 dev->init = (void *) db64360_eth_probe;
247 dev->halt = (void *) ethernet_phy_reset;
248 dev->send = (void *) db64360_eth_transmit;
249 dev->recv = (void *) db64360_eth_poll;
250
251 ethernet_private = calloc (sizeof (*ethernet_private), 1);
252 dev->priv = (void *) ethernet_private;
253
254 if (!ethernet_private) {
255 printf ("%s: %s allocation failure, %s\n",
256 __FUNCTION__, dev->name,
257 "Private Device Structure");
258 free (dev);
259 return;
260 }
261 /* start with an zeroed ETH_PORT_INFO */
262 memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
263 memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
264
265 /* set pointer to memory for stats data structure etc... */
266 port_private = calloc (sizeof (*ethernet_private), 1);
267 ethernet_private->port_private = (void *)port_private;
268 if (!port_private) {
269 printf ("%s: %s allocation failure, %s\n",
270 __FUNCTION__, dev->name,
271 "Port Private Device Structure");
272
273 free (ethernet_private);
274 free (dev);
275 return;
276 }
277
278 port_private->stats =
279 calloc (sizeof (struct net_device_stats), 1);
280 if (!port_private->stats) {
281 printf ("%s: %s allocation failure, %s\n",
282 __FUNCTION__, dev->name,
283 "Net stat Structure");
284
285 free (port_private);
286 free (ethernet_private);
287 free (dev);
288 return;
289 }
290 memset (ethernet_private->port_private, 0,
291 sizeof (struct mv64360_eth_priv));
292 switch (devnum) {
293 case 0:
294 ethernet_private->port_num = ETH_0;
295 break;
296 case 1:
297 ethernet_private->port_num = ETH_1;
298 break;
299 case 2:
300 ethernet_private->port_num = ETH_2;
301 break;
302 default:
303 printf ("Invalid device number %d\n", devnum);
304 break;
305 };
306
307 port_private->port_num = devnum;
308 /*
309 * Read MIB counter on the GT in order to reset them,
310 * then zero all the stats fields in memory
311 */
312 mv64360_eth_update_stat (dev);
313 memset (port_private->stats, 0,
314 sizeof (struct net_device_stats));
315 /* Extract the MAC address from the environment */
316 switch (devnum) {
317 case 0:
318 s = "ethaddr";
319 break;
320
321 case 1:
322 s = "eth1addr";
323 break;
324
325 case 2:
326 s = "eth2addr";
327 break;
328
329 default: /* this should never happen */
330 printf ("%s: Invalid device number %d\n",
331 __FUNCTION__, devnum);
332 return;
333 }
334
335 temp = getenv_f(s, buf, sizeof (buf));
336 s = (temp > 0) ? buf : NULL;
337
338 #ifdef DEBUG
339 printf ("Setting MAC %d to %s\n", devnum, s);
340 #endif
341 for (x = 0; x < 6; ++x) {
342 dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
343 if (s)
344 s = (*e) ? e + 1 : e;
345 }
346
347 DP (printf ("Allocating descriptor and buffer rings\n"));
348
349 ethernet_private->p_rx_desc_area_base[0] =
350 (ETH_RX_DESC *) memalign (16,
351 RX_DESC_ALIGNED_SIZE *
352 MV64360_RX_QUEUE_SIZE + 1);
353 ethernet_private->p_tx_desc_area_base[0] =
354 (ETH_TX_DESC *) memalign (16,
355 TX_DESC_ALIGNED_SIZE *
356 MV64360_TX_QUEUE_SIZE + 1);
357
358 ethernet_private->p_rx_buffer_base[0] =
359 (char *) memalign (16,
360 MV64360_RX_QUEUE_SIZE *
361 MV64360_TX_BUFFER_SIZE + 1);
362 ethernet_private->p_tx_buffer_base[0] =
363 (char *) memalign (16,
364 MV64360_RX_QUEUE_SIZE *
365 MV64360_TX_BUFFER_SIZE + 1);
366
367 #ifdef DEBUG_MV_ETH
368 /* DEBUG OUTPUT prints adresses of globals */
369 print_globals (dev);
370 #endif
371 eth_register (dev);
372
373 }
374 DP (printf ("%s: exit\n", __FUNCTION__));
375
376 }
377
378 /**********************************************************************
379 * mv64360_eth_open
380 *
381 * This function is called when openning the network device. The function
382 * should initialize all the hardware, initialize cyclic Rx/Tx
383 * descriptors chain and buffers and allocate an IRQ to the network
384 * device.
385 *
386 * Input : a pointer to the network device structure
387 * / / ronen - changed the output to match net/eth.c needs
388 * Output : nonzero of success , zero if fails.
389 * under construction
390 **********************************************************************/
391
392 int mv64360_eth_open (struct eth_device *dev)
393 {
394 return (mv64360_eth_real_open (dev));
395 }
396
397 /* Helper function for mv64360_eth_open */
398 static int mv64360_eth_real_open (struct eth_device *dev)
399 {
400
401 unsigned int queue;
402 ETH_PORT_INFO *ethernet_private;
403 struct mv64360_eth_priv *port_private;
404 unsigned int port_num;
405 u32 phy_reg_data;
406
407 ethernet_private = (ETH_PORT_INFO *) dev->priv;
408 /* ronen - when we update the MAC env params we only update dev->enetaddr
409 see ./net/eth.c eth_set_enetaddr() */
410 memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
411
412 port_private =
413 (struct mv64360_eth_priv *) ethernet_private->port_private;
414 port_num = port_private->port_num;
415
416 /* Stop RX Queues */
417 MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
418 0x0000ff00);
419
420 /* Clear the ethernet port interrupts */
421 MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
422 MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
423
424 /* Unmask RX buffer and TX end interrupt */
425 MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num),
426 INT_CAUSE_UNMASK_ALL);
427
428 /* Unmask phy and link status changes interrupts */
429 MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
430 INT_CAUSE_UNMASK_ALL_EXT);
431
432 /* Set phy address of the port */
433 ethernet_private->port_phy_addr = 0x8 + port_num;
434
435 /* Activate the DMA channels etc */
436 eth_port_init (ethernet_private);
437
438
439 /* "Allocate" setup TX rings */
440
441 for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
442 unsigned int size;
443
444 port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE;
445 size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */
446 ethernet_private->tx_desc_area_size[queue] = size;
447
448 /* first clear desc area completely */
449 memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
450 0, ethernet_private->tx_desc_area_size[queue]);
451
452 /* initialize tx desc ring with low level driver */
453 if (ether_init_tx_desc_ring
454 (ethernet_private, ETH_Q0,
455 port_private->tx_ring_size[queue],
456 MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
457 (unsigned int) ethernet_private->
458 p_tx_desc_area_base[queue],
459 (unsigned int) ethernet_private->
460 p_tx_buffer_base[queue]) == false)
461 printf ("### Error initializing TX Ring\n");
462 }
463
464 /* "Allocate" setup RX rings */
465 for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
466 unsigned int size;
467
468 /* Meantime RX Ring are fixed - but must be configurable by user */
469 port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE;
470 size = (port_private->rx_ring_size[queue] *
471 RX_DESC_ALIGNED_SIZE);
472 ethernet_private->rx_desc_area_size[queue] = size;
473
474 /* first clear desc area completely */
475 memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
476 0, ethernet_private->rx_desc_area_size[queue]);
477 if ((ether_init_rx_desc_ring
478 (ethernet_private, ETH_Q0,
479 port_private->rx_ring_size[queue],
480 MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
481 (unsigned int) ethernet_private->
482 p_rx_desc_area_base[queue],
483 (unsigned int) ethernet_private->
484 p_rx_buffer_base[queue])) == false)
485 printf ("### Error initializing RX Ring\n");
486 }
487
488 eth_port_start (ethernet_private);
489
490 /* Set maximum receive buffer to 9700 bytes */
491 MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num),
492 (0x5 << 17) |
493 (MV_REG_READ
494 (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num))
495 & 0xfff1ffff));
496
497 /*
498 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
499 * disable the leaky bucket mechanism .
500 */
501
502 MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
503 MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
504
505 /* Check Link status on phy */
506 eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
507 if (!(phy_reg_data & 0x20)) {
508 /* Reset PHY */
509 if ((ethernet_phy_reset (port_num)) != true) {
510 printf ("$$ Warnning: No link on port %d \n",
511 port_num);
512 return 0;
513 } else {
514 eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
515 if (!(phy_reg_data & 0x20)) {
516 printf ("### Error: Phy is not active\n");
517 return 0;
518 }
519 }
520 } else {
521 mv64360_eth_print_phy_status (dev);
522 }
523 port_private->eth_running = MAGIC_ETH_RUNNING;
524 return 1;
525 }
526
527
528 static int mv64360_eth_free_tx_rings (struct eth_device *dev)
529 {
530 unsigned int queue;
531 ETH_PORT_INFO *ethernet_private;
532 struct mv64360_eth_priv *port_private;
533 unsigned int port_num;
534 volatile ETH_TX_DESC *p_tx_curr_desc;
535
536 ethernet_private = (ETH_PORT_INFO *) dev->priv;
537 port_private =
538 (struct mv64360_eth_priv *) ethernet_private->port_private;
539 port_num = port_private->port_num;
540
541 /* Stop Tx Queues */
542 MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
543 0x0000ff00);
544
545 /* Free TX rings */
546 DP (printf ("Clearing previously allocated TX queues... "));
547 for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
548 /* Free on TX rings */
549 for (p_tx_curr_desc =
550 ethernet_private->p_tx_desc_area_base[queue];
551 ((unsigned int) p_tx_curr_desc <= (unsigned int)
552 ethernet_private->p_tx_desc_area_base[queue] +
553 ethernet_private->tx_desc_area_size[queue]);
554 p_tx_curr_desc =
555 (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
556 TX_DESC_ALIGNED_SIZE)) {
557 /* this is inside for loop */
558 if (p_tx_curr_desc->return_info != 0) {
559 p_tx_curr_desc->return_info = 0;
560 DP (printf ("freed\n"));
561 }
562 }
563 DP (printf ("Done\n"));
564 }
565 return 0;
566 }
567
568 static int mv64360_eth_free_rx_rings (struct eth_device *dev)
569 {
570 unsigned int queue;
571 ETH_PORT_INFO *ethernet_private;
572 struct mv64360_eth_priv *port_private;
573 unsigned int port_num;
574 volatile ETH_RX_DESC *p_rx_curr_desc;
575
576 ethernet_private = (ETH_PORT_INFO *) dev->priv;
577 port_private =
578 (struct mv64360_eth_priv *) ethernet_private->port_private;
579 port_num = port_private->port_num;
580
581
582 /* Stop RX Queues */
583 MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
584 0x0000ff00);
585
586 /* Free RX rings */
587 DP (printf ("Clearing previously allocated RX queues... "));
588 for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
589 /* Free preallocated skb's on RX rings */
590 for (p_rx_curr_desc =
591 ethernet_private->p_rx_desc_area_base[queue];
592 (((unsigned int) p_rx_curr_desc <
593 ((unsigned int) ethernet_private->
594 p_rx_desc_area_base[queue] +
595 ethernet_private->rx_desc_area_size[queue])));
596 p_rx_curr_desc =
597 (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
598 RX_DESC_ALIGNED_SIZE)) {
599 if (p_rx_curr_desc->return_info != 0) {
600 p_rx_curr_desc->return_info = 0;
601 DP (printf ("freed\n"));
602 }
603 }
604 DP (printf ("Done\n"));
605 }
606 return 0;
607 }
608
609 /**********************************************************************
610 * mv64360_eth_stop
611 *
612 * This function is used when closing the network device.
613 * It updates the hardware,
614 * release all memory that holds buffers and descriptors and release the IRQ.
615 * Input : a pointer to the device structure
616 * Output : zero if success , nonzero if fails
617 *********************************************************************/
618
619 int mv64360_eth_stop (struct eth_device *dev)
620 {
621 /* Disable all gigE address decoder */
622 MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
623 DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
624 mv64360_eth_real_stop (dev);
625
626 return 0;
627 };
628
629 /* Helper function for mv64360_eth_stop */
630
631 static int mv64360_eth_real_stop (struct eth_device *dev)
632 {
633 ETH_PORT_INFO *ethernet_private;
634 struct mv64360_eth_priv *port_private;
635 unsigned int port_num;
636
637 ethernet_private = (ETH_PORT_INFO *) dev->priv;
638 port_private =
639 (struct mv64360_eth_priv *) ethernet_private->port_private;
640 port_num = port_private->port_num;
641
642
643 mv64360_eth_free_tx_rings (dev);
644 mv64360_eth_free_rx_rings (dev);
645
646 eth_port_reset (ethernet_private->port_num);
647 /* Disable ethernet port interrupts */
648 MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
649 MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
650 /* Mask RX buffer and TX end interrupt */
651 MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0);
652 /* Mask phy and link status changes interrupts */
653 MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
654 MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH,
655 BIT0 << port_num);
656 /* Print Network statistics */
657 #ifndef UPDATE_STATS_BY_SOFTWARE
658 /*
659 * Print statistics (only if ethernet is running),
660 * then zero all the stats fields in memory
661 */
662 if (port_private->eth_running == MAGIC_ETH_RUNNING) {
663 port_private->eth_running = 0;
664 mv64360_eth_print_stat (dev);
665 }
666 memset (port_private->stats, 0, sizeof (struct net_device_stats));
667 #endif
668 DP (printf ("\nEthernet stopped ... \n"));
669 return 0;
670 }
671
672
673 /**********************************************************************
674 * mv64360_eth_start_xmit
675 *
676 * This function is queues a packet in the Tx descriptor for
677 * required port.
678 *
679 * Input : skb - a pointer to socket buffer
680 * dev - a pointer to the required port
681 *
682 * Output : zero upon success
683 **********************************************************************/
684
685 int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
686 int dataSize)
687 {
688 ETH_PORT_INFO *ethernet_private;
689 struct mv64360_eth_priv *port_private;
690 PKT_INFO pkt_info;
691 ETH_FUNC_RET_STATUS status;
692 struct net_device_stats *stats;
693 ETH_FUNC_RET_STATUS release_result;
694
695 ethernet_private = (ETH_PORT_INFO *) dev->priv;
696 port_private =
697 (struct mv64360_eth_priv *) ethernet_private->port_private;
698
699 stats = port_private->stats;
700
701 /* Update packet info data structure */
702 pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */
703 pkt_info.byte_cnt = dataSize;
704 pkt_info.buf_ptr = (unsigned int) dataPtr;
705 pkt_info.return_info = 0;
706
707 status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
708 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
709 printf ("Error on transmitting packet ..");
710 if (status == ETH_QUEUE_FULL)
711 printf ("ETH Queue is full. \n");
712 if (status == ETH_QUEUE_LAST_RESOURCE)
713 printf ("ETH Queue: using last available resource. \n");
714 goto error;
715 }
716
717 /* Update statistics and start of transmittion time */
718 stats->tx_bytes += dataSize;
719 stats->tx_packets++;
720
721 /* Check if packet(s) is(are) transmitted correctly (release everything) */
722 do {
723 release_result =
724 eth_tx_return_desc (ethernet_private, ETH_Q0,
725 &pkt_info);
726 switch (release_result) {
727 case ETH_OK:
728 DP (printf ("descriptor released\n"));
729 if (pkt_info.cmd_sts & BIT0) {
730 printf ("Error in TX\n");
731 stats->tx_errors++;
732
733 }
734 break;
735 case ETH_RETRY:
736 DP (printf ("transmission still in process\n"));
737 break;
738
739 case ETH_ERROR:
740 printf ("routine can not access Tx desc ring\n");
741 break;
742
743 case ETH_END_OF_JOB:
744 DP (printf ("the routine has nothing to release\n"));
745 break;
746 default: /* should not happen */
747 break;
748 }
749 } while (release_result == ETH_OK);
750
751
752 return 0; /* success */
753 error:
754 return 1; /* Failed - higher layers will free the skb */
755 }
756
757 /**********************************************************************
758 * mv64360_eth_receive
759 *
760 * This function is forward packets that are received from the port's
761 * queues toward kernel core or FastRoute them to another interface.
762 *
763 * Input : dev - a pointer to the required interface
764 * max - maximum number to receive (0 means unlimted)
765 *
766 * Output : number of served packets
767 **********************************************************************/
768
769 int mv64360_eth_receive (struct eth_device *dev)
770 {
771 ETH_PORT_INFO *ethernet_private;
772 struct mv64360_eth_priv *port_private;
773 PKT_INFO pkt_info;
774 struct net_device_stats *stats;
775
776 ethernet_private = (ETH_PORT_INFO *) dev->priv;
777 port_private =
778 (struct mv64360_eth_priv *) ethernet_private->port_private;
779 stats = port_private->stats;
780
781 while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
782 ETH_OK)) {
783
784 #ifdef DEBUG_MV_ETH
785 if (pkt_info.byte_cnt != 0) {
786 printf ("%s: Received %d byte Packet @ 0x%x\n",
787 __FUNCTION__, pkt_info.byte_cnt,
788 pkt_info.buf_ptr);
789 }
790 #endif
791 /* Update statistics. Note byte count includes 4 byte CRC count */
792 stats->rx_packets++;
793 stats->rx_bytes += pkt_info.byte_cnt;
794
795 /*
796 * In case received a packet without first / last bits on OR the error
797 * summary bit is on, the packets needs to be dropeed.
798 */
799 if (((pkt_info.
800 cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
801 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
802 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
803 stats->rx_dropped++;
804
805 printf ("Received packet spread on multiple descriptors\n");
806
807 /* Is this caused by an error ? */
808 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
809 stats->rx_errors++;
810 }
811
812 /* free these descriptors again without forwarding them to the higher layers */
813 pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
814 pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
815
816 if (eth_rx_return_buff
817 (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
818 printf ("Error while returning the RX Desc to Ring\n");
819 } else {
820 DP (printf ("RX Desc returned to Ring\n"));
821 }
822 /* /free these descriptors again */
823 } else {
824
825 /* !!! call higher layer processing */
826 #ifdef DEBUG_MV_ETH
827 printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
828 #endif
829 /* let the upper layer handle the packet */
830 NetReceive ((uchar *) pkt_info.buf_ptr,
831 (int) pkt_info.byte_cnt);
832
833 /* **************************************************************** */
834 /* free descriptor */
835 pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
836 pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
837 DP (printf
838 ("RX: pkt_info.buf_ptr = %x\n",
839 pkt_info.buf_ptr));
840 if (eth_rx_return_buff
841 (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
842 printf ("Error while returning the RX Desc to Ring\n");
843 } else {
844 DP (printf ("RX Desc returned to Ring\n"));
845 }
846
847 /* **************************************************************** */
848
849 }
850 }
851 mv64360_eth_get_stats (dev); /* update statistics */
852 return 1;
853 }
854
855 /**********************************************************************
856 * mv64360_eth_get_stats
857 *
858 * Returns a pointer to the interface statistics.
859 *
860 * Input : dev - a pointer to the required interface
861 *
862 * Output : a pointer to the interface's statistics
863 **********************************************************************/
864
865 static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev)
866 {
867 ETH_PORT_INFO *ethernet_private;
868 struct mv64360_eth_priv *port_private;
869
870 ethernet_private = (ETH_PORT_INFO *) dev->priv;
871 port_private =
872 (struct mv64360_eth_priv *) ethernet_private->port_private;
873
874 mv64360_eth_update_stat (dev);
875
876 return port_private->stats;
877 }
878
879
880 /**********************************************************************
881 * mv64360_eth_update_stat
882 *
883 * Update the statistics structure in the private data structure
884 *
885 * Input : pointer to ethernet interface network device structure
886 * Output : N/A
887 **********************************************************************/
888
889 static void mv64360_eth_update_stat (struct eth_device *dev)
890 {
891 ETH_PORT_INFO *ethernet_private;
892 struct mv64360_eth_priv *port_private;
893 struct net_device_stats *stats;
894
895 ethernet_private = (ETH_PORT_INFO *) dev->priv;
896 port_private =
897 (struct mv64360_eth_priv *) ethernet_private->port_private;
898 stats = port_private->stats;
899
900 /* These are false updates */
901 stats->rx_packets += (unsigned long)
902 eth_read_mib_counter (ethernet_private->port_num,
903 ETH_MIB_GOOD_FRAMES_RECEIVED);
904 stats->tx_packets += (unsigned long)
905 eth_read_mib_counter (ethernet_private->port_num,
906 ETH_MIB_GOOD_FRAMES_SENT);
907 stats->rx_bytes += (unsigned long)
908 eth_read_mib_counter (ethernet_private->port_num,
909 ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
910 /*
911 * Ideally this should be as follows -
912 *
913 * stats->rx_bytes += stats->rx_bytes +
914 * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
915 * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
916 *
917 * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
918 * is just a dummy read for proper work of the GigE port
919 */
920 eth_read_mib_counter (ethernet_private->port_num,
921 ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
922 stats->tx_bytes += (unsigned long)
923 eth_read_mib_counter (ethernet_private->port_num,
924 ETH_MIB_GOOD_OCTETS_SENT_LOW);
925 eth_read_mib_counter (ethernet_private->port_num,
926 ETH_MIB_GOOD_OCTETS_SENT_HIGH);
927 stats->rx_errors += (unsigned long)
928 eth_read_mib_counter (ethernet_private->port_num,
929 ETH_MIB_MAC_RECEIVE_ERROR);
930
931 /* Rx dropped is for received packet with CRC error */
932 stats->rx_dropped +=
933 (unsigned long) eth_read_mib_counter (ethernet_private->
934 port_num,
935 ETH_MIB_BAD_CRC_EVENT);
936 stats->multicast += (unsigned long)
937 eth_read_mib_counter (ethernet_private->port_num,
938 ETH_MIB_MULTICAST_FRAMES_RECEIVED);
939 stats->collisions +=
940 (unsigned long) eth_read_mib_counter (ethernet_private->
941 port_num,
942 ETH_MIB_COLLISION) +
943 (unsigned long) eth_read_mib_counter (ethernet_private->
944 port_num,
945 ETH_MIB_LATE_COLLISION);
946 /* detailed rx errors */
947 stats->rx_length_errors +=
948 (unsigned long) eth_read_mib_counter (ethernet_private->
949 port_num,
950 ETH_MIB_UNDERSIZE_RECEIVED)
951 +
952 (unsigned long) eth_read_mib_counter (ethernet_private->
953 port_num,
954 ETH_MIB_OVERSIZE_RECEIVED);
955 /* detailed tx errors */
956 }
957
958 #ifndef UPDATE_STATS_BY_SOFTWARE
959 /**********************************************************************
960 * mv64360_eth_print_stat
961 *
962 * Update the statistics structure in the private data structure
963 *
964 * Input : pointer to ethernet interface network device structure
965 * Output : N/A
966 **********************************************************************/
967
968 static void mv64360_eth_print_stat (struct eth_device *dev)
969 {
970 ETH_PORT_INFO *ethernet_private;
971 struct mv64360_eth_priv *port_private;
972 struct net_device_stats *stats;
973
974 ethernet_private = (ETH_PORT_INFO *) dev->priv;
975 port_private =
976 (struct mv64360_eth_priv *) ethernet_private->port_private;
977 stats = port_private->stats;
978
979 /* These are false updates */
980 printf ("\n### Network statistics: ###\n");
981 printf ("--------------------------\n");
982 printf (" Packets received: %ld\n", stats->rx_packets);
983 printf (" Packets send: %ld\n", stats->tx_packets);
984 printf (" Received bytes: %ld\n", stats->rx_bytes);
985 printf (" Send bytes: %ld\n", stats->tx_bytes);
986 if (stats->rx_errors != 0)
987 printf (" Rx Errors: %ld\n",
988 stats->rx_errors);
989 if (stats->rx_dropped != 0)
990 printf (" Rx dropped (CRC Errors): %ld\n",
991 stats->rx_dropped);
992 if (stats->multicast != 0)
993 printf (" Rx mulicast frames: %ld\n",
994 stats->multicast);
995 if (stats->collisions != 0)
996 printf (" No. of collisions: %ld\n",
997 stats->collisions);
998 if (stats->rx_length_errors != 0)
999 printf (" Rx length errors: %ld\n",
1000 stats->rx_length_errors);
1001 }
1002 #endif
1003
1004 /**************************************************************************
1005 *network_start - Network Kick Off Routine UBoot
1006 *Inputs :
1007 *Outputs :
1008 **************************************************************************/
1009
1010 bool db64360_eth_start (struct eth_device *dev)
1011 {
1012 return (mv64360_eth_open (dev)); /* calls real open */
1013 }
1014
1015 /*************************************************************************
1016 **************************************************************************
1017 **************************************************************************
1018 * The second part is the low level driver of the gigE ethernet ports. *
1019 **************************************************************************
1020 **************************************************************************
1021 *************************************************************************/
1022 /*
1023 * based on Linux code
1024 * arch/powerpc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports
1025 * Copyright (C) 2002 rabeeh@galileo.co.il
1026 * SPDX-License-Identifier: GPL-2.0+
1027 */
1028
1029 /********************************************************************************
1030 * Marvell's Gigabit Ethernet controller low level driver
1031 *
1032 * DESCRIPTION:
1033 * This file introduce low level API to Marvell's Gigabit Ethernet
1034 * controller. This Gigabit Ethernet Controller driver API controls
1035 * 1) Operations (i.e. port init, start, reset etc').
1036 * 2) Data flow (i.e. port send, receive etc').
1037 * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
1038 * struct.
1039 * This struct includes user configuration information as well as
1040 * driver internal data needed for its operations.
1041 *
1042 * Supported Features:
1043 * - This low level driver is OS independent. Allocating memory for
1044 * the descriptor rings and buffers are not within the scope of
1045 * this driver.
1046 * - The user is free from Rx/Tx queue managing.
1047 * - This low level driver introduce functionality API that enable
1048 * the to operate Marvell's Gigabit Ethernet Controller in a
1049 * convenient way.
1050 * - Simple Gigabit Ethernet port operation API.
1051 * - Simple Gigabit Ethernet port data flow API.
1052 * - Data flow and operation API support per queue functionality.
1053 * - Support cached descriptors for better performance.
1054 * - Enable access to all four DRAM banks and internal SRAM memory
1055 * spaces.
1056 * - PHY access and control API.
1057 * - Port control register configuration API.
1058 * - Full control over Unicast and Multicast MAC configurations.
1059 *
1060 * Operation flow:
1061 *
1062 * Initialization phase
1063 * This phase complete the initialization of the ETH_PORT_INFO
1064 * struct.
1065 * User information regarding port configuration has to be set
1066 * prior to calling the port initialization routine. For example,
1067 * the user has to assign the port_phy_addr field which is board
1068 * depended parameter.
1069 * In this phase any port Tx/Rx activity is halted, MIB counters
1070 * are cleared, PHY address is set according to user parameter and
1071 * access to DRAM and internal SRAM memory spaces.
1072 *
1073 * Driver ring initialization
1074 * Allocating memory for the descriptor rings and buffers is not
1075 * within the scope of this driver. Thus, the user is required to
1076 * allocate memory for the descriptors ring and buffers. Those
1077 * memory parameters are used by the Rx and Tx ring initialization
1078 * routines in order to curve the descriptor linked list in a form
1079 * of a ring.
1080 * Note: Pay special attention to alignment issues when using
1081 * cached descriptors/buffers. In this phase the driver store
1082 * information in the ETH_PORT_INFO struct regarding each queue
1083 * ring.
1084 *
1085 * Driver start
1086 * This phase prepares the Ethernet port for Rx and Tx activity.
1087 * It uses the information stored in the ETH_PORT_INFO struct to
1088 * initialize the various port registers.
1089 *
1090 * Data flow:
1091 * All packet references to/from the driver are done using PKT_INFO
1092 * struct.
1093 * This struct is a unified struct used with Rx and Tx operations.
1094 * This way the user is not required to be familiar with neither
1095 * Tx nor Rx descriptors structures.
1096 * The driver's descriptors rings are management by indexes.
1097 * Those indexes controls the ring resources and used to indicate
1098 * a SW resource error:
1099 * 'current'
1100 * This index points to the current available resource for use. For
1101 * example in Rx process this index will point to the descriptor
1102 * that will be passed to the user upon calling the receive routine.
1103 * In Tx process, this index will point to the descriptor
1104 * that will be assigned with the user packet info and transmitted.
1105 * 'used'
1106 * This index points to the descriptor that need to restore its
1107 * resources. For example in Rx process, using the Rx buffer return
1108 * API will attach the buffer returned in packet info to the
1109 * descriptor pointed by 'used'. In Tx process, using the Tx
1110 * descriptor return will merely return the user packet info with
1111 * the command status of the transmitted buffer pointed by the
1112 * 'used' index. Nevertheless, it is essential to use this routine
1113 * to update the 'used' index.
1114 * 'first'
1115 * This index supports Tx Scatter-Gather. It points to the first
1116 * descriptor of a packet assembled of multiple buffers. For example
1117 * when in middle of Such packet we have a Tx resource error the
1118 * 'curr' index get the value of 'first' to indicate that the ring
1119 * returned to its state before trying to transmit this packet.
1120 *
1121 * Receive operation:
1122 * The eth_port_receive API set the packet information struct,
1123 * passed by the caller, with received information from the
1124 * 'current' SDMA descriptor.
1125 * It is the user responsibility to return this resource back
1126 * to the Rx descriptor ring to enable the reuse of this source.
1127 * Return Rx resource is done using the eth_rx_return_buff API.
1128 *
1129 * Transmit operation:
1130 * The eth_port_send API supports Scatter-Gather which enables to
1131 * send a packet spanned over multiple buffers. This means that
1132 * for each packet info structure given by the user and put into
1133 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1134 * bit will be set in the packet info command status field. This
1135 * API also consider restriction regarding buffer alignments and
1136 * sizes.
1137 * The user must return a Tx resource after ensuring the buffer
1138 * has been transmitted to enable the Tx ring indexes to update.
1139 *
1140 * BOARD LAYOUT
1141 * This device is on-board. No jumper diagram is necessary.
1142 *
1143 * EXTERNAL INTERFACE
1144 *
1145 * Prior to calling the initialization routine eth_port_init() the user
1146 * must set the following fields under ETH_PORT_INFO struct:
1147 * port_num User Ethernet port number.
1148 * port_phy_addr User PHY address of Ethernet port.
1149 * port_mac_addr[6] User defined port MAC address.
1150 * port_config User port configuration value.
1151 * port_config_extend User port config extend value.
1152 * port_sdma_config User port SDMA config value.
1153 * port_serial_control User port serial control value.
1154 * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr.
1155 * *port_private User scratch pad for user specific data structures.
1156 *
1157 * This driver introduce a set of default values:
1158 * PORT_CONFIG_VALUE Default port configuration value
1159 * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value
1160 * PORT_SDMA_CONFIG_VALUE Default sdma control value
1161 * PORT_SERIAL_CONTROL_VALUE Default port serial control value
1162 *
1163 * This driver data flow is done using the PKT_INFO struct which is
1164 * a unified struct for Rx and Tx operations:
1165 * byte_cnt Tx/Rx descriptor buffer byte count.
1166 * l4i_chk CPU provided TCP Checksum. For Tx operation only.
1167 * cmd_sts Tx/Rx descriptor command status.
1168 * buf_ptr Tx/Rx descriptor buffer pointer.
1169 * return_info Tx/Rx user resource return information.
1170 *
1171 *
1172 * EXTERNAL SUPPORT REQUIREMENTS
1173 *
1174 * This driver requires the following external support:
1175 *
1176 * D_CACHE_FLUSH_LINE (address, address offset)
1177 *
1178 * This macro applies assembly code to flush and invalidate cache
1179 * line.
1180 * address - address base.
1181 * address offset - address offset
1182 *
1183 *
1184 * CPU_PIPE_FLUSH
1185 *
1186 * This macro applies assembly code to flush the CPU pipeline.
1187 *
1188 *******************************************************************************/
1189 /* includes */
1190
1191 /* defines */
1192 /* SDMA command macros */
1193 #define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
1194 MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
1195
1196 #define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
1197 MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
1198 (1 << (8 + tx_queue)))
1199
1200 #define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
1201 MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
1202
1203 #define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
1204 MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
1205
1206 #define CURR_RFD_GET(p_curr_desc, queue) \
1207 ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
1208
1209 #define CURR_RFD_SET(p_curr_desc, queue) \
1210 (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
1211
1212 #define USED_RFD_GET(p_used_desc, queue) \
1213 ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
1214
1215 #define USED_RFD_SET(p_used_desc, queue)\
1216 (p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
1217
1218
1219 #define CURR_TFD_GET(p_curr_desc, queue) \
1220 ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
1221
1222 #define CURR_TFD_SET(p_curr_desc, queue) \
1223 (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
1224
1225 #define USED_TFD_GET(p_used_desc, queue) \
1226 ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
1227
1228 #define USED_TFD_SET(p_used_desc, queue) \
1229 (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
1230
1231 #define FIRST_TFD_GET(p_first_desc, queue) \
1232 ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
1233
1234 #define FIRST_TFD_SET(p_first_desc, queue) \
1235 (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
1236
1237
1238 /* Macros that save access to desc in order to find next desc pointer */
1239 #define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
1240
1241 #define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
1242
1243 #define LINK_UP_TIMEOUT 100000
1244 #define PHY_BUSY_TIMEOUT 10000000
1245
1246 /* locals */
1247
1248 /* PHY routines */
1249 static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
1250 static int ethernet_phy_get (ETH_PORT eth_port_num);
1251
1252 /* Ethernet Port routines */
1253 static void eth_set_access_control (ETH_PORT eth_port_num,
1254 ETH_WIN_PARAM * param);
1255 static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
1256 ETH_QUEUE queue, int option);
1257 #if 0 /* FIXME */
1258 static bool eth_port_smc_addr (ETH_PORT eth_port_num,
1259 unsigned char mc_byte,
1260 ETH_QUEUE queue, int option);
1261 static bool eth_port_omc_addr (ETH_PORT eth_port_num,
1262 unsigned char crc8,
1263 ETH_QUEUE queue, int option);
1264 #endif
1265
1266 static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
1267 int byte_count);
1268
1269 void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
1270
1271
1272 typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
1273 u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
1274 {
1275 u32 result = 0;
1276 u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
1277
1278 if (enable & (1 << bank))
1279 return 0;
1280 if (bank == BANK0)
1281 result = MV_REG_READ (MV64360_CS_0_BASE_ADDR);
1282 if (bank == BANK1)
1283 result = MV_REG_READ (MV64360_CS_1_BASE_ADDR);
1284 if (bank == BANK2)
1285 result = MV_REG_READ (MV64360_CS_2_BASE_ADDR);
1286 if (bank == BANK3)
1287 result = MV_REG_READ (MV64360_CS_3_BASE_ADDR);
1288 result &= 0x0000ffff;
1289 result = result << 16;
1290 return result;
1291 }
1292
1293 u32 mv_get_dram_bank_size (MEMORY_BANK bank)
1294 {
1295 u32 result = 0;
1296 u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
1297
1298 if (enable & (1 << bank))
1299 return 0;
1300 if (bank == BANK0)
1301 result = MV_REG_READ (MV64360_CS_0_SIZE);
1302 if (bank == BANK1)
1303 result = MV_REG_READ (MV64360_CS_1_SIZE);
1304 if (bank == BANK2)
1305 result = MV_REG_READ (MV64360_CS_2_SIZE);
1306 if (bank == BANK3)
1307 result = MV_REG_READ (MV64360_CS_3_SIZE);
1308 result += 1;
1309 result &= 0x0000ffff;
1310 result = result << 16;
1311 return result;
1312 }
1313
1314 u32 mv_get_internal_sram_base (void)
1315 {
1316 u32 result;
1317
1318 result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR);
1319 result &= 0x0000ffff;
1320 result = result << 16;
1321 return result;
1322 }
1323
1324 /*******************************************************************************
1325 * eth_port_init - Initialize the Ethernet port driver
1326 *
1327 * DESCRIPTION:
1328 * This function prepares the ethernet port to start its activity:
1329 * 1) Completes the ethernet port driver struct initialization toward port
1330 * start routine.
1331 * 2) Resets the device to a quiescent state in case of warm reboot.
1332 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1333 * 4) Clean MAC tables. The reset status of those tables is unknown.
1334 * 5) Set PHY address.
1335 * Note: Call this routine prior to eth_port_start routine and after setting
1336 * user values in the user fields of Ethernet port control struct (i.e.
1337 * port_phy_addr).
1338 *
1339 * INPUT:
1340 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
1341 *
1342 * OUTPUT:
1343 * See description.
1344 *
1345 * RETURN:
1346 * None.
1347 *
1348 *******************************************************************************/
1349 static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
1350 {
1351 int queue;
1352 ETH_WIN_PARAM win_param;
1353
1354 p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
1355 p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
1356 p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
1357 p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
1358
1359 p_eth_port_ctrl->port_rx_queue_command = 0;
1360 p_eth_port_ctrl->port_tx_queue_command = 0;
1361
1362 /* Zero out SW structs */
1363 for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
1364 CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
1365 USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
1366 p_eth_port_ctrl->rx_resource_err[queue] = false;
1367 }
1368
1369 for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
1370 CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1371 USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1372 FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1373 p_eth_port_ctrl->tx_resource_err[queue] = false;
1374 }
1375
1376 eth_port_reset (p_eth_port_ctrl->port_num);
1377
1378 /* Set access parameters for DRAM bank 0 */
1379 win_param.win = ETH_WIN0; /* Use Ethernet window 0 */
1380 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1381 win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */
1382 #ifndef CONFIG_NOT_COHERENT_CACHE
1383 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1384 #endif
1385 win_param.high_addr = 0;
1386 /* Get bank base */
1387 win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
1388 win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */
1389 if (win_param.size == 0)
1390 win_param.enable = 0;
1391 else
1392 win_param.enable = 1; /* Enable the access */
1393 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1394
1395 /* Set the access control for address window (EPAPR) READ & WRITE */
1396 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1397
1398 /* Set access parameters for DRAM bank 1 */
1399 win_param.win = ETH_WIN1; /* Use Ethernet window 1 */
1400 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1401 win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */
1402 #ifndef CONFIG_NOT_COHERENT_CACHE
1403 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1404 #endif
1405 win_param.high_addr = 0;
1406 /* Get bank base */
1407 win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
1408 win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */
1409 if (win_param.size == 0)
1410 win_param.enable = 0;
1411 else
1412 win_param.enable = 1; /* Enable the access */
1413 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1414
1415 /* Set the access control for address window (EPAPR) READ & WRITE */
1416 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1417
1418 /* Set access parameters for DRAM bank 2 */
1419 win_param.win = ETH_WIN2; /* Use Ethernet window 2 */
1420 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1421 win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */
1422 #ifndef CONFIG_NOT_COHERENT_CACHE
1423 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1424 #endif
1425 win_param.high_addr = 0;
1426 /* Get bank base */
1427 win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
1428 win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */
1429 if (win_param.size == 0)
1430 win_param.enable = 0;
1431 else
1432 win_param.enable = 1; /* Enable the access */
1433 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1434
1435 /* Set the access control for address window (EPAPR) READ & WRITE */
1436 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1437
1438 /* Set access parameters for DRAM bank 3 */
1439 win_param.win = ETH_WIN3; /* Use Ethernet window 3 */
1440 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1441 win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */
1442 #ifndef CONFIG_NOT_COHERENT_CACHE
1443 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1444 #endif
1445 win_param.high_addr = 0;
1446 /* Get bank base */
1447 win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
1448 win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */
1449 if (win_param.size == 0)
1450 win_param.enable = 0;
1451 else
1452 win_param.enable = 1; /* Enable the access */
1453 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1454
1455 /* Set the access control for address window (EPAPR) READ & WRITE */
1456 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1457
1458 /* Set access parameters for Internal SRAM */
1459 win_param.win = ETH_WIN4; /* Use Ethernet window 0 */
1460 win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */
1461 win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
1462 win_param.high_addr = 0;
1463 win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */
1464 win_param.size = MV64360_INTERNAL_SRAM_SIZE; /* Get bank size */
1465 win_param.enable = 1; /* Enable the access */
1466 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1467
1468 /* Set the access control for address window (EPAPR) READ & WRITE */
1469 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1470
1471 eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
1472
1473 ethernet_phy_set (p_eth_port_ctrl->port_num,
1474 p_eth_port_ctrl->port_phy_addr);
1475
1476 return;
1477
1478 }
1479
1480 /*******************************************************************************
1481 * eth_port_start - Start the Ethernet port activity.
1482 *
1483 * DESCRIPTION:
1484 * This routine prepares the Ethernet port for Rx and Tx activity:
1485 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1486 * has been initialized a descriptor's ring (using ether_init_tx_desc_ring
1487 * for Tx and ether_init_rx_desc_ring for Rx)
1488 * 2. Initialize and enable the Ethernet configuration port by writing to
1489 * the port's configuration and command registers.
1490 * 3. Initialize and enable the SDMA by writing to the SDMA's
1491 * configuration and command registers.
1492 * After completing these steps, the ethernet port SDMA can starts to
1493 * perform Rx and Tx activities.
1494 *
1495 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1496 * to calling this function (use ether_init_tx_desc_ring for Tx queues and
1497 * ether_init_rx_desc_ring for Rx queues).
1498 *
1499 * INPUT:
1500 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
1501 *
1502 * OUTPUT:
1503 * Ethernet port is ready to receive and transmit.
1504 *
1505 * RETURN:
1506 * false if the port PHY is not up.
1507 * true otherwise.
1508 *
1509 *******************************************************************************/
1510 static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
1511 {
1512 int queue;
1513 volatile ETH_TX_DESC *p_tx_curr_desc;
1514 volatile ETH_RX_DESC *p_rx_curr_desc;
1515 unsigned int phy_reg_data;
1516 ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
1517
1518
1519 /* Assignment of Tx CTRP of given queue */
1520 for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
1521 CURR_TFD_GET (p_tx_curr_desc, queue);
1522 MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
1523 (eth_port_num)
1524 + (4 * queue)),
1525 ((unsigned int) p_tx_curr_desc));
1526
1527 }
1528
1529 /* Assignment of Rx CRDP of given queue */
1530 for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
1531 CURR_RFD_GET (p_rx_curr_desc, queue);
1532 MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
1533 (eth_port_num)
1534 + (4 * queue)),
1535 ((unsigned int) p_rx_curr_desc));
1536
1537 if (p_rx_curr_desc != NULL)
1538 /* Add the assigned Ethernet address to the port's address table */
1539 eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
1540 p_eth_port_ctrl->port_mac_addr,
1541 queue);
1542 }
1543
1544 /* Assign port configuration and command. */
1545 MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
1546 p_eth_port_ctrl->port_config);
1547
1548 MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
1549 p_eth_port_ctrl->port_config_extend);
1550
1551 MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
1552 p_eth_port_ctrl->port_serial_control);
1553
1554 MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
1555 ETH_SERIAL_PORT_ENABLE);
1556
1557 /* Assign port SDMA configuration */
1558 MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
1559 p_eth_port_ctrl->port_sdma_config);
1560
1561 MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
1562 (eth_port_num), 0x3fffffff);
1563 MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
1564 (eth_port_num), 0x03fffcff);
1565 /* Turn off the port/queue bandwidth limitation */
1566 MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
1567
1568 /* Enable port Rx. */
1569 MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
1570 p_eth_port_ctrl->port_rx_queue_command);
1571
1572 /* Check if link is up */
1573 eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
1574
1575 if (!(phy_reg_data & 0x20))
1576 return false;
1577
1578 return true;
1579 }
1580
1581 /*******************************************************************************
1582 * eth_port_uc_addr_set - This function Set the port Unicast address.
1583 *
1584 * DESCRIPTION:
1585 * This function Set the port Ethernet MAC address.
1586 *
1587 * INPUT:
1588 * ETH_PORT eth_port_num Port number.
1589 * char * p_addr Address to be set
1590 * ETH_QUEUE queue Rx queue number for this MAC address.
1591 *
1592 * OUTPUT:
1593 * Set MAC address low and high registers. also calls eth_port_uc_addr()
1594 * To set the unicast table with the proper information.
1595 *
1596 * RETURN:
1597 * N/A.
1598 *
1599 *******************************************************************************/
1600 static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
1601 unsigned char *p_addr, ETH_QUEUE queue)
1602 {
1603 unsigned int mac_h;
1604 unsigned int mac_l;
1605
1606 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1607 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
1608 (p_addr[2] << 8) | (p_addr[3] << 0);
1609
1610 MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
1611 MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
1612
1613 /* Accept frames of this address */
1614 eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
1615
1616 return;
1617 }
1618
1619 /*******************************************************************************
1620 * eth_port_uc_addr - This function Set the port unicast address table
1621 *
1622 * DESCRIPTION:
1623 * This function locates the proper entry in the Unicast table for the
1624 * specified MAC nibble and sets its properties according to function
1625 * parameters.
1626 *
1627 * INPUT:
1628 * ETH_PORT eth_port_num Port number.
1629 * unsigned char uc_nibble Unicast MAC Address last nibble.
1630 * ETH_QUEUE queue Rx queue number for this MAC address.
1631 * int option 0 = Add, 1 = remove address.
1632 *
1633 * OUTPUT:
1634 * This function add/removes MAC addresses from the port unicast address
1635 * table.
1636 *
1637 * RETURN:
1638 * true is output succeeded.
1639 * false if option parameter is invalid.
1640 *
1641 *******************************************************************************/
1642 static bool eth_port_uc_addr (ETH_PORT eth_port_num,
1643 unsigned char uc_nibble,
1644 ETH_QUEUE queue, int option)
1645 {
1646 unsigned int unicast_reg;
1647 unsigned int tbl_offset;
1648 unsigned int reg_offset;
1649
1650 /* Locate the Unicast table entry */
1651 uc_nibble = (0xf & uc_nibble);
1652 tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
1653 reg_offset = uc_nibble % 4; /* Entry offset within the above register */
1654
1655 switch (option) {
1656 case REJECT_MAC_ADDR:
1657 /* Clear accepts frame bit at specified unicast DA table entry */
1658 unicast_reg =
1659 MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
1660 (eth_port_num)
1661 + tbl_offset));
1662
1663 unicast_reg &= (0x0E << (8 * reg_offset));
1664
1665 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
1666 (eth_port_num)
1667 + tbl_offset), unicast_reg);
1668 break;
1669
1670 case ACCEPT_MAC_ADDR:
1671 /* Set accepts frame bit at unicast DA filter table entry */
1672 unicast_reg =
1673 MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
1674 (eth_port_num)
1675 + tbl_offset));
1676
1677 unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
1678
1679 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
1680 (eth_port_num)
1681 + tbl_offset), unicast_reg);
1682
1683 break;
1684
1685 default:
1686 return false;
1687 }
1688 return true;
1689 }
1690
1691 #if 0 /* FIXME */
1692 /*******************************************************************************
1693 * eth_port_mc_addr - Multicast address settings.
1694 *
1695 * DESCRIPTION:
1696 * This API controls the MV device MAC multicast support.
1697 * The MV device supports multicast using two tables:
1698 * 1) Special Multicast Table for MAC addresses of the form
1699 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
1700 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1701 * Table entries in the DA-Filter table.
1702 * In this case, the function calls eth_port_smc_addr() routine to set the
1703 * Special Multicast Table.
1704 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
1705 * is used as an index to the Other Multicast Table entries in the
1706 * DA-Filter table.
1707 * In this case, the function calculates the CRC-8bit value and calls
1708 * eth_port_omc_addr() routine to set the Other Multicast Table.
1709 * INPUT:
1710 * ETH_PORT eth_port_num Port number.
1711 * unsigned char *p_addr Unicast MAC Address.
1712 * ETH_QUEUE queue Rx queue number for this MAC address.
1713 * int option 0 = Add, 1 = remove address.
1714 *
1715 * OUTPUT:
1716 * See description.
1717 *
1718 * RETURN:
1719 * true is output succeeded.
1720 * false if add_address_table_entry( ) failed.
1721 *
1722 *******************************************************************************/
1723 static void eth_port_mc_addr (ETH_PORT eth_port_num,
1724 unsigned char *p_addr,
1725 ETH_QUEUE queue, int option)
1726 {
1727 unsigned int mac_h;
1728 unsigned int mac_l;
1729 unsigned char crc_result = 0;
1730 int mac_array[48];
1731 int crc[8];
1732 int i;
1733
1734
1735 if ((p_addr[0] == 0x01) &&
1736 (p_addr[1] == 0x00) &&
1737 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
1738
1739 eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
1740 else {
1741 /* Calculate CRC-8 out of the given address */
1742 mac_h = (p_addr[0] << 8) | (p_addr[1]);
1743 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
1744 (p_addr[4] << 8) | (p_addr[5] << 0);
1745
1746 for (i = 0; i < 32; i++)
1747 mac_array[i] = (mac_l >> i) & 0x1;
1748 for (i = 32; i < 48; i++)
1749 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1750
1751
1752 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
1753 mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
1754 mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
1755 mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
1756 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
1757 mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
1758 mac_array[6] ^ mac_array[0];
1759
1760 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
1761 mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
1762 mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
1763 mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
1764 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
1765 mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
1766 mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
1767 mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
1768 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
1769 mac_array[0];
1770
1771 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
1772 mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
1773 mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
1774 mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
1775 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
1776 mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
1777 mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
1778 mac_array[2] ^ mac_array[1] ^ mac_array[0];
1779
1780 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
1781 mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
1782 mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
1783 mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
1784 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
1785 mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
1786 mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
1787 mac_array[2] ^ mac_array[1];
1788
1789 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
1790 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
1791 mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
1792 mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
1793 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
1794 mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
1795 mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
1796 mac_array[2];
1797
1798 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
1799 mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
1800 mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
1801 mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
1802 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
1803 mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
1804 mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
1805 mac_array[3];
1806
1807 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
1808 mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
1809 mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
1810 mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
1811 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
1812 mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
1813 mac_array[6] ^ mac_array[5] ^ mac_array[4];
1814
1815 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
1816 mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
1817 mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
1818 mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
1819 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
1820 mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
1821 mac_array[6] ^ mac_array[5];
1822
1823 for (i = 0; i < 8; i++)
1824 crc_result = crc_result | (crc[i] << i);
1825
1826 eth_port_omc_addr (eth_port_num, crc_result, queue, option);
1827 }
1828 return;
1829 }
1830
1831 /*******************************************************************************
1832 * eth_port_smc_addr - Special Multicast address settings.
1833 *
1834 * DESCRIPTION:
1835 * This routine controls the MV device special MAC multicast support.
1836 * The Special Multicast Table for MAC addresses supports MAC of the form
1837 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
1838 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1839 * Table entries in the DA-Filter table.
1840 * This function set the Special Multicast Table appropriate entry
1841 * according to the argument given.
1842 *
1843 * INPUT:
1844 * ETH_PORT eth_port_num Port number.
1845 * unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits).
1846 * ETH_QUEUE queue Rx queue number for this MAC address.
1847 * int option 0 = Add, 1 = remove address.
1848 *
1849 * OUTPUT:
1850 * See description.
1851 *
1852 * RETURN:
1853 * true is output succeeded.
1854 * false if option parameter is invalid.
1855 *
1856 *******************************************************************************/
1857 static bool eth_port_smc_addr (ETH_PORT eth_port_num,
1858 unsigned char mc_byte,
1859 ETH_QUEUE queue, int option)
1860 {
1861 unsigned int smc_table_reg;
1862 unsigned int tbl_offset;
1863 unsigned int reg_offset;
1864
1865 /* Locate the SMC table entry */
1866 tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */
1867 reg_offset = mc_byte % 4; /* Entry offset within the above register */
1868 queue &= 0x7;
1869
1870 switch (option) {
1871 case REJECT_MAC_ADDR:
1872 /* Clear accepts frame bit at specified Special DA table entry */
1873 smc_table_reg =
1874 MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1875 smc_table_reg &= (0x0E << (8 * reg_offset));
1876
1877 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
1878 break;
1879
1880 case ACCEPT_MAC_ADDR:
1881 /* Set accepts frame bit at specified Special DA table entry */
1882 smc_table_reg =
1883 MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1884 smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
1885
1886 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
1887 break;
1888
1889 default:
1890 return false;
1891 }
1892 return true;
1893 }
1894
1895 /*******************************************************************************
1896 * eth_port_omc_addr - Multicast address settings.
1897 *
1898 * DESCRIPTION:
1899 * This routine controls the MV device Other MAC multicast support.
1900 * The Other Multicast Table is used for multicast of another type.
1901 * A CRC-8bit is used as an index to the Other Multicast Table entries
1902 * in the DA-Filter table.
1903 * The function gets the CRC-8bit value from the calling routine and
1904 * set the Other Multicast Table appropriate entry according to the
1905 * CRC-8 argument given.
1906 *
1907 * INPUT:
1908 * ETH_PORT eth_port_num Port number.
1909 * unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
1910 * ETH_QUEUE queue Rx queue number for this MAC address.
1911 * int option 0 = Add, 1 = remove address.
1912 *
1913 * OUTPUT:
1914 * See description.
1915 *
1916 * RETURN:
1917 * true is output succeeded.
1918 * false if option parameter is invalid.
1919 *
1920 *******************************************************************************/
1921 static bool eth_port_omc_addr (ETH_PORT eth_port_num,
1922 unsigned char crc8,
1923 ETH_QUEUE queue, int option)
1924 {
1925 unsigned int omc_table_reg;
1926 unsigned int tbl_offset;
1927 unsigned int reg_offset;
1928
1929 /* Locate the OMC table entry */
1930 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
1931 reg_offset = crc8 % 4; /* Entry offset within the above register */
1932 queue &= 0x7;
1933
1934 switch (option) {
1935 case REJECT_MAC_ADDR:
1936 /* Clear accepts frame bit at specified Other DA table entry */
1937 omc_table_reg =
1938 MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1939 omc_table_reg &= (0x0E << (8 * reg_offset));
1940
1941 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
1942 break;
1943
1944 case ACCEPT_MAC_ADDR:
1945 /* Set accepts frame bit at specified Other DA table entry */
1946 omc_table_reg =
1947 MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1948 omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
1949
1950 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
1951 break;
1952
1953 default:
1954 return false;
1955 }
1956 return true;
1957 }
1958 #endif
1959
1960 /*******************************************************************************
1961 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
1962 *
1963 * DESCRIPTION:
1964 * Go through all the DA filter tables (Unicast, Special Multicast & Other
1965 * Multicast) and set each entry to 0.
1966 *
1967 * INPUT:
1968 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
1969 *
1970 * OUTPUT:
1971 * Multicast and Unicast packets are rejected.
1972 *
1973 * RETURN:
1974 * None.
1975 *
1976 *******************************************************************************/
1977 static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
1978 {
1979 int table_index;
1980
1981 /* Clear DA filter unicast table (Ex_dFUT) */
1982 for (table_index = 0; table_index <= 0xC; table_index += 4)
1983 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
1984 (eth_port_num) + table_index), 0);
1985
1986 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1987 /* Clear DA filter special multicast table (Ex_dFSMT) */
1988 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
1989 /* Clear DA filter other multicast table (Ex_dFOMT) */
1990 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
1991 }
1992 }
1993
1994 /*******************************************************************************
1995 * eth_clear_mib_counters - Clear all MIB counters
1996 *
1997 * DESCRIPTION:
1998 * This function clears all MIB counters of a specific ethernet port.
1999 * A read from the MIB counter will reset the counter.
2000 *
2001 * INPUT:
2002 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2003 *
2004 * OUTPUT:
2005 * After reading all MIB counters, the counters resets.
2006 *
2007 * RETURN:
2008 * MIB counter value.
2009 *
2010 *******************************************************************************/
2011 static void eth_clear_mib_counters (ETH_PORT eth_port_num)
2012 {
2013 int i;
2014
2015 /* Perform dummy reads from MIB counters */
2016 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2017 i += 4)
2018 MV_REG_READ((MV64360_ETH_MIB_COUNTERS_BASE(eth_port_num) + i));
2019
2020 return;
2021 }
2022
2023 /*******************************************************************************
2024 * eth_read_mib_counter - Read a MIB counter
2025 *
2026 * DESCRIPTION:
2027 * This function reads a MIB counter of a specific ethernet port.
2028 * NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
2029 * following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
2030 * register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
2031 * ETH_MIB_GOOD_OCTETS_SENT_HIGH
2032 *
2033 * INPUT:
2034 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2035 * unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros).
2036 *
2037 * OUTPUT:
2038 * After reading the MIB counter, the counter resets.
2039 *
2040 * RETURN:
2041 * MIB counter value.
2042 *
2043 *******************************************************************************/
2044 unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
2045 unsigned int mib_offset)
2046 {
2047 return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num)
2048 + mib_offset));
2049 }
2050
2051 /*******************************************************************************
2052 * ethernet_phy_set - Set the ethernet port PHY address.
2053 *
2054 * DESCRIPTION:
2055 * This routine set the ethernet port PHY address according to given
2056 * parameter.
2057 *
2058 * INPUT:
2059 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2060 *
2061 * OUTPUT:
2062 * Set PHY Address Register with given PHY address parameter.
2063 *
2064 * RETURN:
2065 * None.
2066 *
2067 *******************************************************************************/
2068 static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
2069 {
2070 unsigned int reg_data;
2071
2072 reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
2073
2074 reg_data &= ~(0x1F << (5 * eth_port_num));
2075 reg_data |= (phy_addr << (5 * eth_port_num));
2076
2077 MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data);
2078
2079 return;
2080 }
2081
2082 /*******************************************************************************
2083 * ethernet_phy_get - Get the ethernet port PHY address.
2084 *
2085 * DESCRIPTION:
2086 * This routine returns the given ethernet port PHY address.
2087 *
2088 * INPUT:
2089 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2090 *
2091 * OUTPUT:
2092 * None.
2093 *
2094 * RETURN:
2095 * PHY address.
2096 *
2097 *******************************************************************************/
2098 static int ethernet_phy_get (ETH_PORT eth_port_num)
2099 {
2100 unsigned int reg_data;
2101
2102 reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
2103
2104 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2105 }
2106
2107 /*******************************************************************************
2108 * ethernet_phy_reset - Reset Ethernet port PHY.
2109 *
2110 * DESCRIPTION:
2111 * This routine utilize the SMI interface to reset the ethernet port PHY.
2112 * The routine waits until the link is up again or link up is timeout.
2113 *
2114 * INPUT:
2115 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2116 *
2117 * OUTPUT:
2118 * The ethernet port PHY renew its link.
2119 *
2120 * RETURN:
2121 * None.
2122 *
2123 *******************************************************************************/
2124 static bool ethernet_phy_reset (ETH_PORT eth_port_num)
2125 {
2126 unsigned int time_out = 50;
2127 unsigned int phy_reg_data;
2128
2129 /* Reset the PHY */
2130 eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
2131 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2132 eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
2133
2134 /* Poll on the PHY LINK */
2135 do {
2136 eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
2137
2138 if (time_out-- == 0)
2139 return false;
2140 }
2141 while (!(phy_reg_data & 0x20));
2142
2143 return true;
2144 }
2145
2146 /*******************************************************************************
2147 * eth_port_reset - Reset Ethernet port
2148 *
2149 * DESCRIPTION:
2150 * This routine resets the chip by aborting any SDMA engine activity and
2151 * clearing the MIB counters. The Receiver and the Transmit unit are in
2152 * idle state after this command is performed and the port is disabled.
2153 *
2154 * INPUT:
2155 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2156 *
2157 * OUTPUT:
2158 * Channel activity is halted.
2159 *
2160 * RETURN:
2161 * None.
2162 *
2163 *******************************************************************************/
2164 static void eth_port_reset (ETH_PORT eth_port_num)
2165 {
2166 unsigned int reg_data;
2167
2168 /* Stop Tx port activity. Check port Tx activity. */
2169 reg_data =
2170 MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
2171 (eth_port_num));
2172
2173 if (reg_data & 0xFF) {
2174 /* Issue stop command for active channels only */
2175 MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
2176 (eth_port_num), (reg_data << 8));
2177
2178 /* Wait for all Tx activity to terminate. */
2179 do {
2180 /* Check port cause register that all Tx queues are stopped */
2181 reg_data =
2182 MV_REG_READ
2183 (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
2184 (eth_port_num));
2185 }
2186 while (reg_data & 0xFF);
2187 }
2188
2189 /* Stop Rx port activity. Check port Rx activity. */
2190 reg_data =
2191 MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
2192 (eth_port_num));
2193
2194 if (reg_data & 0xFF) {
2195 /* Issue stop command for active channels only */
2196 MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
2197 (eth_port_num), (reg_data << 8));
2198
2199 /* Wait for all Rx activity to terminate. */
2200 do {
2201 /* Check port cause register that all Rx queues are stopped */
2202 reg_data =
2203 MV_REG_READ
2204 (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
2205 (eth_port_num));
2206 }
2207 while (reg_data & 0xFF);
2208 }
2209
2210
2211 /* Clear all MIB counters */
2212 eth_clear_mib_counters (eth_port_num);
2213
2214 /* Reset the Enable bit in the Configuration Register */
2215 reg_data =
2216 MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG
2217 (eth_port_num));
2218 reg_data &= ~ETH_SERIAL_PORT_ENABLE;
2219 MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
2220 reg_data);
2221
2222 return;
2223 }
2224
2225 #if 0 /* Not needed here */
2226 /*******************************************************************************
2227 * ethernet_set_config_reg - Set specified bits in configuration register.
2228 *
2229 * DESCRIPTION:
2230 * This function sets specified bits in the given ethernet
2231 * configuration register.
2232 *
2233 * INPUT:
2234 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2235 * unsigned int value 32 bit value.
2236 *
2237 * OUTPUT:
2238 * The set bits in the value parameter are set in the configuration
2239 * register.
2240 *
2241 * RETURN:
2242 * None.
2243 *
2244 *******************************************************************************/
2245 static void ethernet_set_config_reg (ETH_PORT eth_port_num,
2246 unsigned int value)
2247 {
2248 unsigned int eth_config_reg;
2249
2250 eth_config_reg =
2251 MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num));
2252 eth_config_reg |= value;
2253 MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
2254 eth_config_reg);
2255
2256 return;
2257 }
2258 #endif
2259
2260 #if 0 /* FIXME */
2261 /*******************************************************************************
2262 * ethernet_reset_config_reg - Reset specified bits in configuration register.
2263 *
2264 * DESCRIPTION:
2265 * This function resets specified bits in the given Ethernet
2266 * configuration register.
2267 *
2268 * INPUT:
2269 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2270 * unsigned int value 32 bit value.
2271 *
2272 * OUTPUT:
2273 * The set bits in the value parameter are reset in the configuration
2274 * register.
2275 *
2276 * RETURN:
2277 * None.
2278 *
2279 *******************************************************************************/
2280 static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
2281 unsigned int value)
2282 {
2283 unsigned int eth_config_reg;
2284
2285 eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
2286 (eth_port_num));
2287 eth_config_reg &= ~value;
2288 MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
2289 eth_config_reg);
2290
2291 return;
2292 }
2293 #endif
2294
2295 #if 0 /* Not needed here */
2296 /*******************************************************************************
2297 * ethernet_get_config_reg - Get the port configuration register
2298 *
2299 * DESCRIPTION:
2300 * This function returns the configuration register value of the given
2301 * ethernet port.
2302 *
2303 * INPUT:
2304 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2305 *
2306 * OUTPUT:
2307 * None.
2308 *
2309 * RETURN:
2310 * Port configuration register value.
2311 *
2312 *******************************************************************************/
2313 static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
2314 {
2315 unsigned int eth_config_reg;
2316
2317 eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
2318 (eth_port_num));
2319 return eth_config_reg;
2320 }
2321
2322 #endif
2323
2324 /*******************************************************************************
2325 * eth_port_read_smi_reg - Read PHY registers
2326 *
2327 * DESCRIPTION:
2328 * This routine utilize the SMI interface to interact with the PHY in
2329 * order to perform PHY register read.
2330 *
2331 * INPUT:
2332 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2333 * unsigned int phy_reg PHY register address offset.
2334 * unsigned int *value Register value buffer.
2335 *
2336 * OUTPUT:
2337 * Write the value of a specified PHY register into given buffer.
2338 *
2339 * RETURN:
2340 * false if the PHY is busy or read data is not in valid state.
2341 * true otherwise.
2342 *
2343 *******************************************************************************/
2344 static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
2345 unsigned int phy_reg, unsigned int *value)
2346 {
2347 unsigned int reg_value;
2348 unsigned int time_out = PHY_BUSY_TIMEOUT;
2349 int phy_addr;
2350
2351 phy_addr = ethernet_phy_get (eth_port_num);
2352 /* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/
2353
2354 /* first check that it is not busy */
2355 do {
2356 reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
2357 if (time_out-- == 0) {
2358 return false;
2359 }
2360 }
2361 while (reg_value & ETH_SMI_BUSY);
2362
2363 /* not busy */
2364
2365 MV_REG_WRITE (MV64360_ETH_SMI_REG,
2366 (phy_addr << 16) | (phy_reg << 21) |
2367 ETH_SMI_OPCODE_READ);
2368
2369 time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */
2370
2371 do {
2372 reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
2373 if (time_out-- == 0) {
2374 return false;
2375 }
2376 }
2377 while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
2378
2379 /* Wait for the data to update in the SMI register */
2380 #define PHY_UPDATE_TIMEOUT 10000
2381 for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
2382
2383 reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
2384
2385 *value = reg_value & 0xffff;
2386
2387 return true;
2388 }
2389
2390 /*******************************************************************************
2391 * eth_port_write_smi_reg - Write to PHY registers
2392 *
2393 * DESCRIPTION:
2394 * This routine utilize the SMI interface to interact with the PHY in
2395 * order to perform writes to PHY registers.
2396 *
2397 * INPUT:
2398 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2399 * unsigned int phy_reg PHY register address offset.
2400 * unsigned int value Register value.
2401 *
2402 * OUTPUT:
2403 * Write the given value to the specified PHY register.
2404 *
2405 * RETURN:
2406 * false if the PHY is busy.
2407 * true otherwise.
2408 *
2409 *******************************************************************************/
2410 static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
2411 unsigned int phy_reg, unsigned int value)
2412 {
2413 unsigned int reg_value;
2414 unsigned int time_out = PHY_BUSY_TIMEOUT;
2415 int phy_addr;
2416
2417 phy_addr = ethernet_phy_get (eth_port_num);
2418
2419 /* first check that it is not busy */
2420 do {
2421 reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
2422 if (time_out-- == 0) {
2423 return false;
2424 }
2425 }
2426 while (reg_value & ETH_SMI_BUSY);
2427
2428 /* not busy */
2429 MV_REG_WRITE (MV64360_ETH_SMI_REG,
2430 (phy_addr << 16) | (phy_reg << 21) |
2431 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2432 return true;
2433 }
2434
2435 /*******************************************************************************
2436 * eth_set_access_control - Config address decode parameters for Ethernet unit
2437 *
2438 * DESCRIPTION:
2439 * This function configures the address decode parameters for the Gigabit
2440 * Ethernet Controller according the given parameters struct.
2441 *
2442 * INPUT:
2443 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2444 * ETH_WIN_PARAM *param Address decode parameter struct.
2445 *
2446 * OUTPUT:
2447 * An access window is opened using the given access parameters.
2448 *
2449 * RETURN:
2450 * None.
2451 *
2452 *******************************************************************************/
2453 static void eth_set_access_control (ETH_PORT eth_port_num,
2454 ETH_WIN_PARAM * param)
2455 {
2456 unsigned int access_prot_reg;
2457
2458 /* Set access control register */
2459 access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG
2460 (eth_port_num));
2461 access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */
2462 access_prot_reg |= (param->access_ctrl << (param->win * 2));
2463 MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num),
2464 access_prot_reg);
2465
2466 /* Set window Size reg (SR) */
2467 MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 +
2468 (ETH_SIZE_REG_GAP * param->win)),
2469 (((param->size / 0x10000) - 1) << 16));
2470
2471 /* Set window Base address reg (BA) */
2472 MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
2473 (param->target | param->attributes | param->base_addr));
2474 /* High address remap reg (HARR) */
2475 if (param->win < 4)
2476 MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 +
2477 (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
2478 param->high_addr);
2479
2480 /* Base address enable reg (BARER) */
2481 if (param->enable == 1)
2482 MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
2483 (1 << param->win));
2484 else
2485 MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
2486 (1 << param->win));
2487 }
2488
2489 /*******************************************************************************
2490 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
2491 *
2492 * DESCRIPTION:
2493 * This function prepares a Rx chained list of descriptors and packet
2494 * buffers in a form of a ring. The routine must be called after port
2495 * initialization routine and before port start routine.
2496 * The Ethernet SDMA engine uses CPU bus addresses to access the various
2497 * devices in the system (i.e. DRAM). This function uses the ethernet
2498 * struct 'virtual to physical' routine (set by the user) to set the ring
2499 * with physical addresses.
2500 *
2501 * INPUT:
2502 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2503 * ETH_QUEUE rx_queue Number of Rx queue.
2504 * int rx_desc_num Number of Rx descriptors
2505 * int rx_buff_size Size of Rx buffer
2506 * unsigned int rx_desc_base_addr Rx descriptors memory area base addr.
2507 * unsigned int rx_buff_base_addr Rx buffer memory area base addr.
2508 *
2509 * OUTPUT:
2510 * The routine updates the Ethernet port control struct with information
2511 * regarding the Rx descriptors and buffers.
2512 *
2513 * RETURN:
2514 * false if the given descriptors memory area is not aligned according to
2515 * Ethernet SDMA specifications.
2516 * true otherwise.
2517 *
2518 *******************************************************************************/
2519 static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
2520 ETH_QUEUE rx_queue,
2521 int rx_desc_num,
2522 int rx_buff_size,
2523 unsigned int rx_desc_base_addr,
2524 unsigned int rx_buff_base_addr)
2525 {
2526 ETH_RX_DESC *p_rx_desc;
2527 ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */
2528 unsigned int buffer_addr;
2529 int ix; /* a counter */
2530
2531
2532 p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
2533 p_rx_prev_desc = p_rx_desc;
2534 buffer_addr = rx_buff_base_addr;
2535
2536 /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
2537 if (rx_buff_base_addr & 0xF)
2538 return false;
2539
2540 /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */
2541 if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
2542 return false;
2543
2544 /* Rx buffers must be 64-bit aligned. */
2545 if ((rx_buff_base_addr + rx_buff_size) & 0x7)
2546 return false;
2547
2548 /* initialize the Rx descriptors ring */
2549 for (ix = 0; ix < rx_desc_num; ix++) {
2550 p_rx_desc->buf_size = rx_buff_size;
2551 p_rx_desc->byte_cnt = 0x0000;
2552 p_rx_desc->cmd_sts =
2553 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2554 p_rx_desc->next_desc_ptr =
2555 ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
2556 p_rx_desc->buf_ptr = buffer_addr;
2557 p_rx_desc->return_info = 0x00000000;
2558 D_CACHE_FLUSH_LINE (p_rx_desc, 0);
2559 buffer_addr += rx_buff_size;
2560 p_rx_prev_desc = p_rx_desc;
2561 p_rx_desc = (ETH_RX_DESC *)
2562 ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
2563 }
2564
2565 /* Closing Rx descriptors ring */
2566 p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
2567 D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
2568
2569 /* Save Rx desc pointer to driver struct. */
2570 CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
2571 USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
2572
2573 p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
2574 (ETH_RX_DESC *) rx_desc_base_addr;
2575 p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
2576 rx_desc_num * RX_DESC_ALIGNED_SIZE;
2577
2578 p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
2579
2580 return true;
2581 }
2582
2583 /*******************************************************************************
2584 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
2585 *
2586 * DESCRIPTION:
2587 * This function prepares a Tx chained list of descriptors and packet
2588 * buffers in a form of a ring. The routine must be called after port
2589 * initialization routine and before port start routine.
2590 * The Ethernet SDMA engine uses CPU bus addresses to access the various
2591 * devices in the system (i.e. DRAM). This function uses the ethernet
2592 * struct 'virtual to physical' routine (set by the user) to set the ring
2593 * with physical addresses.
2594 *
2595 * INPUT:
2596 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2597 * ETH_QUEUE tx_queue Number of Tx queue.
2598 * int tx_desc_num Number of Tx descriptors
2599 * int tx_buff_size Size of Tx buffer
2600 * unsigned int tx_desc_base_addr Tx descriptors memory area base addr.
2601 * unsigned int tx_buff_base_addr Tx buffer memory area base addr.
2602 *
2603 * OUTPUT:
2604 * The routine updates the Ethernet port control struct with information
2605 * regarding the Tx descriptors and buffers.
2606 *
2607 * RETURN:
2608 * false if the given descriptors memory area is not aligned according to
2609 * Ethernet SDMA specifications.
2610 * true otherwise.
2611 *
2612 *******************************************************************************/
2613 static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
2614 ETH_QUEUE tx_queue,
2615 int tx_desc_num,
2616 int tx_buff_size,
2617 unsigned int tx_desc_base_addr,
2618 unsigned int tx_buff_base_addr)
2619 {
2620
2621 ETH_TX_DESC *p_tx_desc;
2622 ETH_TX_DESC *p_tx_prev_desc;
2623 unsigned int buffer_addr;
2624 int ix; /* a counter */
2625
2626
2627 /* save the first desc pointer to link with the last descriptor */
2628 p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
2629 p_tx_prev_desc = p_tx_desc;
2630 buffer_addr = tx_buff_base_addr;
2631
2632 /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
2633 if (tx_buff_base_addr & 0xF)
2634 return false;
2635
2636 /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */
2637 if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
2638 || (tx_buff_size < TX_BUFFER_MIN_SIZE))
2639 return false;
2640
2641 /* Initialize the Tx descriptors ring */
2642 for (ix = 0; ix < tx_desc_num; ix++) {
2643 p_tx_desc->byte_cnt = 0x0000;
2644 p_tx_desc->l4i_chk = 0x0000;
2645 p_tx_desc->cmd_sts = 0x00000000;
2646 p_tx_desc->next_desc_ptr =
2647 ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
2648
2649 p_tx_desc->buf_ptr = buffer_addr;
2650 p_tx_desc->return_info = 0x00000000;
2651 D_CACHE_FLUSH_LINE (p_tx_desc, 0);
2652 buffer_addr += tx_buff_size;
2653 p_tx_prev_desc = p_tx_desc;
2654 p_tx_desc = (ETH_TX_DESC *)
2655 ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
2656
2657 }
2658 /* Closing Tx descriptors ring */
2659 p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
2660 D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
2661 /* Set Tx desc pointer in driver struct. */
2662 CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
2663 USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
2664
2665 /* Init Tx ring base and size parameters */
2666 p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
2667 (ETH_TX_DESC *) tx_desc_base_addr;
2668 p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
2669 (tx_desc_num * TX_DESC_ALIGNED_SIZE);
2670
2671 /* Add the queue to the list of Tx queues of this port */
2672 p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
2673
2674 return true;
2675 }
2676
2677 /*******************************************************************************
2678 * eth_port_send - Send an Ethernet packet
2679 *
2680 * DESCRIPTION:
2681 * This routine send a given packet described by p_pktinfo parameter. It
2682 * supports transmitting of a packet spaned over multiple buffers. The
2683 * routine updates 'curr' and 'first' indexes according to the packet
2684 * segment passed to the routine. In case the packet segment is first,
2685 * the 'first' index is update. In any case, the 'curr' index is updated.
2686 * If the routine get into Tx resource error it assigns 'curr' index as
2687 * 'first'. This way the function can abort Tx process of multiple
2688 * descriptors per packet.
2689 *
2690 * INPUT:
2691 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2692 * ETH_QUEUE tx_queue Number of Tx queue.
2693 * PKT_INFO *p_pkt_info User packet buffer.
2694 *
2695 * OUTPUT:
2696 * Tx ring 'curr' and 'first' indexes are updated.
2697 *
2698 * RETURN:
2699 * ETH_QUEUE_FULL in case of Tx resource error.
2700 * ETH_ERROR in case the routine can not access Tx desc ring.
2701 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2702 * ETH_OK otherwise.
2703 *
2704 *******************************************************************************/
2705 static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
2706 ETH_QUEUE tx_queue,
2707 PKT_INFO * p_pkt_info)
2708 {
2709 volatile ETH_TX_DESC *p_tx_desc_first;
2710 volatile ETH_TX_DESC *p_tx_desc_curr;
2711 volatile ETH_TX_DESC *p_tx_next_desc_curr;
2712 volatile ETH_TX_DESC *p_tx_desc_used;
2713 unsigned int command_status;
2714
2715 /* Do not process Tx ring in case of Tx ring resource error */
2716 if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
2717 return ETH_QUEUE_FULL;
2718
2719 /* Get the Tx Desc ring indexes */
2720 CURR_TFD_GET (p_tx_desc_curr, tx_queue);
2721 USED_TFD_GET (p_tx_desc_used, tx_queue);
2722
2723 if (p_tx_desc_curr == NULL)
2724 return ETH_ERROR;
2725
2726 /* The following parameters are used to save readings from memory */
2727 p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
2728 command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
2729
2730 if (command_status & (ETH_TX_FIRST_DESC)) {
2731 /* Update first desc */
2732 FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
2733 p_tx_desc_first = p_tx_desc_curr;
2734 } else {
2735 FIRST_TFD_GET (p_tx_desc_first, tx_queue);
2736 command_status |= ETH_BUFFER_OWNED_BY_DMA;
2737 }
2738
2739 /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
2740 /* boundary. We use the memory allocated for Tx descriptor. This memory */
2741 /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
2742 if (p_pkt_info->byte_cnt <= 8) {
2743 printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */
2744 return ETH_ERROR;
2745
2746 p_tx_desc_curr->buf_ptr =
2747 (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
2748 eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
2749 p_pkt_info->byte_cnt);
2750 } else
2751 p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
2752
2753 p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
2754 p_tx_desc_curr->return_info = p_pkt_info->return_info;
2755
2756 if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
2757 /* Set last desc with DMA ownership and interrupt enable. */
2758 p_tx_desc_curr->cmd_sts = command_status |
2759 ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
2760
2761 if (p_tx_desc_curr != p_tx_desc_first)
2762 p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
2763
2764 /* Flush CPU pipe */
2765
2766 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
2767 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
2768 CPU_PIPE_FLUSH;
2769
2770 /* Apply send command */
2771 ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
2772
2773 /* Finish Tx packet. Update first desc in case of Tx resource error */
2774 p_tx_desc_first = p_tx_next_desc_curr;
2775 FIRST_TFD_SET (p_tx_desc_first, tx_queue);
2776
2777 } else {
2778 p_tx_desc_curr->cmd_sts = command_status;
2779 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
2780 }
2781
2782 /* Check for ring index overlap in the Tx desc ring */
2783 if (p_tx_next_desc_curr == p_tx_desc_used) {
2784 /* Update the current descriptor */
2785 CURR_TFD_SET (p_tx_desc_first, tx_queue);
2786
2787 p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
2788 return ETH_QUEUE_LAST_RESOURCE;
2789 } else {
2790 /* Update the current descriptor */
2791 CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
2792 return ETH_OK;
2793 }
2794 }
2795
2796 /*******************************************************************************
2797 * eth_tx_return_desc - Free all used Tx descriptors
2798 *
2799 * DESCRIPTION:
2800 * This routine returns the transmitted packet information to the caller.
2801 * It uses the 'first' index to support Tx desc return in case a transmit
2802 * of a packet spanned over multiple buffer still in process.
2803 * In case the Tx queue was in "resource error" condition, where there are
2804 * no available Tx resources, the function resets the resource error flag.
2805 *
2806 * INPUT:
2807 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2808 * ETH_QUEUE tx_queue Number of Tx queue.
2809 * PKT_INFO *p_pkt_info User packet buffer.
2810 *
2811 * OUTPUT:
2812 * Tx ring 'first' and 'used' indexes are updated.
2813 *
2814 * RETURN:
2815 * ETH_ERROR in case the routine can not access Tx desc ring.
2816 * ETH_RETRY in case there is transmission in process.
2817 * ETH_END_OF_JOB if the routine has nothing to release.
2818 * ETH_OK otherwise.
2819 *
2820 *******************************************************************************/
2821 static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
2822 p_eth_port_ctrl,
2823 ETH_QUEUE tx_queue,
2824 PKT_INFO * p_pkt_info)
2825 {
2826 volatile ETH_TX_DESC *p_tx_desc_used = NULL;
2827 volatile ETH_TX_DESC *p_tx_desc_first = NULL;
2828 unsigned int command_status;
2829
2830
2831 /* Get the Tx Desc ring indexes */
2832 USED_TFD_GET (p_tx_desc_used, tx_queue);
2833 FIRST_TFD_GET (p_tx_desc_first, tx_queue);
2834
2835
2836 /* Sanity check */
2837 if (p_tx_desc_used == NULL)
2838 return ETH_ERROR;
2839
2840 command_status = p_tx_desc_used->cmd_sts;
2841
2842 /* Still transmitting... */
2843 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2844 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
2845 return ETH_RETRY;
2846 }
2847
2848 /* Stop release. About to overlap the current available Tx descriptor */
2849 if ((p_tx_desc_used == p_tx_desc_first) &&
2850 (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
2851 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
2852 return ETH_END_OF_JOB;
2853 }
2854
2855 /* Pass the packet information to the caller */
2856 p_pkt_info->cmd_sts = command_status;
2857 p_pkt_info->return_info = p_tx_desc_used->return_info;
2858 p_tx_desc_used->return_info = 0;
2859
2860 /* Update the next descriptor to release. */
2861 USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
2862
2863 /* Any Tx return cancels the Tx resource error status */
2864 if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
2865 p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
2866
2867 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
2868
2869 return ETH_OK;
2870
2871 }
2872
2873 /*******************************************************************************
2874 * eth_port_receive - Get received information from Rx ring.
2875 *
2876 * DESCRIPTION:
2877 * This routine returns the received data to the caller. There is no
2878 * data copying during routine operation. All information is returned
2879 * using pointer to packet information struct passed from the caller.
2880 * If the routine exhausts Rx ring resources then the resource error flag
2881 * is set.
2882 *
2883 * INPUT:
2884 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2885 * ETH_QUEUE rx_queue Number of Rx queue.
2886 * PKT_INFO *p_pkt_info User packet buffer.
2887 *
2888 * OUTPUT:
2889 * Rx ring current and used indexes are updated.
2890 *
2891 * RETURN:
2892 * ETH_ERROR in case the routine can not access Rx desc ring.
2893 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2894 * ETH_END_OF_JOB if there is no received data.
2895 * ETH_OK otherwise.
2896 *
2897 *******************************************************************************/
2898 static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
2899 ETH_QUEUE rx_queue,
2900 PKT_INFO * p_pkt_info)
2901 {
2902 volatile ETH_RX_DESC *p_rx_curr_desc;
2903 volatile ETH_RX_DESC *p_rx_next_curr_desc;
2904 volatile ETH_RX_DESC *p_rx_used_desc;
2905 unsigned int command_status;
2906
2907 /* Do not process Rx ring in case of Rx ring resource error */
2908 if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
2909 printf ("\nRx Queue is full ...\n");
2910 return ETH_QUEUE_FULL;
2911 }
2912
2913 /* Get the Rx Desc ring 'curr and 'used' indexes */
2914 CURR_RFD_GET (p_rx_curr_desc, rx_queue);
2915 USED_RFD_GET (p_rx_used_desc, rx_queue);
2916
2917 /* Sanity check */
2918 if (p_rx_curr_desc == NULL)
2919 return ETH_ERROR;
2920
2921 /* The following parameters are used to save readings from memory */
2922 p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
2923 command_status = p_rx_curr_desc->cmd_sts;
2924
2925 /* Nothing to receive... */
2926 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2927 /* DP(printf("Rx: command_status: %08x\n", command_status)); */
2928 D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
2929 /* DP(printf("\nETH_END_OF_JOB ...\n"));*/
2930 return ETH_END_OF_JOB;
2931 }
2932
2933 p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
2934 p_pkt_info->cmd_sts = command_status;
2935 p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
2936 p_pkt_info->return_info = p_rx_curr_desc->return_info;
2937 p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */
2938
2939 /* Clean the return info field to indicate that the packet has been */
2940 /* moved to the upper layers */
2941 p_rx_curr_desc->return_info = 0;
2942
2943 /* Update 'curr' in data structure */
2944 CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
2945
2946 /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
2947 if (p_rx_next_curr_desc == p_rx_used_desc)
2948 p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
2949
2950 D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
2951 CPU_PIPE_FLUSH;
2952 return ETH_OK;
2953 }
2954
2955 /*******************************************************************************
2956 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2957 *
2958 * DESCRIPTION:
2959 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2960 * next 'used' descriptor and attached the returned buffer to it.
2961 * In case the Rx ring was in "resource error" condition, where there are
2962 * no available Rx resources, the function resets the resource error flag.
2963 *
2964 * INPUT:
2965 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2966 * ETH_QUEUE rx_queue Number of Rx queue.
2967 * PKT_INFO *p_pkt_info Information on the returned buffer.
2968 *
2969 * OUTPUT:
2970 * New available Rx resource in Rx descriptor ring.
2971 *
2972 * RETURN:
2973 * ETH_ERROR in case the routine can not access Rx desc ring.
2974 * ETH_OK otherwise.
2975 *
2976 *******************************************************************************/
2977 static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
2978 p_eth_port_ctrl,
2979 ETH_QUEUE rx_queue,
2980 PKT_INFO * p_pkt_info)
2981 {
2982 volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */
2983
2984 /* Get 'used' Rx descriptor */
2985 USED_RFD_GET (p_used_rx_desc, rx_queue);
2986
2987 /* Sanity check */
2988 if (p_used_rx_desc == NULL)
2989 return ETH_ERROR;
2990
2991 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
2992 p_used_rx_desc->return_info = p_pkt_info->return_info;
2993 p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
2994 p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE; /* Reset Buffer size */
2995
2996 /* Flush the write pipe */
2997 CPU_PIPE_FLUSH;
2998
2999 /* Return the descriptor to DMA ownership */
3000 p_used_rx_desc->cmd_sts =
3001 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
3002
3003 /* Flush descriptor and CPU pipe */
3004 D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
3005 CPU_PIPE_FLUSH;
3006
3007 /* Move the used descriptor pointer to the next descriptor */
3008 USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
3009
3010 /* Any Rx return cancels the Rx resource error status */
3011 if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
3012 p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
3013
3014 return ETH_OK;
3015 }
3016
3017 /*******************************************************************************
3018 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
3019 *
3020 * DESCRIPTION:
3021 * This routine sets the RX coalescing interrupt mechanism parameter.
3022 * This parameter is a timeout counter, that counts in 64 t_clk
3023 * chunks ; that when timeout event occurs a maskable interrupt
3024 * occurs.
3025 * The parameter is calculated using the tClk of the MV-643xx chip
3026 * , and the required delay of the interrupt in usec.
3027 *
3028 * INPUT:
3029 * ETH_PORT eth_port_num Ethernet port number
3030 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
3031 * unsigned int delay Delay in usec
3032 *
3033 * OUTPUT:
3034 * Interrupt coalescing mechanism value is set in MV-643xx chip.
3035 *
3036 * RETURN:
3037 * The interrupt coalescing value set in the gigE port.
3038 *
3039 *******************************************************************************/
3040 #if 0 /* FIXME */
3041 static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
3042 unsigned int t_clk,
3043 unsigned int delay)
3044 {
3045 unsigned int coal;
3046
3047 coal = ((t_clk / 1000000) * delay) / 64;
3048 /* Set RX Coalescing mechanism */
3049 MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
3050 ((coal & 0x3fff) << 8) |
3051 (MV_REG_READ
3052 (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num))
3053 & 0xffc000ff));
3054 return coal;
3055 }
3056
3057 #endif
3058 /*******************************************************************************
3059 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
3060 *
3061 * DESCRIPTION:
3062 * This routine sets the TX coalescing interrupt mechanism parameter.
3063 * This parameter is a timeout counter, that counts in 64 t_clk
3064 * chunks ; that when timeout event occurs a maskable interrupt
3065 * occurs.
3066 * The parameter is calculated using the t_cLK frequency of the
3067 * MV-643xx chip and the required delay in the interrupt in uSec
3068 *
3069 * INPUT:
3070 * ETH_PORT eth_port_num Ethernet port number
3071 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
3072 * unsigned int delay Delay in uSeconds
3073 *
3074 * OUTPUT:
3075 * Interrupt coalescing mechanism value is set in MV-643xx chip.
3076 *
3077 * RETURN:
3078 * The interrupt coalescing value set in the gigE port.
3079 *
3080 *******************************************************************************/
3081 #if 0 /* FIXME */
3082 static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
3083 unsigned int t_clk,
3084 unsigned int delay)
3085 {
3086 unsigned int coal;
3087
3088 coal = ((t_clk / 1000000) * delay) / 64;
3089 /* Set TX Coalescing mechanism */
3090 MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
3091 coal << 4);
3092 return coal;
3093 }
3094 #endif
3095
3096 /*******************************************************************************
3097 * eth_b_copy - Copy bytes from source to destination
3098 *
3099 * DESCRIPTION:
3100 * This function supports the eight bytes limitation on Tx buffer size.
3101 * The routine will zero eight bytes starting from the destination address
3102 * followed by copying bytes from the source address to the destination.
3103 *
3104 * INPUT:
3105 * unsigned int src_addr 32 bit source address.
3106 * unsigned int dst_addr 32 bit destination address.
3107 * int byte_count Number of bytes to copy.
3108 *
3109 * OUTPUT:
3110 * See description.
3111 *
3112 * RETURN:
3113 * None.
3114 *
3115 *******************************************************************************/
3116 static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
3117 int byte_count)
3118 {
3119 /* Zero the dst_addr area */
3120 *(unsigned int *) dst_addr = 0x0;
3121
3122 while (byte_count != 0) {
3123 *(char *) dst_addr = *(char *) src_addr;
3124 dst_addr++;
3125 src_addr++;
3126 byte_count--;
3127 }
3128 }
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