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[people/ms/u-boot.git] / board / Marvell / db64360 / mv_eth.h
1 /*
2 * (C) Copyright 2003
3 * Ingo Assmus <ingo.assmus@keymile.com>
4 *
5 * based on - Driver for MV64360X ethernet ports
6 * Copyright (C) 2002 rabeeh@galileo.co.il
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 /*
12 * mv_eth.h - header file for the polled mode GT ethernet driver
13 */
14
15 #ifndef __DB64360_ETH_H__
16 #define __DB64360_ETH_H__
17
18 #include <asm/types.h>
19 #include <asm/io.h>
20 #include <asm/byteorder.h>
21 #include <common.h>
22 #include <net.h>
23 #include "mv_regs.h"
24 #include <asm/errno.h>
25
26 /*************************************************************************
27 **************************************************************************
28 **************************************************************************
29 * The first part is the high level driver of the gigE ethernet ports. *
30 **************************************************************************
31 **************************************************************************
32 *************************************************************************/
33 /* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
34 #ifndef MAX_SKB_FRAGS
35 #define MAX_SKB_FRAGS 0
36 #endif
37
38 /* Port attributes */
39 /*#define MAX_RX_QUEUE_NUM 8*/
40 /*#define MAX_TX_QUEUE_NUM 8*/
41 #define MAX_RX_QUEUE_NUM 1
42 #define MAX_TX_QUEUE_NUM 1
43
44
45 /* Use one TX queue and one RX queue */
46 #define MV64360_TX_QUEUE_NUM 1
47 #define MV64360_RX_QUEUE_NUM 1
48
49 /*
50 * Number of RX / TX descriptors on RX / TX rings.
51 * Note that allocating RX descriptors is done by allocating the RX
52 * ring AND a preallocated RX buffers (skb's) for each descriptor.
53 * The TX descriptors only allocates the TX descriptors ring,
54 * with no pre allocated TX buffers (skb's are allocated by higher layers.
55 */
56
57 /* Default TX ring size is 10 descriptors */
58 #ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
59 #define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
60 #else
61 #define MV64360_TX_QUEUE_SIZE 4
62 #endif
63
64 /* Default RX ring size is 4 descriptors */
65 #ifdef CONFIG_MV64360_ETH_RXQUEUE_SIZE
66 #define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
67 #else
68 #define MV64360_RX_QUEUE_SIZE 4
69 #endif
70
71 #ifdef CONFIG_RX_BUFFER_SIZE
72 #define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
73 #else
74 #define MV64360_RX_BUFFER_SIZE 1600
75 #endif
76
77 #ifdef CONFIG_TX_BUFFER_SIZE
78 #define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
79 #else
80 #define MV64360_TX_BUFFER_SIZE 1600
81 #endif
82
83
84 /*
85 * Network device statistics. Akin to the 2.0 ether stats but
86 * with byte counters.
87 */
88
89 struct net_device_stats
90 {
91 unsigned long rx_packets; /* total packets received */
92 unsigned long tx_packets; /* total packets transmitted */
93 unsigned long rx_bytes; /* total bytes received */
94 unsigned long tx_bytes; /* total bytes transmitted */
95 unsigned long rx_errors; /* bad packets received */
96 unsigned long tx_errors; /* packet transmit problems */
97 unsigned long rx_dropped; /* no space in linux buffers */
98 unsigned long tx_dropped; /* no space available in linux */
99 unsigned long multicast; /* multicast packets received */
100 unsigned long collisions;
101
102 /* detailed rx_errors: */
103 unsigned long rx_length_errors;
104 unsigned long rx_over_errors; /* receiver ring buff overflow */
105 unsigned long rx_crc_errors; /* recved pkt with crc error */
106 unsigned long rx_frame_errors; /* recv'd frame alignment error */
107 unsigned long rx_fifo_errors; /* recv'r fifo overrun */
108 unsigned long rx_missed_errors; /* receiver missed packet */
109
110 /* detailed tx_errors */
111 unsigned long tx_aborted_errors;
112 unsigned long tx_carrier_errors;
113 unsigned long tx_fifo_errors;
114 unsigned long tx_heartbeat_errors;
115 unsigned long tx_window_errors;
116
117 /* for cslip etc */
118 unsigned long rx_compressed;
119 unsigned long tx_compressed;
120 };
121
122
123 /* Private data structure used for ethernet device */
124 struct mv64360_eth_priv {
125 unsigned int port_num;
126 struct net_device_stats *stats;
127
128 /* to buffer area aligned */
129 char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */
130 char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */
131
132 /* Size of Tx Ring per queue */
133 unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
134
135
136 /* Size of Rx Ring per queue */
137 unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
138
139 /* Magic Number for Ethernet running */
140 unsigned int eth_running;
141
142 };
143
144
145 int mv64360_eth_init (struct eth_device *dev);
146 int mv64360_eth_stop (struct eth_device *dev);
147 int mv64360_eth_start_xmit(struct eth_device *dev, void *packet, int length);
148 int mv64360_eth_open (struct eth_device *dev);
149
150
151 /*************************************************************************
152 **************************************************************************
153 **************************************************************************
154 * The second part is the low level driver of the gigE ethernet ports. *
155 **************************************************************************
156 **************************************************************************
157 *************************************************************************/
158
159
160 /********************************************************************************
161 * Header File for : MV-643xx network interface header
162 *
163 * DESCRIPTION:
164 * This header file contains macros typedefs and function declaration for
165 * the Marvell Gig Bit Ethernet Controller.
166 *
167 * DEPENDENCIES:
168 * None.
169 *
170 *******************************************************************************/
171
172
173 #ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
174 #ifdef CONFIG_MV64360_SRAM_CACHEABLE
175 /* In case SRAM is cacheable but not cache coherent */
176 #define D_CACHE_FLUSH_LINE(addr, offset) \
177 { \
178 __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
179 }
180 #else
181 /* In case SRAM is cache coherent or non-cacheable */
182 #define D_CACHE_FLUSH_LINE(addr, offset) ;
183 #endif
184 #else
185 #ifdef CONFIG_NOT_COHERENT_CACHE
186 /* In case of descriptors on DDR but not cache coherent */
187 #define D_CACHE_FLUSH_LINE(addr, offset) \
188 { \
189 __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
190 }
191 #else
192 /* In case of descriptors on DDR and cache coherent */
193 #define D_CACHE_FLUSH_LINE(addr, offset) ;
194 #endif /* CONFIG_NOT_COHERENT_CACHE */
195 #endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
196
197
198 #define CPU_PIPE_FLUSH \
199 { \
200 __asm__ __volatile__ ("eieio"); \
201 }
202
203
204 /* defines */
205
206 /* Default port configuration value */
207 #define PORT_CONFIG_VALUE \
208 ETH_UNICAST_NORMAL_MODE | \
209 ETH_DEFAULT_RX_QUEUE_0 | \
210 ETH_DEFAULT_RX_ARP_QUEUE_0 | \
211 ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
212 ETH_RECEIVE_BC_IF_IP | \
213 ETH_RECEIVE_BC_IF_ARP | \
214 ETH_CAPTURE_TCP_FRAMES_DIS | \
215 ETH_CAPTURE_UDP_FRAMES_DIS | \
216 ETH_DEFAULT_RX_TCP_QUEUE_0 | \
217 ETH_DEFAULT_RX_UDP_QUEUE_0 | \
218 ETH_DEFAULT_RX_BPDU_QUEUE_0
219
220 /* Default port extend configuration value */
221 #define PORT_CONFIG_EXTEND_VALUE \
222 ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
223 ETH_PARTITION_DISABLE
224
225
226 /* Default sdma control value */
227 #ifdef CONFIG_NOT_COHERENT_CACHE
228 #define PORT_SDMA_CONFIG_VALUE \
229 ETH_RX_BURST_SIZE_16_64BIT | \
230 GT_ETH_IPG_INT_RX(0) | \
231 ETH_TX_BURST_SIZE_16_64BIT;
232 #else
233 #define PORT_SDMA_CONFIG_VALUE \
234 ETH_RX_BURST_SIZE_4_64BIT | \
235 GT_ETH_IPG_INT_RX(0) | \
236 ETH_TX_BURST_SIZE_4_64BIT;
237 #endif
238
239 #define GT_ETH_IPG_INT_RX(value) \
240 ((value & 0x3fff) << 8)
241
242 /* Default port serial control value */
243 #define PORT_SERIAL_CONTROL_VALUE \
244 ETH_FORCE_LINK_PASS | \
245 ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
246 ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
247 ETH_ADV_SYMMETRIC_FLOW_CTRL | \
248 ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
249 ETH_FORCE_BP_MODE_NO_JAM | \
250 BIT9 | \
251 ETH_DO_NOT_FORCE_LINK_FAIL | \
252 ETH_RETRANSMIT_16_ETTEMPTS | \
253 ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
254 ETH_DTE_ADV_0 | \
255 ETH_DISABLE_AUTO_NEG_BYPASS | \
256 ETH_AUTO_NEG_NO_CHANGE | \
257 ETH_MAX_RX_PACKET_1552BYTE | \
258 ETH_CLR_EXT_LOOPBACK | \
259 ETH_SET_FULL_DUPLEX_MODE | \
260 ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
261
262 #define RX_BUFFER_MAX_SIZE 0xFFFF
263 #define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */
264
265 #define RX_BUFFER_MIN_SIZE 0x8
266 #define TX_BUFFER_MIN_SIZE 0x8
267
268 /* Tx WRR confoguration macros */
269 #define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
270 #define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */
271 #define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */
272
273 /* MAC accepet/reject macros */
274 #define ACCEPT_MAC_ADDR 0
275 #define REJECT_MAC_ADDR 1
276
277 /* Size of a Tx/Rx descriptor used in chain list data structure */
278 #define RX_DESC_ALIGNED_SIZE 0x20
279 #define TX_DESC_ALIGNED_SIZE 0x20
280
281 /* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
282 #define TX_BUF_OFFSET_IN_DESC 0x18
283 /* Buffer offset from buffer pointer */
284 #define RX_BUF_OFFSET 0x2
285
286 /* Gap define */
287 #define ETH_BAR_GAP 0x8
288 #define ETH_SIZE_REG_GAP 0x8
289 #define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4
290 #define ETH_PORT_ACCESS_CTRL_GAP 0x4
291
292 /* Gigabit Ethernet Unit Global Registers */
293
294 /* MIB Counters register definitions */
295 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
296 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
297 #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
298 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
299 #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
300 #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
301 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
302 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
303 #define ETH_MIB_FRAMES_64_OCTETS 0x20
304 #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
305 #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
306 #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
307 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
308 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
309 #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
310 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
311 #define ETH_MIB_GOOD_FRAMES_SENT 0x40
312 #define ETH_MIB_EXCESSIVE_COLLISION 0x44
313 #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
314 #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
315 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
316 #define ETH_MIB_FC_SENT 0x54
317 #define ETH_MIB_GOOD_FC_RECEIVED 0x58
318 #define ETH_MIB_BAD_FC_RECEIVED 0x5c
319 #define ETH_MIB_UNDERSIZE_RECEIVED 0x60
320 #define ETH_MIB_FRAGMENTS_RECEIVED 0x64
321 #define ETH_MIB_OVERSIZE_RECEIVED 0x68
322 #define ETH_MIB_JABBER_RECEIVED 0x6c
323 #define ETH_MIB_MAC_RECEIVE_ERROR 0x70
324 #define ETH_MIB_BAD_CRC_EVENT 0x74
325 #define ETH_MIB_COLLISION 0x78
326 #define ETH_MIB_LATE_COLLISION 0x7c
327
328 /* Port serial status reg (PSR) */
329 #define ETH_INTERFACE_GMII_MII 0
330 #define ETH_INTERFACE_PCM BIT0
331 #define ETH_LINK_IS_DOWN 0
332 #define ETH_LINK_IS_UP BIT1
333 #define ETH_PORT_AT_HALF_DUPLEX 0
334 #define ETH_PORT_AT_FULL_DUPLEX BIT2
335 #define ETH_RX_FLOW_CTRL_DISABLED 0
336 #define ETH_RX_FLOW_CTRL_ENBALED BIT3
337 #define ETH_GMII_SPEED_100_10 0
338 #define ETH_GMII_SPEED_1000 BIT4
339 #define ETH_MII_SPEED_10 0
340 #define ETH_MII_SPEED_100 BIT5
341 #define ETH_NO_TX 0
342 #define ETH_TX_IN_PROGRESS BIT7
343 #define ETH_BYPASS_NO_ACTIVE 0
344 #define ETH_BYPASS_ACTIVE BIT8
345 #define ETH_PORT_NOT_AT_PARTITION_STATE 0
346 #define ETH_PORT_AT_PARTITION_STATE BIT9
347 #define ETH_PORT_TX_FIFO_NOT_EMPTY 0
348 #define ETH_PORT_TX_FIFO_EMPTY BIT10
349
350
351 /* These macros describes the Port configuration reg (Px_cR) bits */
352 #define ETH_UNICAST_NORMAL_MODE 0
353 #define ETH_UNICAST_PROMISCUOUS_MODE BIT0
354 #define ETH_DEFAULT_RX_QUEUE_0 0
355 #define ETH_DEFAULT_RX_QUEUE_1 BIT1
356 #define ETH_DEFAULT_RX_QUEUE_2 BIT2
357 #define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
358 #define ETH_DEFAULT_RX_QUEUE_4 BIT3
359 #define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
360 #define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
361 #define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
362 #define ETH_DEFAULT_RX_ARP_QUEUE_0 0
363 #define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
364 #define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
365 #define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
366 #define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
367 #define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
368 #define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
369 #define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
370 #define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
371 #define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
372 #define ETH_RECEIVE_BC_IF_IP 0
373 #define ETH_REJECT_BC_IF_IP BIT8
374 #define ETH_RECEIVE_BC_IF_ARP 0
375 #define ETH_REJECT_BC_IF_ARP BIT9
376 #define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
377 #define ETH_CAPTURE_TCP_FRAMES_DIS 0
378 #define ETH_CAPTURE_TCP_FRAMES_EN BIT14
379 #define ETH_CAPTURE_UDP_FRAMES_DIS 0
380 #define ETH_CAPTURE_UDP_FRAMES_EN BIT15
381 #define ETH_DEFAULT_RX_TCP_QUEUE_0 0
382 #define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
383 #define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
384 #define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
385 #define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
386 #define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
387 #define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
388 #define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
389 #define ETH_DEFAULT_RX_UDP_QUEUE_0 0
390 #define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
391 #define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
392 #define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
393 #define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
394 #define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
395 #define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
396 #define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
397 #define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
398 #define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
399 #define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
400 #define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
401 #define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
402 #define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
403 #define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
404 #define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
405
406
407 /* These macros describes the Port configuration extend reg (Px_cXR) bits*/
408 #define ETH_CLASSIFY_EN BIT0
409 #define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
410 #define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
411 #define ETH_PARTITION_DISABLE 0
412 #define ETH_PARTITION_ENABLE BIT2
413
414
415 /* Tx/Rx queue command reg (RQCR/TQCR)*/
416 #define ETH_QUEUE_0_ENABLE BIT0
417 #define ETH_QUEUE_1_ENABLE BIT1
418 #define ETH_QUEUE_2_ENABLE BIT2
419 #define ETH_QUEUE_3_ENABLE BIT3
420 #define ETH_QUEUE_4_ENABLE BIT4
421 #define ETH_QUEUE_5_ENABLE BIT5
422 #define ETH_QUEUE_6_ENABLE BIT6
423 #define ETH_QUEUE_7_ENABLE BIT7
424 #define ETH_QUEUE_0_DISABLE BIT8
425 #define ETH_QUEUE_1_DISABLE BIT9
426 #define ETH_QUEUE_2_DISABLE BIT10
427 #define ETH_QUEUE_3_DISABLE BIT11
428 #define ETH_QUEUE_4_DISABLE BIT12
429 #define ETH_QUEUE_5_DISABLE BIT13
430 #define ETH_QUEUE_6_DISABLE BIT14
431 #define ETH_QUEUE_7_DISABLE BIT15
432
433
434 /* These macros describes the Port Sdma configuration reg (SDCR) bits */
435 #define ETH_RIFB BIT0
436 #define ETH_RX_BURST_SIZE_1_64BIT 0
437 #define ETH_RX_BURST_SIZE_2_64BIT BIT1
438 #define ETH_RX_BURST_SIZE_4_64BIT BIT2
439 #define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
440 #define ETH_RX_BURST_SIZE_16_64BIT BIT3
441 #define ETH_BLM_RX_NO_SWAP BIT4
442 #define ETH_BLM_RX_BYTE_SWAP 0
443 #define ETH_BLM_TX_NO_SWAP BIT5
444 #define ETH_BLM_TX_BYTE_SWAP 0
445 #define ETH_DESCRIPTORS_BYTE_SWAP BIT6
446 #define ETH_DESCRIPTORS_NO_SWAP 0
447 #define ETH_TX_BURST_SIZE_1_64BIT 0
448 #define ETH_TX_BURST_SIZE_2_64BIT BIT22
449 #define ETH_TX_BURST_SIZE_4_64BIT BIT23
450 #define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
451 #define ETH_TX_BURST_SIZE_16_64BIT BIT24
452
453
454 /* These macros describes the Port serial control reg (PSCR) bits */
455 #define ETH_SERIAL_PORT_DISABLE 0
456 #define ETH_SERIAL_PORT_ENABLE BIT0
457 #define ETH_FORCE_LINK_PASS BIT1
458 #define ETH_DO_NOT_FORCE_LINK_PASS 0
459 #define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
460 #define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
461 #define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
462 #define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
463 #define ETH_ADV_NO_FLOW_CTRL 0
464 #define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
465 #define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
466 #define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
467 #define ETH_FORCE_BP_MODE_NO_JAM 0
468 #define ETH_FORCE_BP_MODE_JAM_TX BIT7
469 #define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
470 #define ETH_FORCE_LINK_FAIL 0
471 #define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
472 #define ETH_RETRANSMIT_16_ETTEMPTS 0
473 #define ETH_RETRANSMIT_FOREVER BIT11
474 #define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
475 #define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
476 #define ETH_DTE_ADV_0 0
477 #define ETH_DTE_ADV_1 BIT14
478 #define ETH_DISABLE_AUTO_NEG_BYPASS 0
479 #define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
480 #define ETH_AUTO_NEG_NO_CHANGE 0
481 #define ETH_RESTART_AUTO_NEG BIT16
482 #define ETH_MAX_RX_PACKET_1518BYTE 0
483 #define ETH_MAX_RX_PACKET_1522BYTE BIT17
484 #define ETH_MAX_RX_PACKET_1552BYTE BIT18
485 #define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
486 #define ETH_MAX_RX_PACKET_9192BYTE BIT19
487 #define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
488 #define ETH_SET_EXT_LOOPBACK BIT20
489 #define ETH_CLR_EXT_LOOPBACK 0
490 #define ETH_SET_FULL_DUPLEX_MODE BIT21
491 #define ETH_SET_HALF_DUPLEX_MODE 0
492 #define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
493 #define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
494 #define ETH_SET_GMII_SPEED_TO_10_100 0
495 #define ETH_SET_GMII_SPEED_TO_1000 BIT23
496 #define ETH_SET_MII_SPEED_TO_10 0
497 #define ETH_SET_MII_SPEED_TO_100 BIT24
498
499
500 /* SMI reg */
501 #define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
502 #define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
503 #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
504 #define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
505
506 /* SDMA command status fields macros */
507
508 /* Tx & Rx descriptors status */
509 #define ETH_ERROR_SUMMARY (BIT0)
510
511 /* Tx & Rx descriptors command */
512 #define ETH_BUFFER_OWNED_BY_DMA (BIT31)
513
514 /* Tx descriptors status */
515 #define ETH_LC_ERROR (0 )
516 #define ETH_UR_ERROR (BIT1 )
517 #define ETH_RL_ERROR (BIT2 )
518 #define ETH_LLC_SNAP_FORMAT (BIT9 )
519
520 /* Rx descriptors status */
521 #define ETH_CRC_ERROR (0 )
522 #define ETH_OVERRUN_ERROR (BIT1 )
523 #define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
524 #define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
525 #define ETH_VLAN_TAGGED (BIT19)
526 #define ETH_BPDU_FRAME (BIT20)
527 #define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
528 #define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
529 #define ETH_OTHER_FRAME_TYPE (BIT22)
530 #define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
531 #define ETH_FRAME_TYPE_IP_V_4 (BIT24)
532 #define ETH_FRAME_HEADER_OK (BIT25)
533 #define ETH_RX_LAST_DESC (BIT26)
534 #define ETH_RX_FIRST_DESC (BIT27)
535 #define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
536 #define ETH_RX_ENABLE_INTERRUPT (BIT29)
537 #define ETH_LAYER_4_CHECKSUM_OK (BIT30)
538
539 /* Rx descriptors byte count */
540 #define ETH_FRAME_FRAGMENTED (BIT2)
541
542 /* Tx descriptors command */
543 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
544 #define ETH_FRAME_SET_TO_VLAN (BIT15)
545 #define ETH_TCP_FRAME (0 )
546 #define ETH_UDP_FRAME (BIT16)
547 #define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
548 #define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
549 #define ETH_ZERO_PADDING (BIT19)
550 #define ETH_TX_LAST_DESC (BIT20)
551 #define ETH_TX_FIRST_DESC (BIT21)
552 #define ETH_GEN_CRC (BIT22)
553 #define ETH_TX_ENABLE_INTERRUPT (BIT23)
554 #define ETH_AUTO_MODE (BIT30)
555
556 /* Address decode parameters */
557 /* Ethernet Base Address Register bits */
558 #define EBAR_TARGET_DRAM 0x00000000
559 #define EBAR_TARGET_DEVICE 0x00000001
560 #define EBAR_TARGET_CBS 0x00000002
561 #define EBAR_TARGET_PCI0 0x00000003
562 #define EBAR_TARGET_PCI1 0x00000004
563 #define EBAR_TARGET_CUNIT 0x00000005
564 #define EBAR_TARGET_AUNIT 0x00000006
565 #define EBAR_TARGET_GUNIT 0x00000007
566
567 /* Window attributes */
568 #define EBAR_ATTR_DRAM_CS0 0x00000E00
569 #define EBAR_ATTR_DRAM_CS1 0x00000D00
570 #define EBAR_ATTR_DRAM_CS2 0x00000B00
571 #define EBAR_ATTR_DRAM_CS3 0x00000700
572
573 /* DRAM Target interface */
574 #define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000
575 #define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000
576 #define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000
577
578 /* Device Bus Target interface */
579 #define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00
580 #define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00
581 #define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00
582 #define EBAR_ATTR_DEVICE_DEVCS3 0x00001700
583 #define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00
584
585 /* PCI Target interface */
586 #define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000
587 #define EBAR_ATTR_PCI_NO_SWAP 0x00000100
588 #define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200
589 #define EBAR_ATTR_PCI_WORD_SWAP 0x00000300
590 #define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
591 #define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400
592 #define EBAR_ATTR_PCI_IO_SPACE 0x00000000
593 #define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800
594 #define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000
595 #define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000
596
597 /* CPU 60x bus or internal SRAM interface */
598 #define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000
599 #define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100
600 #define EBAR_ATTR_CBS_SRAM 0x00000000
601 #define EBAR_ATTR_CBS_CPU_BUS 0x00000800
602
603 /* Window access control */
604 #define EWIN_ACCESS_NOT_ALLOWED 0
605 #define EWIN_ACCESS_READ_ONLY BIT0
606 #define EWIN_ACCESS_FULL (BIT1 | BIT0)
607 #define EWIN0_ACCESS_MASK 0x0003
608 #define EWIN1_ACCESS_MASK 0x000C
609 #define EWIN2_ACCESS_MASK 0x0030
610 #define EWIN3_ACCESS_MASK 0x00C0
611
612 /* typedefs */
613
614 typedef enum _eth_port
615 {
616 ETH_0 = 0,
617 ETH_1 = 1,
618 ETH_2 = 2
619 }ETH_PORT;
620
621 typedef enum _eth_func_ret_status
622 {
623 ETH_OK, /* Returned as expected. */
624 ETH_ERROR, /* Fundamental error. */
625 ETH_RETRY, /* Could not process request. Try later. */
626 ETH_END_OF_JOB, /* Ring has nothing to process. */
627 ETH_QUEUE_FULL, /* Ring resource error. */
628 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
629 }ETH_FUNC_RET_STATUS;
630
631 typedef enum _eth_queue
632 {
633 ETH_Q0 = 0,
634 ETH_Q1 = 1,
635 ETH_Q2 = 2,
636 ETH_Q3 = 3,
637 ETH_Q4 = 4,
638 ETH_Q5 = 5,
639 ETH_Q6 = 6,
640 ETH_Q7 = 7
641 } ETH_QUEUE;
642
643 typedef enum _addr_win
644 {
645 ETH_WIN0,
646 ETH_WIN1,
647 ETH_WIN2,
648 ETH_WIN3,
649 ETH_WIN4,
650 ETH_WIN5
651 } ETH_ADDR_WIN;
652
653 typedef enum _eth_target
654 {
655 ETH_TARGET_DRAM ,
656 ETH_TARGET_DEVICE,
657 ETH_TARGET_CBS ,
658 ETH_TARGET_PCI0 ,
659 ETH_TARGET_PCI1
660 }ETH_TARGET;
661
662 typedef struct _eth_rx_desc
663 {
664 unsigned short byte_cnt ; /* Descriptor buffer byte count */
665 unsigned short buf_size ; /* Buffer size */
666 unsigned int cmd_sts ; /* Descriptor command status */
667 unsigned int next_desc_ptr; /* Next descriptor pointer */
668 unsigned int buf_ptr ; /* Descriptor buffer pointer */
669 unsigned int return_info ; /* User resource return information */
670 } ETH_RX_DESC;
671
672
673 typedef struct _eth_tx_desc
674 {
675 unsigned short byte_cnt ; /* Descriptor buffer byte count */
676 unsigned short l4i_chk ; /* CPU provided TCP Checksum */
677 unsigned int cmd_sts ; /* Descriptor command status */
678 unsigned int next_desc_ptr; /* Next descriptor pointer */
679 unsigned int buf_ptr ; /* Descriptor buffer pointer */
680 unsigned int return_info ; /* User resource return information */
681 } ETH_TX_DESC;
682
683 /* Unified struct for Rx and Tx operations. The user is not required to */
684 /* be familier with neither Tx nor Rx descriptors. */
685 typedef struct _pkt_info
686 {
687 unsigned short byte_cnt ; /* Descriptor buffer byte count */
688 unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */
689 unsigned int cmd_sts ; /* Descriptor command status */
690 unsigned int buf_ptr ; /* Descriptor buffer pointer */
691 unsigned int return_info ; /* User resource return information */
692 } PKT_INFO;
693
694
695 typedef struct _eth_win_param
696 {
697 ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */
698 ETH_TARGET target; /* System targets. See ETH_TARGET enum */
699 unsigned short attributes; /* BAR attributes. See above macros. */
700 unsigned int base_addr; /* Window base address in unsigned int form */
701 unsigned int high_addr; /* Window high address in unsigned int form */
702 unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
703 bool enable; /* Enable/disable access to the window. */
704 unsigned short access_ctrl; /* Access ctrl register. see above macros */
705 } ETH_WIN_PARAM;
706
707
708 /* Ethernet port specific infomation */
709
710 typedef struct _eth_port_ctrl
711 {
712 ETH_PORT port_num; /* User Ethernet port number */
713 int port_phy_addr; /* User phy address of Ethrnet port */
714 unsigned char port_mac_addr[6]; /* User defined port MAC address. */
715 unsigned int port_config; /* User port configuration value */
716 unsigned int port_config_extend; /* User port config extend value */
717 unsigned int port_sdma_config; /* User port SDMA config value */
718 unsigned int port_serial_control; /* User port serial control value */
719 unsigned int port_tx_queue_command; /* Port active Tx queues summary */
720 unsigned int port_rx_queue_command; /* Port active Rx queues summary */
721
722 /* User function to cast virtual address to CPU bus address */
723 unsigned int (*port_virt_to_phys)(unsigned int addr);
724 /* User scratch pad for user specific data structures */
725 void *port_private;
726
727 bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
728 bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
729
730 /* Tx/Rx rings managment indexes fields. For driver use */
731
732 /* Next available Rx resource */
733 volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
734 /* Returning Rx resource */
735 volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
736
737 /* Next available Tx resource */
738 volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
739 /* Returning Tx resource */
740 volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
741 /* An extra Tx index to support transmit of multiple buffers per packet */
742 volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
743
744 /* Tx/Rx rings size and base variables fields. For driver use */
745
746 volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
747 unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM];
748 char *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
749
750 volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
751 unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM];
752 char *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
753
754 } ETH_PORT_INFO;
755
756
757 /* ethernet.h API list */
758
759 /* Port operation control routines */
760 static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
761 static void eth_port_reset(ETH_PORT eth_port_num);
762 static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
763
764
765 /* Port MAC address routines */
766 static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
767 unsigned char *p_addr,
768 ETH_QUEUE queue);
769 #if 0 /* FIXME */
770 static void eth_port_mc_addr (ETH_PORT eth_port_num,
771 unsigned char *p_addr,
772 ETH_QUEUE queue,
773 int option);
774 #endif
775
776 /* PHY and MIB routines */
777 static bool ethernet_phy_reset(ETH_PORT eth_port_num);
778
779 static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
780 unsigned int phy_reg,
781 unsigned int value);
782
783 static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
784 unsigned int phy_reg,
785 unsigned int* value);
786
787 static void eth_clear_mib_counters(ETH_PORT eth_port_num);
788
789 /* Port data flow control routines */
790 static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl,
791 ETH_QUEUE tx_queue,
792 PKT_INFO *p_pkt_info);
793 static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
794 ETH_QUEUE tx_queue,
795 PKT_INFO *p_pkt_info);
796 static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
797 ETH_QUEUE rx_queue,
798 PKT_INFO *p_pkt_info);
799 static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
800 ETH_QUEUE rx_queue,
801 PKT_INFO *p_pkt_info);
802
803
804 static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
805 ETH_QUEUE tx_queue,
806 int tx_desc_num,
807 int tx_buff_size,
808 unsigned int tx_desc_base_addr,
809 unsigned int tx_buff_base_addr);
810
811 static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
812 ETH_QUEUE rx_queue,
813 int rx_desc_num,
814 int rx_buff_size,
815 unsigned int rx_desc_base_addr,
816 unsigned int rx_buff_base_addr);
817
818 #endif /* MV64360_ETH_ */
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