3 * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /*************************************************************************
25 * changes for Marvell DB64460 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
27 ************************************************************************/
30 * mpsc.c - driver for console over the MPSC.
36 #include <asm/cache.h>
43 #include "../include/memory.h"
45 /* Define this if you wish to use the MPSC as a register based UART.
46 * This will force the serial port to not use the SDMA engine at all.
48 #undef CONFIG_MPSC_DEBUG_PORT
51 int (*mpsc_putchar
) (char ch
) = mpsc_putchar_early
;
52 char (*mpsc_getchar
) (void) = mpsc_getchar_debug
;
53 int (*mpsc_test_char
) (void) = mpsc_test_char_debug
;
56 static volatile unsigned int *rx_desc_base
= NULL
;
57 static unsigned int rx_desc_index
= 0;
58 static volatile unsigned int *tx_desc_base
= NULL
;
59 static unsigned int tx_desc_index
= 0;
61 /* local function declarations */
62 static int galmpsc_connect (int channel
, int connect
);
63 static int galmpsc_route_rx_clock (int channel
, int brg
);
64 static int galmpsc_route_tx_clock (int channel
, int brg
);
65 static int galmpsc_write_config_regs (int mpsc
, int mode
);
66 static int galmpsc_config_channel_regs (int mpsc
);
67 static int galmpsc_set_char_length (int mpsc
, int value
);
68 static int galmpsc_set_stop_bit_length (int mpsc
, int value
);
69 static int galmpsc_set_parity (int mpsc
, int value
);
70 static int galmpsc_enter_hunt (int mpsc
);
71 static int galmpsc_set_brkcnt (int mpsc
, int value
);
72 static int galmpsc_set_tcschar (int mpsc
, int value
);
73 static int galmpsc_set_snoop (int mpsc
, int value
);
74 static int galmpsc_shutdown (int mpsc
);
76 static int galsdma_set_RFT (int channel
);
77 static int galsdma_set_SFM (int channel
);
78 static int galsdma_set_rxle (int channel
);
79 static int galsdma_set_txle (int channel
);
80 static int galsdma_set_burstsize (int channel
, unsigned int value
);
81 static int galsdma_set_RC (int channel
, unsigned int value
);
83 static int galbrg_set_CDV (int channel
, int value
);
84 static int galbrg_enable (int channel
);
85 static int galbrg_disable (int channel
);
86 static int galbrg_set_clksrc (int channel
, int value
);
87 static int galbrg_set_CUV (int channel
, int value
);
89 static void galsdma_enable_rx (void);
90 static int galsdma_set_mem_space (unsigned int memSpace
,
91 unsigned int memSpaceTarget
,
92 unsigned int memSpaceAttr
,
93 unsigned int baseAddress
,
97 #define SOFTWARE_CACHE_MANAGEMENT
99 #ifdef SOFTWARE_CACHE_MANAGEMENT
100 #define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
101 #define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
102 #define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
104 #define FLUSH_DCACHE(a,b)
105 #define FLUSH_AND_INVALIDATE_DCACHE(a,b)
106 #define INVALIDATE_DCACHE(a,b)
109 #ifdef CONFIG_MPSC_DEBUG_PORT
110 static void mpsc_debug_init (void)
113 volatile unsigned int temp
;
115 /* Clear the CFR (CHR4) */
116 /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
117 temp
= GTREGREAD (GALMPSC_CHANNELREG_4
+ (CHANNEL
* GALMPSC_indent
: Standard input
:229: Warning
:old style assignment ambiguity in
"=&". Assuming
"= &"
122 GT_REG_WRITE (GALMPSC_CHANNELREG_4
+ (CHANNEL
* GALMPSC_REG_GAP
),
125 /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
126 temp
= GTREGREAD (GALMPSC_CHANNELREG_5
+ (CHANNEL
* GALMPSC_REG_GAP
));
127 temp
|= (BIT12
| BIT15
);
128 GT_REG_WRITE (GALMPSC_CHANNELREG_5
+ (CHANNEL
* GALMPSC_REG_GAP
),
132 temp
= GTREGREAD (GALMPSC_0_INT_MASK
);
134 GT_REG_WRITE (GALMPSC_0_INT_MASK
, temp
);
138 char mpsc_getchar_debug (void)
141 volatile unsigned int cause
;
143 cause
= GTREGREAD (GALMPSC_0_INT_CAUSE
);
144 while ((cause
& BIT6
) == 0) {
145 cause
= GTREGREAD (GALMPSC_0_INT_CAUSE
);
148 temp
= GTREGREAD (GALMPSC_CHANNELREG_10
+
149 (CHANNEL
* GALMPSC_REG_GAP
));
150 /* By writing 1's to the set bits, the register is cleared */
151 GT_REG_WRITE (GALMPSC_CHANNELREG_10
+ (CHANNEL
* GALMPSC_REG_GAP
),
153 GT_REG_WRITE (GALMPSC_0_INT_CAUSE
, cause
& ~BIT6
);
154 return (temp
>> 16) & 0xff;
157 /* special function for running out of flash. doesn't modify any
158 * global variables [josh] */
159 int mpsc_putchar_early (char ch
)
161 DECLARE_GLOBAL_DATA_PTR
;
164 GTREGREAD (GALMPSC_CHANNELREG_2
+ (mpsc
* GALMPSC_REG_GAP
));
165 galmpsc_set_tcschar (mpsc
, ch
);
166 GT_REG_WRITE (GALMPSC_CHANNELREG_2
+ (mpsc
* GALMPSC_REG_GAP
),
169 #define MAGIC_FACTOR (10*1000000)
171 udelay (MAGIC_FACTOR
/ gd
->baudrate
);
175 /* This is used after relocation, see serial.c and mpsc_init2 */
176 static int mpsc_putchar_sdma (char ch
)
178 volatile unsigned int *p
;
182 /* align the descriptor */
184 memset ((void *) p
, 0, 8 * sizeof (unsigned int));
186 /* fill one 64 bit buffer */
187 /* word swap, pad with 0 */
189 p
[5] = (unsigned int) ch
; /* x */
191 /* CHANGED completely according to GT64260A dox - NTL */
192 p
[0] = 0x00010001; /* 0 */
193 p
[1] = DESC_OWNER_BIT
| DESC_FIRST
| DESC_LAST
; /* 4 */
195 p
[3] = (unsigned int) &p
[4]; /* c */
198 p
[9] = DESC_FIRST
| DESC_LAST
;
199 p
[10] = (unsigned int) &p
[0];
200 p
[11] = (unsigned int) &p
[12];
203 FLUSH_DCACHE (&p
[0], &p
[8]);
205 GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR
+ (CHANNEL
* GALSDMA_REG_DIFF
),
206 (unsigned int) &p
[0]);
207 GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR
+ (CHANNEL
* GALSDMA_REG_DIFF
),
208 (unsigned int) &p
[0]);
210 temp
= GTREGREAD (GALSDMA_0_COM_REG
+ (CHANNEL
* GALSDMA_REG_DIFF
));
211 temp
|= (TX_DEMAND
| TX_STOP
);
212 GT_REG_WRITE (GALSDMA_0_COM_REG
+ (CHANNEL
* GALSDMA_REG_DIFF
), temp
);
214 INVALIDATE_DCACHE (&p
[1], &p
[2]);
216 while (p
[1] & DESC_OWNER_BIT
) {
218 INVALIDATE_DCACHE (&p
[1], &p
[2]);
223 char mpsc_getchar_sdma (void)
225 static unsigned int done
= 0;
227 unsigned int len
= 0, idx
= 0, temp
;
229 volatile unsigned int *p
;
233 p
= &rx_desc_base
[rx_desc_index
* 8];
235 INVALIDATE_DCACHE (&p
[0], &p
[1]);
236 /* Wait for character */
237 while (p
[1] & DESC_OWNER_BIT
) {
239 INVALIDATE_DCACHE (&p
[0], &p
[1]);
242 /* Handle error case */
243 if (p
[1] & (1 << 15)) {
244 printf ("oops, error: %08x\n", p
[1]);
246 temp
= GTREGREAD (GALMPSC_CHANNELREG_2
+
247 (CHANNEL
* GALMPSC_REG_GAP
));
249 GT_REG_WRITE (GALMPSC_CHANNELREG_2
+
250 (CHANNEL
* GALMPSC_REG_GAP
), temp
);
252 /* Can't poll on abort bit, so we just wait. */
255 galsdma_enable_rx ();
258 /* Number of bytes left in this descriptor */
271 INVALIDATE_DCACHE (&p
[idx
], &p
[idx
+ 1]);
277 /* this descriptor has more bytes still
278 * shift down the char we just read, and leave the
279 * buffer in place for the next time around
281 p
[idx
] = p
[idx
] >> 8;
282 FLUSH_DCACHE (&p
[idx
], &p
[idx
+ 1]);
286 /* nothing left in this descriptor.
289 p
[1] = DESC_OWNER_BIT
| DESC_FIRST
| DESC_LAST
;
291 FLUSH_DCACHE (&p
[0], &p
[1]);
292 /* Next descriptor */
293 rx_desc_index
= (rx_desc_index
+ 1) % RX_DESC
;
296 } while (len
== 0); /* galileo bug.. len might be zero */
302 int mpsc_test_char_debug (void)
304 if ((GTREGREAD (GALMPSC_0_INT_CAUSE
) & BIT6
) == 0)
312 int mpsc_test_char_sdma (void)
314 volatile unsigned int *p
= &rx_desc_base
[rx_desc_index
* 8];
316 INVALIDATE_DCACHE (&p
[1], &p
[2]);
318 if (p
[1] & DESC_OWNER_BIT
)
324 int mpsc_init (int baud
)
327 galbrg_set_baudrate (CHANNEL
, baud
);
328 galbrg_set_clksrc (CHANNEL
, 8); /* set source=Tclk */
329 galbrg_set_CUV (CHANNEL
, 0); /* set up CountUpValue */
330 galbrg_enable (CHANNEL
); /* Enable BRG */
332 /* Set up clock routing */
333 galmpsc_connect (CHANNEL
, GALMPSC_CONNECT
); /* connect it */
335 galmpsc_route_rx_clock (CHANNEL
, CHANNEL
); /* chosse BRG0 for Rx */
336 galmpsc_route_tx_clock (CHANNEL
, CHANNEL
); /* chose BRG0 for Tx */
338 /* reset MPSC state */
339 galmpsc_shutdown (CHANNEL
);
342 galsdma_set_burstsize (CHANNEL
, L1_CACHE_BYTES
/ 8); /* in 64 bit words (8 bytes) */
343 galsdma_set_txle (CHANNEL
);
344 galsdma_set_rxle (CHANNEL
);
345 galsdma_set_RC (CHANNEL
, 0xf);
346 galsdma_set_SFM (CHANNEL
);
347 galsdma_set_RFT (CHANNEL
);
350 galmpsc_write_config_regs (CHANNEL
, GALMPSC_UART
);
351 galmpsc_config_channel_regs (CHANNEL
);
352 galmpsc_set_char_length (CHANNEL
, GALMPSC_CHAR_LENGTH_8
); /* 8 */
353 galmpsc_set_parity (CHANNEL
, GALMPSC_PARITY_NONE
); /* N */
354 galmpsc_set_stop_bit_length (CHANNEL
, GALMPSC_STOP_BITS_1
); /* 1 */
356 #ifdef CONFIG_MPSC_DEBUG_PORT
360 /* COMM_MPSC CONFIG */
361 #ifdef SOFTWARE_CACHE_MANAGEMENT
362 galmpsc_set_snoop (CHANNEL
, 0); /* disable snoop */
364 galmpsc_set_snoop (CHANNEL
, 1); /* enable snoop */
371 void mpsc_sdma_init (void)
373 /* Setup SDMA channel0 SDMA_CONFIG_REG*/
374 GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
376 /* Enable MPSC-Window0 for DRAM Bank0 */
377 if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT
,
378 MV64460_SDMA_DRAM_CS_0_TARGET
,
380 memoryGetBankBaseAddress
381 (CS_0_LOW_DECODE_ADDRESS
),
382 memoryGetBankSize (BANK0
)) != true)
383 printf ("%s: SDMA_Window0 memory setup failed !!! \n",
387 /* Disable MPSC-Window1 */
388 if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_1_BIT
,
389 MV64460_SDMA_DRAM_CS_0_TARGET
,
391 memoryGetBankBaseAddress
392 (CS_1_LOW_DECODE_ADDRESS
),
393 memoryGetBankSize (BANK3
)) != true)
394 printf ("%s: SDMA_Window1 memory setup failed !!! \n",
398 /* Disable MPSC-Window2 */
399 if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_2_BIT
,
400 MV64460_SDMA_DRAM_CS_0_TARGET
,
402 memoryGetBankBaseAddress
403 (CS_2_LOW_DECODE_ADDRESS
),
404 memoryGetBankSize (BANK3
)) != true)
405 printf ("%s: SDMA_Window2 memory setup failed !!! \n",
409 /* Disable MPSC-Window3 */
410 if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_3_BIT
,
411 MV64460_SDMA_DRAM_CS_0_TARGET
,
413 memoryGetBankBaseAddress
414 (CS_3_LOW_DECODE_ADDRESS
),
415 memoryGetBankSize (BANK3
)) != true)
416 printf ("%s: SDMA_Window3 memory setup failed !!! \n",
419 /* Setup MPSC0 access mode Window0 full access */
420 GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG
,
421 (MV64460_SDMA_WIN_ACCESS_FULL
<<
422 (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT
* 2)));
424 /* Setup MPSC1 access mode Window1 full access */
425 GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG
,
426 (MV64460_SDMA_WIN_ACCESS_FULL
<<
427 (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT
* 2)));
429 /* Setup MPSC internal address space base address */
430 GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG
, CFG_GT_REGS
);
432 /* no high address remap*/
433 GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0
, 0x00);
434 GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1
, 0x00);
436 /* clear interrupt cause register for MPSC (fault register)*/
437 GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG
, 0x00);
441 void mpsc_init2 (void)
445 #ifndef CONFIG_MPSC_DEBUG_PORT
446 mpsc_putchar
= mpsc_putchar_sdma
;
447 mpsc_getchar
= mpsc_getchar_sdma
;
448 mpsc_test_char
= mpsc_test_char_sdma
;
451 rx_desc_base
= (unsigned int *) malloc (((RX_DESC
+ 1) * 8) *
452 sizeof (unsigned int));
454 /* align descriptors */
455 rx_desc_base
= (unsigned int *)
456 (((unsigned int) rx_desc_base
+ 32) & 0xFFFFFFF0);
460 memset ((void *) rx_desc_base
, 0,
461 (RX_DESC
* 8) * sizeof (unsigned int));
463 for (i
= 0; i
< RX_DESC
; i
++) {
464 rx_desc_base
[i
* 8 + 3] = (unsigned int) &rx_desc_base
[i
* 8 + 4]; /* Buffer */
465 rx_desc_base
[i
* 8 + 2] = (unsigned int) &rx_desc_base
[(i
+ 1) * 8]; /* Next descriptor */
466 rx_desc_base
[i
* 8 + 1] = DESC_OWNER_BIT
| DESC_FIRST
| DESC_LAST
; /* Command & control */
467 rx_desc_base
[i
* 8] = 0x00100000;
469 rx_desc_base
[(i
- 1) * 8 + 2] = (unsigned int) &rx_desc_base
[0];
471 FLUSH_DCACHE (&rx_desc_base
[0], &rx_desc_base
[RX_DESC
* 8]);
472 GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR
+ (CHANNEL
* GALSDMA_REG_DIFF
),
473 (unsigned int) &rx_desc_base
[0]);
476 tx_desc_base
= (unsigned int *) malloc (((TX_DESC
+ 1) * 8) *
477 sizeof (unsigned int));
479 /* align descriptors */
480 tx_desc_base
= (unsigned int *)
481 (((unsigned int) tx_desc_base
+ 32) & 0xFFFFFFF0);
485 memset ((void *) tx_desc_base
, 0,
486 (TX_DESC
* 8) * sizeof (unsigned int));
488 for (i
= 0; i
< TX_DESC
; i
++) {
489 tx_desc_base
[i
* 8 + 5] = (unsigned int) 0x23232323;
490 tx_desc_base
[i
* 8 + 4] = (unsigned int) 0x23232323;
491 tx_desc_base
[i
* 8 + 3] =
492 (unsigned int) &tx_desc_base
[i
* 8 + 4];
493 tx_desc_base
[i
* 8 + 2] =
494 (unsigned int) &tx_desc_base
[(i
+ 1) * 8];
495 tx_desc_base
[i
* 8 + 1] =
496 DESC_OWNER_BIT
| DESC_FIRST
| DESC_LAST
;
498 /* set sbytecnt and shadow byte cnt to 1 */
499 tx_desc_base
[i
* 8] = 0x00010001;
501 tx_desc_base
[(i
- 1) * 8 + 2] = (unsigned int) &tx_desc_base
[0];
503 FLUSH_DCACHE (&tx_desc_base
[0], &tx_desc_base
[TX_DESC
* 8]);
507 galsdma_enable_rx ();
512 int galbrg_set_baudrate (int channel
, int rate
)
514 DECLARE_GLOBAL_DATA_PTR
;
517 galbrg_disable (channel
); /*ok */
521 clock
= (CFG_TCLK
/ (16 * rate
)) - 1;
523 clock
= (CFG_TCLK
/ (16 * rate
)) - 1;
526 galbrg_set_CDV (channel
, clock
); /* set timer Reg. for BRG */
528 galbrg_enable (channel
);
535 /* ------------------------------------------------------------------ */
537 /* Below are all the private functions that no one else needs */
539 static int galbrg_set_CDV (int channel
, int value
)
543 temp
= GTREGREAD (GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
));
545 temp
|= (value
& 0x0000FFFF);
546 GT_REG_WRITE (GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
), temp
);
551 static int galbrg_enable (int channel
)
555 temp
= GTREGREAD (GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
));
557 GT_REG_WRITE (GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
), temp
);
562 static int galbrg_disable (int channel
)
566 temp
= GTREGREAD (GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
));
568 GT_REG_WRITE (GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
), temp
);
573 static int galbrg_set_clksrc (int channel
, int value
)
577 temp
= GTREGREAD (GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
));
578 temp
&= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */
579 temp
|= (value
<< 18);
580 GT_REG_WRITE (GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
), temp
);
584 static int galbrg_set_CUV (int channel
, int value
)
586 /* set CountUpValue */
587 GT_REG_WRITE (GALBRG_0_BTREG
+ (channel
* GALBRG_REG_GAP
), value
);
593 static int galbrg_reset (int channel
)
597 temp
= GTREGREAD (GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
));
599 GT_REG_WRITE (GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
), temp
);
605 static int galsdma_set_RFT (int channel
)
609 temp
= GTREGREAD (GALSDMA_0_CONF_REG
+ (channel
* GALSDMA_REG_DIFF
));
611 GT_REG_WRITE (GALSDMA_0_CONF_REG
+ (channel
* GALSDMA_REG_DIFF
),
617 static int galsdma_set_SFM (int channel
)
621 temp
= GTREGREAD (GALSDMA_0_CONF_REG
+ (channel
* GALSDMA_REG_DIFF
));
623 GT_REG_WRITE (GALSDMA_0_CONF_REG
+ (channel
* GALSDMA_REG_DIFF
),
629 static int galsdma_set_rxle (int channel
)
633 temp
= GTREGREAD (GALSDMA_0_CONF_REG
+ (channel
* GALSDMA_REG_DIFF
));
635 GT_REG_WRITE (GALSDMA_0_CONF_REG
+ (channel
* GALSDMA_REG_DIFF
),
641 static int galsdma_set_txle (int channel
)
645 temp
= GTREGREAD (GALSDMA_0_CONF_REG
+ (channel
* GALSDMA_REG_DIFF
));
647 GT_REG_WRITE (GALSDMA_0_CONF_REG
+ (channel
* GALSDMA_REG_DIFF
),
653 static int galsdma_set_RC (int channel
, unsigned int value
)
657 temp
= GTREGREAD (GALSDMA_0_CONF_REG
+ (channel
* GALSDMA_REG_DIFF
));
659 temp
|= (value
<< 2);
660 GT_REG_WRITE (GALSDMA_0_CONF_REG
+ (channel
* GALSDMA_REG_DIFF
),
666 static int galsdma_set_burstsize (int channel
, unsigned int value
)
670 temp
= GTREGREAD (GALSDMA_0_CONF_REG
+ (channel
* GALSDMA_REG_DIFF
));
674 GT_REG_WRITE (GALSDMA_0_CONF_REG
+
675 (channel
* GALSDMA_REG_DIFF
),
676 (temp
| (0x3 << 12)));
680 GT_REG_WRITE (GALSDMA_0_CONF_REG
+
681 (channel
* GALSDMA_REG_DIFF
),
682 (temp
| (0x2 << 12)));
686 GT_REG_WRITE (GALSDMA_0_CONF_REG
+
687 (channel
* GALSDMA_REG_DIFF
),
688 (temp
| (0x1 << 12)));
692 GT_REG_WRITE (GALSDMA_0_CONF_REG
+
693 (channel
* GALSDMA_REG_DIFF
),
694 (temp
| (0x0 << 12)));
705 static int galmpsc_connect (int channel
, int connect
)
709 temp
= GTREGREAD (GALMPSC_ROUTING_REGISTER
);
711 if ((channel
== 0) && connect
)
713 else if ((channel
== 1) && connect
)
714 temp
&= ~(0x00000007 << 6);
715 else if ((channel
== 0) && !connect
)
718 temp
|= (0x00000007 << 6);
720 /* Just in case... */
723 GT_REG_WRITE (GALMPSC_ROUTING_REGISTER
, temp
);
728 static int galmpsc_route_rx_clock (int channel
, int brg
)
732 temp
= GTREGREAD (GALMPSC_RxC_ROUTE
);
742 GT_REG_WRITE (GALMPSC_RxC_ROUTE
, temp
);
747 static int galmpsc_route_tx_clock (int channel
, int brg
)
751 temp
= GTREGREAD (GALMPSC_TxC_ROUTE
);
761 GT_REG_WRITE (GALMPSC_TxC_ROUTE
, temp
);
766 static int galmpsc_write_config_regs (int mpsc
, int mode
)
768 if (mode
== GALMPSC_UART
) {
769 /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
770 GT_REG_WRITE (GALMPSC_MCONF_LOW
+ (mpsc
* GALMPSC_REG_GAP
),
773 /* Main config reg High (32x Rx/Tx clock mode, width=8bits */
774 GT_REG_WRITE (GALMPSC_MCONF_HIGH
+ (mpsc
* GALMPSC_REG_GAP
),
778 /* 0000 0010 0000 0000 */
781 /* 0000 0011 1111 1000 */
788 static int galmpsc_config_channel_regs (int mpsc
)
790 GT_REG_WRITE (GALMPSC_CHANNELREG_1
+ (mpsc
* GALMPSC_REG_GAP
), 0);
791 GT_REG_WRITE (GALMPSC_CHANNELREG_2
+ (mpsc
* GALMPSC_REG_GAP
), 0);
792 GT_REG_WRITE (GALMPSC_CHANNELREG_3
+ (mpsc
* GALMPSC_REG_GAP
), 1);
793 GT_REG_WRITE (GALMPSC_CHANNELREG_4
+ (mpsc
* GALMPSC_REG_GAP
), 0);
794 GT_REG_WRITE (GALMPSC_CHANNELREG_5
+ (mpsc
* GALMPSC_REG_GAP
), 0);
795 GT_REG_WRITE (GALMPSC_CHANNELREG_6
+ (mpsc
* GALMPSC_REG_GAP
), 0);
796 GT_REG_WRITE (GALMPSC_CHANNELREG_7
+ (mpsc
* GALMPSC_REG_GAP
), 0);
797 GT_REG_WRITE (GALMPSC_CHANNELREG_8
+ (mpsc
* GALMPSC_REG_GAP
), 0);
798 GT_REG_WRITE (GALMPSC_CHANNELREG_9
+ (mpsc
* GALMPSC_REG_GAP
), 0);
799 GT_REG_WRITE (GALMPSC_CHANNELREG_10
+ (mpsc
* GALMPSC_REG_GAP
), 0);
801 galmpsc_set_brkcnt (mpsc
, 0x3);
802 galmpsc_set_tcschar (mpsc
, 0xab);
807 static int galmpsc_set_brkcnt (int mpsc
, int value
)
811 temp
= GTREGREAD (GALMPSC_CHANNELREG_1
+ (mpsc
* GALMPSC_REG_GAP
));
813 temp
|= (value
<< 16);
814 GT_REG_WRITE (GALMPSC_CHANNELREG_1
+ (mpsc
* GALMPSC_REG_GAP
), temp
);
819 static int galmpsc_set_tcschar (int mpsc
, int value
)
823 temp
= GTREGREAD (GALMPSC_CHANNELREG_1
+ (mpsc
* GALMPSC_REG_GAP
));
826 GT_REG_WRITE (GALMPSC_CHANNELREG_1
+ (mpsc
* GALMPSC_REG_GAP
), temp
);
831 static int galmpsc_set_char_length (int mpsc
, int value
)
835 temp
= GTREGREAD (GALMPSC_PROTOCONF_REG
+ (mpsc
* GALMPSC_REG_GAP
));
837 temp
|= (value
<< 12);
838 GT_REG_WRITE (GALMPSC_PROTOCONF_REG
+ (mpsc
* GALMPSC_REG_GAP
), temp
);
843 static int galmpsc_set_stop_bit_length (int mpsc
, int value
)
847 temp
= GTREGREAD (GALMPSC_PROTOCONF_REG
+ (mpsc
* GALMPSC_REG_GAP
));
849 temp
|= (value
<< 14);
850 GT_REG_WRITE (GALMPSC_PROTOCONF_REG
+ (mpsc
* GALMPSC_REG_GAP
), temp
);
855 static int galmpsc_set_parity (int mpsc
, int value
)
859 temp
= GTREGREAD (GALMPSC_CHANNELREG_2
+ (mpsc
* GALMPSC_REG_GAP
));
862 temp
|= ((value
<< 18) | (value
<< 2));
863 temp
|= ((value
<< 17) | (value
<< 1));
868 GT_REG_WRITE (GALMPSC_CHANNELREG_2
+ (mpsc
* GALMPSC_REG_GAP
), temp
);
873 static int galmpsc_enter_hunt (int mpsc
)
877 temp
= GTREGREAD (GALMPSC_CHANNELREG_2
+ (mpsc
* GALMPSC_REG_GAP
));
879 GT_REG_WRITE (GALMPSC_CHANNELREG_2
+ (mpsc
* GALMPSC_REG_GAP
), temp
);
881 while (GTREGREAD (GALMPSC_CHANNELREG_2
+ (mpsc
* GALMPSC_REG_GAP
)) &
889 static int galmpsc_shutdown (int mpsc
)
893 /* cause RX abort (clears RX) */
894 temp
= GTREGREAD (GALMPSC_CHANNELREG_2
+ (mpsc
* GALMPSC_REG_GAP
));
895 temp
|= MPSC_RX_ABORT
| MPSC_TX_ABORT
;
896 temp
&= ~MPSC_ENTER_HUNT
;
897 GT_REG_WRITE (GALMPSC_CHANNELREG_2
+ (mpsc
* GALMPSC_REG_GAP
), temp
);
899 GT_REG_WRITE (GALSDMA_0_COM_REG
, 0);
900 GT_REG_WRITE (GALSDMA_0_COM_REG
, SDMA_TX_ABORT
| SDMA_RX_ABORT
);
902 /* shut down the MPSC */
903 GT_REG_WRITE (GALMPSC_MCONF_LOW
, 0);
904 GT_REG_WRITE (GALMPSC_MCONF_HIGH
, 0);
905 GT_REG_WRITE (GALMPSC_PROTOCONF_REG
+ (mpsc
* GALMPSC_REG_GAP
), 0);
909 /* shut down the sdma engines. */
910 /* reset config to default */
911 GT_REG_WRITE (GALSDMA_0_CONF_REG
, 0x000000fc);
915 /* clear the SDMA current and first TX and RX pointers */
916 GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR
, 0);
917 GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR
, 0);
918 GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR
, 0);
925 static void galsdma_enable_rx (void)
929 /* Enable RX processing */
930 temp
= GTREGREAD (GALSDMA_0_COM_REG
+ (CHANNEL
* GALSDMA_REG_DIFF
));
932 GT_REG_WRITE (GALSDMA_0_COM_REG
+ (CHANNEL
* GALSDMA_REG_DIFF
), temp
);
934 galmpsc_enter_hunt (CHANNEL
);
937 static int galmpsc_set_snoop (int mpsc
, int value
)
940 mpsc
? MPSC_1_ADDRESS_CONTROL_LOW
:
941 MPSC_0_ADDRESS_CONTROL_LOW
;
942 int temp
= GTREGREAD (reg
);
945 temp
|= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
947 temp
&= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
948 GT_REG_WRITE (reg
, temp
);
952 /*******************************************************************************
953 * galsdma_set_mem_space - Set MV64460 IDMA memory decoding map.
956 * the MV64460 SDMA has its own address decoding map that is de-coupled
957 * from the CPU interface address decoding windows. The SDMA channels
958 * share four address windows. Each region can be individually configured
959 * by this function by associating it to a target interface and setting
960 * base and size values.
963 * The size must be in 64Kbyte granularity.
964 * The base address must be aligned to the size.
965 * The size must be a series of 1s followed by a series of zeros
971 * True for success, false otherwise.
973 *******************************************************************************/
975 static int galsdma_set_mem_space (unsigned int memSpace
,
976 unsigned int memSpaceTarget
,
977 unsigned int memSpaceAttr
,
978 unsigned int baseAddress
, unsigned int size
)
983 GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG
,
988 /* The base address must be aligned to the size. */
989 if (baseAddress
% size
!= 0) {
992 if (size
< 0x10000) {
996 /* Align size and base to 64K */
997 baseAddress
&= 0xffff0000;
1001 /* Checking that the size is a sequence of '1' followed by a
1002 sequence of '0' starting from LSB to MSB. */
1003 while ((temp
> 0) && (temp
& 0x1)) {
1008 GT_REG_WRITE (MV64460_CUNIT_BASE_ADDR_REG0
+ memSpace
* 8,
1009 (baseAddress
| memSpaceTarget
| memSpaceAttr
));
1010 GT_REG_WRITE ((MV64460_CUNIT_SIZE0
+ memSpace
* 8),
1011 (size
- 1) & 0xffff0000);
1012 GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG
,
1015 /* An invalid size was specified */