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1 /*
2 * (C) Copyright 2003
3 * Ingo Assmus <ingo.assmus@keymile.com>
4 *
5 * based on - Driver for MV64460X ethernet ports
6 * Copyright (C) 2002 rabeeh@galileo.co.il
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27 /*
28 * mv_eth.c - header file for the polled mode GT ethernet driver
29 */
30 #include <common.h>
31 #include <net.h>
32 #include <malloc.h>
33
34 #include "mv_eth.h"
35
36 /* enable Debug outputs */
37
38 #undef DEBUG_MV_ETH
39
40 #ifdef DEBUG_MV_ETH
41 #define DEBUG
42 #define DP(x) x
43 #else
44 #define DP(x)
45 #endif
46
47 #undef MV64460_CHECKSUM_OFFLOAD
48 /*************************************************************************
49 **************************************************************************
50 **************************************************************************
51 * The first part is the high level driver of the gigE ethernet ports. *
52 **************************************************************************
53 **************************************************************************
54 *************************************************************************/
55
56 /* Definition for configuring driver */
57 /* #define UPDATE_STATS_BY_SOFTWARE */
58 #undef MV64460_RX_QUEUE_FILL_ON_TASK
59
60
61 /* Constants */
62 #define MAGIC_ETH_RUNNING 8031971
63 #define MV64460_INTERNAL_SRAM_SIZE _256K
64 #define EXTRA_BYTES 32
65 #define WRAP ETH_HLEN + 2 + 4 + 16
66 #define BUFFER_MTU dev->mtu + WRAP
67 #define INT_CAUSE_UNMASK_ALL 0x0007ffff
68 #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
69 #ifdef MV64460_RX_FILL_ON_TASK
70 #define INT_CAUSE_MASK_ALL 0x00000000
71 #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
72 #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
73 #endif
74
75 /* Read/Write to/from MV64460 internal registers */
76 #define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
77 #define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
78 #define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
79 #define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
80
81 /* Static function declarations */
82 static int mv64460_eth_real_open (struct eth_device *eth);
83 static int mv64460_eth_real_stop (struct eth_device *eth);
84 static struct net_device_stats *mv64460_eth_get_stats (struct eth_device
85 *dev);
86 static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
87 static void mv64460_eth_update_stat (struct eth_device *dev);
88 bool db64460_eth_start (struct eth_device *eth);
89 unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
90 unsigned int mib_offset);
91 int mv64460_eth_receive (struct eth_device *dev);
92
93 int mv64460_eth_xmit (struct eth_device *, volatile void *packet, int length);
94
95 #ifndef UPDATE_STATS_BY_SOFTWARE
96 static void mv64460_eth_print_stat (struct eth_device *dev);
97 #endif
98 /* Processes a received packet */
99 extern void NetReceive (volatile uchar *, int);
100
101 extern unsigned int INTERNAL_REG_BASE_ADDR;
102
103 /*************************************************
104 *Helper functions - used inside the driver only *
105 *************************************************/
106 #ifdef DEBUG_MV_ETH
107 void print_globals (struct eth_device *dev)
108 {
109 printf ("Ethernet PRINT_Globals-Debug function\n");
110 printf ("Base Address for ETH_PORT_INFO: %08x\n",
111 (unsigned int) dev->priv);
112 printf ("Base Address for mv64460_eth_priv: %08x\n",
113 (unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
114 port_private));
115
116 printf ("GT Internal Base Address: %08x\n",
117 INTERNAL_REG_BASE_ADDR);
118 printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64460_TX_QUEUE_SIZE);
119 printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64460_RX_QUEUE_SIZE);
120 printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n",
121 (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
122 p_rx_buffer_base[0],
123 (MV64460_RX_QUEUE_SIZE * MV64460_RX_BUFFER_SIZE) + 32);
124 printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n",
125 (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
126 p_tx_buffer_base[0],
127 (MV64460_TX_QUEUE_SIZE * MV64460_TX_BUFFER_SIZE) + 32);
128 }
129 #endif
130
131 #define my_cpu_to_le32(x) my_le32_to_cpu((x))
132
133 unsigned long my_le32_to_cpu (unsigned long x)
134 {
135 return (((x & 0x000000ffU) << 24) |
136 ((x & 0x0000ff00U) << 8) |
137 ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
138 }
139
140
141 /**********************************************************************
142 * mv64460_eth_print_phy_status
143 *
144 * Prints gigabit ethenret phy status
145 *
146 * Input : pointer to ethernet interface network device structure
147 * Output : N/A
148 **********************************************************************/
149
150 static void mv64460_eth_print_phy_status (struct eth_device *dev)
151 {
152 struct mv64460_eth_priv *port_private;
153 unsigned int port_num;
154 ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
155 unsigned int port_status, phy_reg_data;
156
157 port_private =
158 (struct mv64460_eth_priv *) ethernet_private->port_private;
159 port_num = port_private->port_num;
160
161 /* Check Link status on phy */
162 eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
163 if (!(phy_reg_data & 0x20)) {
164 printf ("Ethernet port changed link status to DOWN\n");
165 } else {
166 port_status =
167 MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
168 printf ("Ethernet status port %d: Link up", port_num);
169 printf (", %s",
170 (port_status & BIT2) ? "Full Duplex" : "Half Duplex");
171 if (port_status & BIT4)
172 printf (", Speed 1 Gbps");
173 else
174 printf (", %s",
175 (port_status & BIT5) ? "Speed 100 Mbps" :
176 "Speed 10 Mbps");
177 printf ("\n");
178 }
179 }
180
181 /**********************************************************************
182 * u-boot entry functions for mv64460_eth
183 *
184 **********************************************************************/
185 int db64460_eth_probe (struct eth_device *dev)
186 {
187 return ((int) db64460_eth_start (dev));
188 }
189
190 int db64460_eth_poll (struct eth_device *dev)
191 {
192 return mv64460_eth_receive (dev);
193 }
194
195 int db64460_eth_transmit (struct eth_device *dev, volatile void *packet,
196 int length)
197 {
198 mv64460_eth_xmit (dev, packet, length);
199 return 0;
200 }
201
202 void db64460_eth_disable (struct eth_device *dev)
203 {
204 mv64460_eth_stop (dev);
205 }
206
207
208 void mv6446x_eth_initialize (bd_t * bis)
209 {
210 struct eth_device *dev;
211 ETH_PORT_INFO *ethernet_private;
212 struct mv64460_eth_priv *port_private;
213 int devnum, x, temp;
214 char *s, *e, buf[64];
215
216 for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
217 dev = calloc (sizeof (*dev), 1);
218 if (!dev) {
219 printf ("%s: mv_enet%d allocation failure, %s\n",
220 __FUNCTION__, devnum, "eth_device structure");
221 return;
222 }
223
224 /* must be less than NAMESIZE (16) */
225 sprintf (dev->name, "mv_enet%d", devnum);
226
227 #ifdef DEBUG
228 printf ("Initializing %s\n", dev->name);
229 #endif
230
231 /* Extract the MAC address from the environment */
232 switch (devnum) {
233 case 0:
234 s = "ethaddr";
235 break;
236
237 case 1:
238 s = "eth1addr";
239 break;
240
241 case 2:
242 s = "eth2addr";
243 break;
244
245 default: /* this should never happen */
246 printf ("%s: Invalid device number %d\n",
247 __FUNCTION__, devnum);
248 return;
249 }
250
251 temp = getenv_r (s, buf, sizeof (buf));
252 s = (temp > 0) ? buf : NULL;
253
254 #ifdef DEBUG
255 printf ("Setting MAC %d to %s\n", devnum, s);
256 #endif
257 for (x = 0; x < 6; ++x) {
258 dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
259 if (s)
260 s = (*e) ? e + 1 : e;
261 }
262 /* ronen - set the MAC addr in the HW */
263 eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
264
265 dev->init = (void *) db64460_eth_probe;
266 dev->halt = (void *) ethernet_phy_reset;
267 dev->send = (void *) db64460_eth_transmit;
268 dev->recv = (void *) db64460_eth_poll;
269
270 ethernet_private = calloc (sizeof (*ethernet_private), 1);
271 dev->priv = (void *)ethernet_private;
272 if (!ethernet_private) {
273 printf ("%s: %s allocation failure, %s\n",
274 __FUNCTION__, dev->name,
275 "Private Device Structure");
276 free (dev);
277 return;
278 }
279 /* start with an zeroed ETH_PORT_INFO */
280 memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
281 memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
282
283 /* set pointer to memory for stats data structure etc... */
284 port_private = calloc (sizeof (*ethernet_private), 1);
285 ethernet_private->port_private = (void *)port_private;
286 if (!port_private) {
287 printf ("%s: %s allocation failure, %s\n",
288 __FUNCTION__, dev->name,
289 "Port Private Device Structure");
290
291 free (ethernet_private);
292 free (dev);
293 return;
294 }
295
296 port_private->stats =
297 calloc (sizeof (struct net_device_stats), 1);
298 if (!port_private->stats) {
299 printf ("%s: %s allocation failure, %s\n",
300 __FUNCTION__, dev->name,
301 "Net stat Structure");
302
303 free (port_private);
304 free (ethernet_private);
305 free (dev);
306 return;
307 }
308 memset (ethernet_private->port_private, 0,
309 sizeof (struct mv64460_eth_priv));
310 switch (devnum) {
311 case 0:
312 ethernet_private->port_num = ETH_0;
313 break;
314 case 1:
315 ethernet_private->port_num = ETH_1;
316 break;
317 case 2:
318 ethernet_private->port_num = ETH_2;
319 break;
320 default:
321 printf ("Invalid device number %d\n", devnum);
322 break;
323 };
324
325 port_private->port_num = devnum;
326 /*
327 * Read MIB counter on the GT in order to reset them,
328 * then zero all the stats fields in memory
329 */
330 mv64460_eth_update_stat (dev);
331 memset (port_private->stats, 0,
332 sizeof (struct net_device_stats));
333 /* Extract the MAC address from the environment */
334 switch (devnum) {
335 case 0:
336 s = "ethaddr";
337 break;
338
339 case 1:
340 s = "eth1addr";
341 break;
342
343 case 2:
344 s = "eth2addr";
345 break;
346
347 default: /* this should never happen */
348 printf ("%s: Invalid device number %d\n",
349 __FUNCTION__, devnum);
350 return;
351 }
352
353 temp = getenv_r (s, buf, sizeof (buf));
354 s = (temp > 0) ? buf : NULL;
355
356 #ifdef DEBUG
357 printf ("Setting MAC %d to %s\n", devnum, s);
358 #endif
359 for (x = 0; x < 6; ++x) {
360 dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
361 if (s)
362 s = (*e) ? e + 1 : e;
363 }
364
365 DP (printf ("Allocating descriptor and buffer rings\n"));
366
367 ethernet_private->p_rx_desc_area_base[0] =
368 (ETH_RX_DESC *) memalign (16,
369 RX_DESC_ALIGNED_SIZE *
370 MV64460_RX_QUEUE_SIZE + 1);
371 ethernet_private->p_tx_desc_area_base[0] =
372 (ETH_TX_DESC *) memalign (16,
373 TX_DESC_ALIGNED_SIZE *
374 MV64460_TX_QUEUE_SIZE + 1);
375
376 ethernet_private->p_rx_buffer_base[0] =
377 (char *) memalign (16,
378 MV64460_RX_QUEUE_SIZE *
379 MV64460_TX_BUFFER_SIZE + 1);
380 ethernet_private->p_tx_buffer_base[0] =
381 (char *) memalign (16,
382 MV64460_RX_QUEUE_SIZE *
383 MV64460_TX_BUFFER_SIZE + 1);
384
385 #ifdef DEBUG_MV_ETH
386 /* DEBUG OUTPUT prints adresses of globals */
387 print_globals (dev);
388 #endif
389 eth_register (dev);
390
391 }
392 DP (printf ("%s: exit\n", __FUNCTION__));
393
394 }
395
396 /**********************************************************************
397 * mv64460_eth_open
398 *
399 * This function is called when openning the network device. The function
400 * should initialize all the hardware, initialize cyclic Rx/Tx
401 * descriptors chain and buffers and allocate an IRQ to the network
402 * device.
403 *
404 * Input : a pointer to the network device structure
405 * / / ronen - changed the output to match net/eth.c needs
406 * Output : nonzero of success , zero if fails.
407 * under construction
408 **********************************************************************/
409
410 int mv64460_eth_open (struct eth_device *dev)
411 {
412 return (mv64460_eth_real_open (dev));
413 }
414
415 /* Helper function for mv64460_eth_open */
416 static int mv64460_eth_real_open (struct eth_device *dev)
417 {
418
419 unsigned int queue;
420 ETH_PORT_INFO *ethernet_private;
421 struct mv64460_eth_priv *port_private;
422 unsigned int port_num;
423 u32 port_status, phy_reg_data;
424
425 ethernet_private = (ETH_PORT_INFO *) dev->priv;
426 /* ronen - when we update the MAC env params we only update dev->enetaddr
427 see ./net/eth.c eth_set_enetaddr() */
428 memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
429
430 port_private =
431 (struct mv64460_eth_priv *) ethernet_private->port_private;
432 port_num = port_private->port_num;
433
434 /* Stop RX Queues */
435 MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
436 0x0000ff00);
437
438 /* Clear the ethernet port interrupts */
439 MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
440 MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
441
442 /* Unmask RX buffer and TX end interrupt */
443 MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num),
444 INT_CAUSE_UNMASK_ALL);
445
446 /* Unmask phy and link status changes interrupts */
447 MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
448 INT_CAUSE_UNMASK_ALL_EXT);
449
450 /* Set phy address of the port */
451 ethernet_private->port_phy_addr = 0x8 + port_num;
452
453 /* Activate the DMA channels etc */
454 eth_port_init (ethernet_private);
455
456
457 /* "Allocate" setup TX rings */
458
459 for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
460 unsigned int size;
461
462 port_private->tx_ring_size[queue] = MV64460_TX_QUEUE_SIZE;
463 size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */
464 ethernet_private->tx_desc_area_size[queue] = size;
465
466 /* first clear desc area completely */
467 memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
468 0, ethernet_private->tx_desc_area_size[queue]);
469
470 /* initialize tx desc ring with low level driver */
471 if (ether_init_tx_desc_ring
472 (ethernet_private, ETH_Q0,
473 port_private->tx_ring_size[queue],
474 MV64460_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
475 (unsigned int) ethernet_private->
476 p_tx_desc_area_base[queue],
477 (unsigned int) ethernet_private->
478 p_tx_buffer_base[queue]) == false)
479 printf ("### Error initializing TX Ring\n");
480 }
481
482 /* "Allocate" setup RX rings */
483 for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
484 unsigned int size;
485
486 /* Meantime RX Ring are fixed - but must be configurable by user */
487 port_private->rx_ring_size[queue] = MV64460_RX_QUEUE_SIZE;
488 size = (port_private->rx_ring_size[queue] *
489 RX_DESC_ALIGNED_SIZE);
490 ethernet_private->rx_desc_area_size[queue] = size;
491
492 /* first clear desc area completely */
493 memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
494 0, ethernet_private->rx_desc_area_size[queue]);
495 if ((ether_init_rx_desc_ring
496 (ethernet_private, ETH_Q0,
497 port_private->rx_ring_size[queue],
498 MV64460_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
499 (unsigned int) ethernet_private->
500 p_rx_desc_area_base[queue],
501 (unsigned int) ethernet_private->
502 p_rx_buffer_base[queue])) == false)
503 printf ("### Error initializing RX Ring\n");
504 }
505
506 eth_port_start (ethernet_private);
507
508 /* Set maximum receive buffer to 9700 bytes */
509 MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num),
510 (0x5 << 17) |
511 (MV_REG_READ
512 (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num))
513 & 0xfff1ffff));
514
515 /*
516 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
517 * disable the leaky bucket mechanism .
518 */
519
520 MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
521 port_status = MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
522
523 /* Check Link status on phy */
524 eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
525 if (!(phy_reg_data & 0x20)) {
526 /* Reset PHY */
527 if ((ethernet_phy_reset (port_num)) != true) {
528 printf ("$$ Warnning: No link on port %d \n",
529 port_num);
530 return 0;
531 } else {
532 eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
533 if (!(phy_reg_data & 0x20)) {
534 printf ("### Error: Phy is not active\n");
535 return 0;
536 }
537 }
538 } else {
539 mv64460_eth_print_phy_status (dev);
540 }
541 port_private->eth_running = MAGIC_ETH_RUNNING;
542 return 1;
543 }
544
545
546 static int mv64460_eth_free_tx_rings (struct eth_device *dev)
547 {
548 unsigned int queue;
549 ETH_PORT_INFO *ethernet_private;
550 struct mv64460_eth_priv *port_private;
551 unsigned int port_num;
552 volatile ETH_TX_DESC *p_tx_curr_desc;
553
554 ethernet_private = (ETH_PORT_INFO *) dev->priv;
555 port_private =
556 (struct mv64460_eth_priv *) ethernet_private->port_private;
557 port_num = port_private->port_num;
558
559 /* Stop Tx Queues */
560 MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
561 0x0000ff00);
562
563 /* Free TX rings */
564 DP (printf ("Clearing previously allocated TX queues... "));
565 for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
566 /* Free on TX rings */
567 for (p_tx_curr_desc =
568 ethernet_private->p_tx_desc_area_base[queue];
569 ((unsigned int) p_tx_curr_desc <= (unsigned int)
570 ethernet_private->p_tx_desc_area_base[queue] +
571 ethernet_private->tx_desc_area_size[queue]);
572 p_tx_curr_desc =
573 (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
574 TX_DESC_ALIGNED_SIZE)) {
575 /* this is inside for loop */
576 if (p_tx_curr_desc->return_info != 0) {
577 p_tx_curr_desc->return_info = 0;
578 DP (printf ("freed\n"));
579 }
580 }
581 DP (printf ("Done\n"));
582 }
583 return 0;
584 }
585
586 static int mv64460_eth_free_rx_rings (struct eth_device *dev)
587 {
588 unsigned int queue;
589 ETH_PORT_INFO *ethernet_private;
590 struct mv64460_eth_priv *port_private;
591 unsigned int port_num;
592 volatile ETH_RX_DESC *p_rx_curr_desc;
593
594 ethernet_private = (ETH_PORT_INFO *) dev->priv;
595 port_private =
596 (struct mv64460_eth_priv *) ethernet_private->port_private;
597 port_num = port_private->port_num;
598
599
600 /* Stop RX Queues */
601 MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
602 0x0000ff00);
603
604 /* Free RX rings */
605 DP (printf ("Clearing previously allocated RX queues... "));
606 for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
607 /* Free preallocated skb's on RX rings */
608 for (p_rx_curr_desc =
609 ethernet_private->p_rx_desc_area_base[queue];
610 (((unsigned int) p_rx_curr_desc <
611 ((unsigned int) ethernet_private->
612 p_rx_desc_area_base[queue] +
613 ethernet_private->rx_desc_area_size[queue])));
614 p_rx_curr_desc =
615 (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
616 RX_DESC_ALIGNED_SIZE)) {
617 if (p_rx_curr_desc->return_info != 0) {
618 p_rx_curr_desc->return_info = 0;
619 DP (printf ("freed\n"));
620 }
621 }
622 DP (printf ("Done\n"));
623 }
624 return 0;
625 }
626
627 /**********************************************************************
628 * mv64460_eth_stop
629 *
630 * This function is used when closing the network device.
631 * It updates the hardware,
632 * release all memory that holds buffers and descriptors and release the IRQ.
633 * Input : a pointer to the device structure
634 * Output : zero if success , nonzero if fails
635 *********************************************************************/
636
637 int mv64460_eth_stop (struct eth_device *dev)
638 {
639 ETH_PORT_INFO *ethernet_private;
640 struct mv64460_eth_priv *port_private;
641 unsigned int port_num;
642
643 ethernet_private = (ETH_PORT_INFO *) dev->priv;
644 port_private =
645 (struct mv64460_eth_priv *) ethernet_private->port_private;
646 port_num = port_private->port_num;
647
648 /* Disable all gigE address decoder */
649 MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
650 DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
651 mv64460_eth_real_stop (dev);
652
653 return 0;
654 };
655
656 /* Helper function for mv64460_eth_stop */
657
658 static int mv64460_eth_real_stop (struct eth_device *dev)
659 {
660 ETH_PORT_INFO *ethernet_private;
661 struct mv64460_eth_priv *port_private;
662 unsigned int port_num;
663
664 ethernet_private = (ETH_PORT_INFO *) dev->priv;
665 port_private =
666 (struct mv64460_eth_priv *) ethernet_private->port_private;
667 port_num = port_private->port_num;
668
669
670 mv64460_eth_free_tx_rings (dev);
671 mv64460_eth_free_rx_rings (dev);
672
673 eth_port_reset (ethernet_private->port_num);
674 /* Disable ethernet port interrupts */
675 MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
676 MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
677 /* Mask RX buffer and TX end interrupt */
678 MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), 0);
679 /* Mask phy and link status changes interrupts */
680 MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
681 MV_RESET_REG_BITS (MV64460_CPU_INTERRUPT0_MASK_HIGH,
682 BIT0 << port_num);
683 /* Print Network statistics */
684 #ifndef UPDATE_STATS_BY_SOFTWARE
685 /*
686 * Print statistics (only if ethernet is running),
687 * then zero all the stats fields in memory
688 */
689 if (port_private->eth_running == MAGIC_ETH_RUNNING) {
690 port_private->eth_running = 0;
691 mv64460_eth_print_stat (dev);
692 }
693 memset (port_private->stats, 0, sizeof (struct net_device_stats));
694 #endif
695 DP (printf ("\nEthernet stopped ... \n"));
696 return 0;
697 }
698
699
700 /**********************************************************************
701 * mv64460_eth_start_xmit
702 *
703 * This function is queues a packet in the Tx descriptor for
704 * required port.
705 *
706 * Input : skb - a pointer to socket buffer
707 * dev - a pointer to the required port
708 *
709 * Output : zero upon success
710 **********************************************************************/
711
712 int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
713 int dataSize)
714 {
715 ETH_PORT_INFO *ethernet_private;
716 struct mv64460_eth_priv *port_private;
717 unsigned int port_num;
718 PKT_INFO pkt_info;
719 ETH_FUNC_RET_STATUS status;
720 struct net_device_stats *stats;
721 ETH_FUNC_RET_STATUS release_result;
722
723 ethernet_private = (ETH_PORT_INFO *) dev->priv;
724 port_private =
725 (struct mv64460_eth_priv *) ethernet_private->port_private;
726 port_num = port_private->port_num;
727
728 stats = port_private->stats;
729
730 /* Update packet info data structure */
731 pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */
732 pkt_info.byte_cnt = dataSize;
733 pkt_info.buf_ptr = (unsigned int) dataPtr;
734
735 status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
736 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
737 printf ("Error on transmitting packet ..");
738 if (status == ETH_QUEUE_FULL)
739 printf ("ETH Queue is full. \n");
740 if (status == ETH_QUEUE_LAST_RESOURCE)
741 printf ("ETH Queue: using last available resource. \n");
742 goto error;
743 }
744
745 /* Update statistics and start of transmittion time */
746 stats->tx_bytes += dataSize;
747 stats->tx_packets++;
748
749 /* Check if packet(s) is(are) transmitted correctly (release everything) */
750 do {
751 release_result =
752 eth_tx_return_desc (ethernet_private, ETH_Q0,
753 &pkt_info);
754 switch (release_result) {
755 case ETH_OK:
756 DP (printf ("descriptor released\n"));
757 if (pkt_info.cmd_sts & BIT0) {
758 printf ("Error in TX\n");
759 stats->tx_errors++;
760
761 }
762 break;
763 case ETH_RETRY:
764 DP (printf ("transmission still in process\n"));
765 break;
766
767 case ETH_ERROR:
768 printf ("routine can not access Tx desc ring\n");
769 break;
770
771 case ETH_END_OF_JOB:
772 DP (printf ("the routine has nothing to release\n"));
773 break;
774 default: /* should not happen */
775 break;
776 }
777 } while (release_result == ETH_OK);
778
779
780 return 0; /* success */
781 error:
782 return 1; /* Failed - higher layers will free the skb */
783 }
784
785 /**********************************************************************
786 * mv64460_eth_receive
787 *
788 * This function is forward packets that are received from the port's
789 * queues toward kernel core or FastRoute them to another interface.
790 *
791 * Input : dev - a pointer to the required interface
792 * max - maximum number to receive (0 means unlimted)
793 *
794 * Output : number of served packets
795 **********************************************************************/
796
797 int mv64460_eth_receive (struct eth_device *dev)
798 {
799 ETH_PORT_INFO *ethernet_private;
800 struct mv64460_eth_priv *port_private;
801 unsigned int port_num;
802 PKT_INFO pkt_info;
803 struct net_device_stats *stats;
804
805
806 ethernet_private = (ETH_PORT_INFO *) dev->priv;
807 port_private =
808 (struct mv64460_eth_priv *) ethernet_private->port_private;
809 port_num = port_private->port_num;
810 stats = port_private->stats;
811
812 while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
813 ETH_OK)) {
814
815 #ifdef DEBUG_MV_ETH
816 if (pkt_info.byte_cnt != 0) {
817 printf ("%s: Received %d byte Packet @ 0x%x\n",
818 __FUNCTION__, pkt_info.byte_cnt,
819 pkt_info.buf_ptr);
820 }
821 #endif
822 /* Update statistics. Note byte count includes 4 byte CRC count */
823 stats->rx_packets++;
824 stats->rx_bytes += pkt_info.byte_cnt;
825
826 /*
827 * In case received a packet without first / last bits on OR the error
828 * summary bit is on, the packets needs to be dropeed.
829 */
830 if (((pkt_info.
831 cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
832 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
833 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
834 stats->rx_dropped++;
835
836 printf ("Received packet spread on multiple descriptors\n");
837
838 /* Is this caused by an error ? */
839 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
840 stats->rx_errors++;
841 }
842
843 /* free these descriptors again without forwarding them to the higher layers */
844 pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
845 pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
846
847 if (eth_rx_return_buff
848 (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
849 printf ("Error while returning the RX Desc to Ring\n");
850 } else {
851 DP (printf ("RX Desc returned to Ring\n"));
852 }
853 /* /free these descriptors again */
854 } else {
855
856 /* !!! call higher layer processing */
857 #ifdef DEBUG_MV_ETH
858 printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
859 #endif
860 /* let the upper layer handle the packet */
861 NetReceive ((uchar *) pkt_info.buf_ptr,
862 (int) pkt_info.byte_cnt);
863
864 /* **************************************************************** */
865 /* free descriptor */
866 pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
867 pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
868 DP (printf
869 ("RX: pkt_info.buf_ptr = %x\n",
870 pkt_info.buf_ptr));
871 if (eth_rx_return_buff
872 (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
873 printf ("Error while returning the RX Desc to Ring\n");
874 } else {
875 DP (printf ("RX Desc returned to Ring\n"));
876 }
877
878 /* **************************************************************** */
879
880 }
881 }
882 mv64460_eth_get_stats (dev); /* update statistics */
883 return 1;
884 }
885
886 /**********************************************************************
887 * mv64460_eth_get_stats
888 *
889 * Returns a pointer to the interface statistics.
890 *
891 * Input : dev - a pointer to the required interface
892 *
893 * Output : a pointer to the interface's statistics
894 **********************************************************************/
895
896 static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev)
897 {
898 ETH_PORT_INFO *ethernet_private;
899 struct mv64460_eth_priv *port_private;
900 unsigned int port_num;
901
902 ethernet_private = (ETH_PORT_INFO *) dev->priv;
903 port_private =
904 (struct mv64460_eth_priv *) ethernet_private->port_private;
905 port_num = port_private->port_num;
906
907 mv64460_eth_update_stat (dev);
908
909 return port_private->stats;
910 }
911
912
913 /**********************************************************************
914 * mv64460_eth_update_stat
915 *
916 * Update the statistics structure in the private data structure
917 *
918 * Input : pointer to ethernet interface network device structure
919 * Output : N/A
920 **********************************************************************/
921
922 static void mv64460_eth_update_stat (struct eth_device *dev)
923 {
924 ETH_PORT_INFO *ethernet_private;
925 struct mv64460_eth_priv *port_private;
926 struct net_device_stats *stats;
927 unsigned int port_num;
928 volatile unsigned int dummy;
929
930 ethernet_private = (ETH_PORT_INFO *) dev->priv;
931 port_private =
932 (struct mv64460_eth_priv *) ethernet_private->port_private;
933 port_num = port_private->port_num;
934 stats = port_private->stats;
935
936 /* These are false updates */
937 stats->rx_packets += (unsigned long)
938 eth_read_mib_counter (ethernet_private->port_num,
939 ETH_MIB_GOOD_FRAMES_RECEIVED);
940 stats->tx_packets += (unsigned long)
941 eth_read_mib_counter (ethernet_private->port_num,
942 ETH_MIB_GOOD_FRAMES_SENT);
943 stats->rx_bytes += (unsigned long)
944 eth_read_mib_counter (ethernet_private->port_num,
945 ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
946 /*
947 * Ideally this should be as follows -
948 *
949 * stats->rx_bytes += stats->rx_bytes +
950 * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
951 * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
952 *
953 * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
954 * is just a dummy read for proper work of the GigE port
955 */
956 dummy = eth_read_mib_counter (ethernet_private->port_num,
957 ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
958 stats->tx_bytes += (unsigned long)
959 eth_read_mib_counter (ethernet_private->port_num,
960 ETH_MIB_GOOD_OCTETS_SENT_LOW);
961 dummy = eth_read_mib_counter (ethernet_private->port_num,
962 ETH_MIB_GOOD_OCTETS_SENT_HIGH);
963 stats->rx_errors += (unsigned long)
964 eth_read_mib_counter (ethernet_private->port_num,
965 ETH_MIB_MAC_RECEIVE_ERROR);
966
967 /* Rx dropped is for received packet with CRC error */
968 stats->rx_dropped +=
969 (unsigned long) eth_read_mib_counter (ethernet_private->
970 port_num,
971 ETH_MIB_BAD_CRC_EVENT);
972 stats->multicast += (unsigned long)
973 eth_read_mib_counter (ethernet_private->port_num,
974 ETH_MIB_MULTICAST_FRAMES_RECEIVED);
975 stats->collisions +=
976 (unsigned long) eth_read_mib_counter (ethernet_private->
977 port_num,
978 ETH_MIB_COLLISION) +
979 (unsigned long) eth_read_mib_counter (ethernet_private->
980 port_num,
981 ETH_MIB_LATE_COLLISION);
982 /* detailed rx errors */
983 stats->rx_length_errors +=
984 (unsigned long) eth_read_mib_counter (ethernet_private->
985 port_num,
986 ETH_MIB_UNDERSIZE_RECEIVED)
987 +
988 (unsigned long) eth_read_mib_counter (ethernet_private->
989 port_num,
990 ETH_MIB_OVERSIZE_RECEIVED);
991 /* detailed tx errors */
992 }
993
994 #ifndef UPDATE_STATS_BY_SOFTWARE
995 /**********************************************************************
996 * mv64460_eth_print_stat
997 *
998 * Update the statistics structure in the private data structure
999 *
1000 * Input : pointer to ethernet interface network device structure
1001 * Output : N/A
1002 **********************************************************************/
1003
1004 static void mv64460_eth_print_stat (struct eth_device *dev)
1005 {
1006 ETH_PORT_INFO *ethernet_private;
1007 struct mv64460_eth_priv *port_private;
1008 struct net_device_stats *stats;
1009 unsigned int port_num;
1010
1011 ethernet_private = (ETH_PORT_INFO *) dev->priv;
1012 port_private =
1013 (struct mv64460_eth_priv *) ethernet_private->port_private;
1014 port_num = port_private->port_num;
1015 stats = port_private->stats;
1016
1017 /* These are false updates */
1018 printf ("\n### Network statistics: ###\n");
1019 printf ("--------------------------\n");
1020 printf (" Packets received: %ld\n", stats->rx_packets);
1021 printf (" Packets send: %ld\n", stats->tx_packets);
1022 printf (" Received bytes: %ld\n", stats->rx_bytes);
1023 printf (" Send bytes: %ld\n", stats->tx_bytes);
1024 if (stats->rx_errors != 0)
1025 printf (" Rx Errors: %ld\n",
1026 stats->rx_errors);
1027 if (stats->rx_dropped != 0)
1028 printf (" Rx dropped (CRC Errors): %ld\n",
1029 stats->rx_dropped);
1030 if (stats->multicast != 0)
1031 printf (" Rx mulicast frames: %ld\n",
1032 stats->multicast);
1033 if (stats->collisions != 0)
1034 printf (" No. of collisions: %ld\n",
1035 stats->collisions);
1036 if (stats->rx_length_errors != 0)
1037 printf (" Rx length errors: %ld\n",
1038 stats->rx_length_errors);
1039 }
1040 #endif
1041
1042 /**************************************************************************
1043 *network_start - Network Kick Off Routine UBoot
1044 *Inputs :
1045 *Outputs :
1046 **************************************************************************/
1047
1048 bool db64460_eth_start (struct eth_device *dev)
1049 {
1050 return (mv64460_eth_open (dev)); /* calls real open */
1051 }
1052
1053 /*************************************************************************
1054 **************************************************************************
1055 **************************************************************************
1056 * The second part is the low level driver of the gigE ethernet ports. *
1057 **************************************************************************
1058 **************************************************************************
1059 *************************************************************************/
1060 /*
1061 * based on Linux code
1062 * arch/ppc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports
1063 * Copyright (C) 2002 rabeeh@galileo.co.il
1064
1065 * This program is free software; you can redistribute it and/or
1066 * modify it under the terms of the GNU General Public License
1067 * as published by the Free Software Foundation; either version 2
1068 * of the License, or (at your option) any later version.
1069
1070 * This program is distributed in the hope that it will be useful,
1071 * but WITHOUT ANY WARRANTY; without even the implied warranty of
1072 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1073 * GNU General Public License for more details.
1074
1075 * You should have received a copy of the GNU General Public License
1076 * along with this program; if not, write to the Free Software
1077 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
1078 *
1079 */
1080
1081 /********************************************************************************
1082 * Marvell's Gigabit Ethernet controller low level driver
1083 *
1084 * DESCRIPTION:
1085 * This file introduce low level API to Marvell's Gigabit Ethernet
1086 * controller. This Gigabit Ethernet Controller driver API controls
1087 * 1) Operations (i.e. port init, start, reset etc').
1088 * 2) Data flow (i.e. port send, receive etc').
1089 * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
1090 * struct.
1091 * This struct includes user configuration information as well as
1092 * driver internal data needed for its operations.
1093 *
1094 * Supported Features:
1095 * - This low level driver is OS independent. Allocating memory for
1096 * the descriptor rings and buffers are not within the scope of
1097 * this driver.
1098 * - The user is free from Rx/Tx queue managing.
1099 * - This low level driver introduce functionality API that enable
1100 * the to operate Marvell's Gigabit Ethernet Controller in a
1101 * convenient way.
1102 * - Simple Gigabit Ethernet port operation API.
1103 * - Simple Gigabit Ethernet port data flow API.
1104 * - Data flow and operation API support per queue functionality.
1105 * - Support cached descriptors for better performance.
1106 * - Enable access to all four DRAM banks and internal SRAM memory
1107 * spaces.
1108 * - PHY access and control API.
1109 * - Port control register configuration API.
1110 * - Full control over Unicast and Multicast MAC configurations.
1111 *
1112 * Operation flow:
1113 *
1114 * Initialization phase
1115 * This phase complete the initialization of the ETH_PORT_INFO
1116 * struct.
1117 * User information regarding port configuration has to be set
1118 * prior to calling the port initialization routine. For example,
1119 * the user has to assign the port_phy_addr field which is board
1120 * depended parameter.
1121 * In this phase any port Tx/Rx activity is halted, MIB counters
1122 * are cleared, PHY address is set according to user parameter and
1123 * access to DRAM and internal SRAM memory spaces.
1124 *
1125 * Driver ring initialization
1126 * Allocating memory for the descriptor rings and buffers is not
1127 * within the scope of this driver. Thus, the user is required to
1128 * allocate memory for the descriptors ring and buffers. Those
1129 * memory parameters are used by the Rx and Tx ring initialization
1130 * routines in order to curve the descriptor linked list in a form
1131 * of a ring.
1132 * Note: Pay special attention to alignment issues when using
1133 * cached descriptors/buffers. In this phase the driver store
1134 * information in the ETH_PORT_INFO struct regarding each queue
1135 * ring.
1136 *
1137 * Driver start
1138 * This phase prepares the Ethernet port for Rx and Tx activity.
1139 * It uses the information stored in the ETH_PORT_INFO struct to
1140 * initialize the various port registers.
1141 *
1142 * Data flow:
1143 * All packet references to/from the driver are done using PKT_INFO
1144 * struct.
1145 * This struct is a unified struct used with Rx and Tx operations.
1146 * This way the user is not required to be familiar with neither
1147 * Tx nor Rx descriptors structures.
1148 * The driver's descriptors rings are management by indexes.
1149 * Those indexes controls the ring resources and used to indicate
1150 * a SW resource error:
1151 * 'current'
1152 * This index points to the current available resource for use. For
1153 * example in Rx process this index will point to the descriptor
1154 * that will be passed to the user upon calling the receive routine.
1155 * In Tx process, this index will point to the descriptor
1156 * that will be assigned with the user packet info and transmitted.
1157 * 'used'
1158 * This index points to the descriptor that need to restore its
1159 * resources. For example in Rx process, using the Rx buffer return
1160 * API will attach the buffer returned in packet info to the
1161 * descriptor pointed by 'used'. In Tx process, using the Tx
1162 * descriptor return will merely return the user packet info with
1163 * the command status of the transmitted buffer pointed by the
1164 * 'used' index. Nevertheless, it is essential to use this routine
1165 * to update the 'used' index.
1166 * 'first'
1167 * This index supports Tx Scatter-Gather. It points to the first
1168 * descriptor of a packet assembled of multiple buffers. For example
1169 * when in middle of Such packet we have a Tx resource error the
1170 * 'curr' index get the value of 'first' to indicate that the ring
1171 * returned to its state before trying to transmit this packet.
1172 *
1173 * Receive operation:
1174 * The eth_port_receive API set the packet information struct,
1175 * passed by the caller, with received information from the
1176 * 'current' SDMA descriptor.
1177 * It is the user responsibility to return this resource back
1178 * to the Rx descriptor ring to enable the reuse of this source.
1179 * Return Rx resource is done using the eth_rx_return_buff API.
1180 *
1181 * Transmit operation:
1182 * The eth_port_send API supports Scatter-Gather which enables to
1183 * send a packet spanned over multiple buffers. This means that
1184 * for each packet info structure given by the user and put into
1185 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1186 * bit will be set in the packet info command status field. This
1187 * API also consider restriction regarding buffer alignments and
1188 * sizes.
1189 * The user must return a Tx resource after ensuring the buffer
1190 * has been transmitted to enable the Tx ring indexes to update.
1191 *
1192 * BOARD LAYOUT
1193 * This device is on-board. No jumper diagram is necessary.
1194 *
1195 * EXTERNAL INTERFACE
1196 *
1197 * Prior to calling the initialization routine eth_port_init() the user
1198 * must set the following fields under ETH_PORT_INFO struct:
1199 * port_num User Ethernet port number.
1200 * port_phy_addr User PHY address of Ethernet port.
1201 * port_mac_addr[6] User defined port MAC address.
1202 * port_config User port configuration value.
1203 * port_config_extend User port config extend value.
1204 * port_sdma_config User port SDMA config value.
1205 * port_serial_control User port serial control value.
1206 * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr.
1207 * *port_private User scratch pad for user specific data structures.
1208 *
1209 * This driver introduce a set of default values:
1210 * PORT_CONFIG_VALUE Default port configuration value
1211 * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value
1212 * PORT_SDMA_CONFIG_VALUE Default sdma control value
1213 * PORT_SERIAL_CONTROL_VALUE Default port serial control value
1214 *
1215 * This driver data flow is done using the PKT_INFO struct which is
1216 * a unified struct for Rx and Tx operations:
1217 * byte_cnt Tx/Rx descriptor buffer byte count.
1218 * l4i_chk CPU provided TCP Checksum. For Tx operation only.
1219 * cmd_sts Tx/Rx descriptor command status.
1220 * buf_ptr Tx/Rx descriptor buffer pointer.
1221 * return_info Tx/Rx user resource return information.
1222 *
1223 *
1224 * EXTERNAL SUPPORT REQUIREMENTS
1225 *
1226 * This driver requires the following external support:
1227 *
1228 * D_CACHE_FLUSH_LINE (address, address offset)
1229 *
1230 * This macro applies assembly code to flush and invalidate cache
1231 * line.
1232 * address - address base.
1233 * address offset - address offset
1234 *
1235 *
1236 * CPU_PIPE_FLUSH
1237 *
1238 * This macro applies assembly code to flush the CPU pipeline.
1239 *
1240 *******************************************************************************/
1241 /* includes */
1242
1243 /* defines */
1244 /* SDMA command macros */
1245 #define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
1246 MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
1247
1248 #define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
1249 MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
1250 (1 << (8 + tx_queue)))
1251
1252 #define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
1253 MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
1254
1255 #define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
1256 MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
1257
1258 #define CURR_RFD_GET(p_curr_desc, queue) \
1259 ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
1260
1261 #define CURR_RFD_SET(p_curr_desc, queue) \
1262 (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
1263
1264 #define USED_RFD_GET(p_used_desc, queue) \
1265 ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
1266
1267 #define USED_RFD_SET(p_used_desc, queue)\
1268 (p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
1269
1270
1271 #define CURR_TFD_GET(p_curr_desc, queue) \
1272 ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
1273
1274 #define CURR_TFD_SET(p_curr_desc, queue) \
1275 (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
1276
1277 #define USED_TFD_GET(p_used_desc, queue) \
1278 ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
1279
1280 #define USED_TFD_SET(p_used_desc, queue) \
1281 (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
1282
1283 #define FIRST_TFD_GET(p_first_desc, queue) \
1284 ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
1285
1286 #define FIRST_TFD_SET(p_first_desc, queue) \
1287 (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
1288
1289
1290 /* Macros that save access to desc in order to find next desc pointer */
1291 #define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
1292
1293 #define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
1294
1295 #define LINK_UP_TIMEOUT 100000
1296 #define PHY_BUSY_TIMEOUT 10000000
1297
1298 /* locals */
1299
1300 /* PHY routines */
1301 static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
1302 static int ethernet_phy_get (ETH_PORT eth_port_num);
1303
1304 /* Ethernet Port routines */
1305 static void eth_set_access_control (ETH_PORT eth_port_num,
1306 ETH_WIN_PARAM * param);
1307 static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
1308 ETH_QUEUE queue, int option);
1309 #if 0 /* FIXME */
1310 static bool eth_port_smc_addr (ETH_PORT eth_port_num,
1311 unsigned char mc_byte,
1312 ETH_QUEUE queue, int option);
1313 static bool eth_port_omc_addr (ETH_PORT eth_port_num,
1314 unsigned char crc8,
1315 ETH_QUEUE queue, int option);
1316 #endif
1317
1318 static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
1319 int byte_count);
1320
1321 void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
1322
1323
1324 typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
1325 u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
1326 {
1327 u32 result = 0;
1328 u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
1329
1330 if (enable & (1 << bank))
1331 return 0;
1332 if (bank == BANK0)
1333 result = MV_REG_READ (MV64460_CS_0_BASE_ADDR);
1334 if (bank == BANK1)
1335 result = MV_REG_READ (MV64460_CS_1_BASE_ADDR);
1336 if (bank == BANK2)
1337 result = MV_REG_READ (MV64460_CS_2_BASE_ADDR);
1338 if (bank == BANK3)
1339 result = MV_REG_READ (MV64460_CS_3_BASE_ADDR);
1340 result &= 0x0000ffff;
1341 result = result << 16;
1342 return result;
1343 }
1344
1345 u32 mv_get_dram_bank_size (MEMORY_BANK bank)
1346 {
1347 u32 result = 0;
1348 u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
1349
1350 if (enable & (1 << bank))
1351 return 0;
1352 if (bank == BANK0)
1353 result = MV_REG_READ (MV64460_CS_0_SIZE);
1354 if (bank == BANK1)
1355 result = MV_REG_READ (MV64460_CS_1_SIZE);
1356 if (bank == BANK2)
1357 result = MV_REG_READ (MV64460_CS_2_SIZE);
1358 if (bank == BANK3)
1359 result = MV_REG_READ (MV64460_CS_3_SIZE);
1360 result += 1;
1361 result &= 0x0000ffff;
1362 result = result << 16;
1363 return result;
1364 }
1365
1366 u32 mv_get_internal_sram_base (void)
1367 {
1368 u32 result;
1369
1370 result = MV_REG_READ (MV64460_INTEGRATED_SRAM_BASE_ADDR);
1371 result &= 0x0000ffff;
1372 result = result << 16;
1373 return result;
1374 }
1375
1376 /*******************************************************************************
1377 * eth_port_init - Initialize the Ethernet port driver
1378 *
1379 * DESCRIPTION:
1380 * This function prepares the ethernet port to start its activity:
1381 * 1) Completes the ethernet port driver struct initialization toward port
1382 * start routine.
1383 * 2) Resets the device to a quiescent state in case of warm reboot.
1384 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1385 * 4) Clean MAC tables. The reset status of those tables is unknown.
1386 * 5) Set PHY address.
1387 * Note: Call this routine prior to eth_port_start routine and after setting
1388 * user values in the user fields of Ethernet port control struct (i.e.
1389 * port_phy_addr).
1390 *
1391 * INPUT:
1392 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
1393 *
1394 * OUTPUT:
1395 * See description.
1396 *
1397 * RETURN:
1398 * None.
1399 *
1400 *******************************************************************************/
1401 static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
1402 {
1403 int queue;
1404 ETH_WIN_PARAM win_param;
1405
1406 p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
1407 p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
1408 p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
1409 p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
1410
1411 p_eth_port_ctrl->port_rx_queue_command = 0;
1412 p_eth_port_ctrl->port_tx_queue_command = 0;
1413
1414 /* Zero out SW structs */
1415 for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
1416 CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
1417 USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
1418 p_eth_port_ctrl->rx_resource_err[queue] = false;
1419 }
1420
1421 for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
1422 CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1423 USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1424 FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1425 p_eth_port_ctrl->tx_resource_err[queue] = false;
1426 }
1427
1428 eth_port_reset (p_eth_port_ctrl->port_num);
1429
1430 /* Set access parameters for DRAM bank 0 */
1431 win_param.win = ETH_WIN0; /* Use Ethernet window 0 */
1432 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1433 win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */
1434 #ifndef CONFIG_NOT_COHERENT_CACHE
1435 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1436 #endif
1437 win_param.high_addr = 0;
1438 /* Get bank base */
1439 win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
1440 win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */
1441 if (win_param.size == 0)
1442 win_param.enable = 0;
1443 else
1444 win_param.enable = 1; /* Enable the access */
1445 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1446
1447 /* Set the access control for address window (EPAPR) READ & WRITE */
1448 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1449
1450 /* Set access parameters for DRAM bank 1 */
1451 win_param.win = ETH_WIN1; /* Use Ethernet window 1 */
1452 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1453 win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */
1454 #ifndef CONFIG_NOT_COHERENT_CACHE
1455 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1456 #endif
1457 win_param.high_addr = 0;
1458 /* Get bank base */
1459 win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
1460 win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */
1461 if (win_param.size == 0)
1462 win_param.enable = 0;
1463 else
1464 win_param.enable = 1; /* Enable the access */
1465 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1466
1467 /* Set the access control for address window (EPAPR) READ & WRITE */
1468 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1469
1470 /* Set access parameters for DRAM bank 2 */
1471 win_param.win = ETH_WIN2; /* Use Ethernet window 2 */
1472 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1473 win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */
1474 #ifndef CONFIG_NOT_COHERENT_CACHE
1475 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1476 #endif
1477 win_param.high_addr = 0;
1478 /* Get bank base */
1479 win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
1480 win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */
1481 if (win_param.size == 0)
1482 win_param.enable = 0;
1483 else
1484 win_param.enable = 1; /* Enable the access */
1485 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1486
1487 /* Set the access control for address window (EPAPR) READ & WRITE */
1488 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1489
1490 /* Set access parameters for DRAM bank 3 */
1491 win_param.win = ETH_WIN3; /* Use Ethernet window 3 */
1492 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1493 win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */
1494 #ifndef CONFIG_NOT_COHERENT_CACHE
1495 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1496 #endif
1497 win_param.high_addr = 0;
1498 /* Get bank base */
1499 win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
1500 win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */
1501 if (win_param.size == 0)
1502 win_param.enable = 0;
1503 else
1504 win_param.enable = 1; /* Enable the access */
1505 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1506
1507 /* Set the access control for address window (EPAPR) READ & WRITE */
1508 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1509
1510 /* Set access parameters for Internal SRAM */
1511 win_param.win = ETH_WIN4; /* Use Ethernet window 0 */
1512 win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */
1513 win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
1514 win_param.high_addr = 0;
1515 win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */
1516 win_param.size = MV64460_INTERNAL_SRAM_SIZE; /* Get bank size */
1517 win_param.enable = 1; /* Enable the access */
1518 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1519
1520 /* Set the access control for address window (EPAPR) READ & WRITE */
1521 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1522
1523 eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
1524
1525 ethernet_phy_set (p_eth_port_ctrl->port_num,
1526 p_eth_port_ctrl->port_phy_addr);
1527
1528 return;
1529
1530 }
1531
1532 /*******************************************************************************
1533 * eth_port_start - Start the Ethernet port activity.
1534 *
1535 * DESCRIPTION:
1536 * This routine prepares the Ethernet port for Rx and Tx activity:
1537 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1538 * has been initialized a descriptor's ring (using ether_init_tx_desc_ring
1539 * for Tx and ether_init_rx_desc_ring for Rx)
1540 * 2. Initialize and enable the Ethernet configuration port by writing to
1541 * the port's configuration and command registers.
1542 * 3. Initialize and enable the SDMA by writing to the SDMA's
1543 * configuration and command registers.
1544 * After completing these steps, the ethernet port SDMA can starts to
1545 * perform Rx and Tx activities.
1546 *
1547 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1548 * to calling this function (use ether_init_tx_desc_ring for Tx queues and
1549 * ether_init_rx_desc_ring for Rx queues).
1550 *
1551 * INPUT:
1552 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
1553 *
1554 * OUTPUT:
1555 * Ethernet port is ready to receive and transmit.
1556 *
1557 * RETURN:
1558 * false if the port PHY is not up.
1559 * true otherwise.
1560 *
1561 *******************************************************************************/
1562 static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
1563 {
1564 int queue;
1565 volatile ETH_TX_DESC *p_tx_curr_desc;
1566 volatile ETH_RX_DESC *p_rx_curr_desc;
1567 unsigned int phy_reg_data;
1568 ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
1569
1570
1571 /* Assignment of Tx CTRP of given queue */
1572 for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
1573 CURR_TFD_GET (p_tx_curr_desc, queue);
1574 MV_REG_WRITE ((MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
1575 (eth_port_num)
1576 + (4 * queue)),
1577 ((unsigned int) p_tx_curr_desc));
1578
1579 }
1580
1581 /* Assignment of Rx CRDP of given queue */
1582 for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
1583 CURR_RFD_GET (p_rx_curr_desc, queue);
1584 MV_REG_WRITE ((MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
1585 (eth_port_num)
1586 + (4 * queue)),
1587 ((unsigned int) p_rx_curr_desc));
1588
1589 if (p_rx_curr_desc != NULL)
1590 /* Add the assigned Ethernet address to the port's address table */
1591 eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
1592 p_eth_port_ctrl->port_mac_addr,
1593 queue);
1594 }
1595
1596 /* Assign port configuration and command. */
1597 MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
1598 p_eth_port_ctrl->port_config);
1599
1600 MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
1601 p_eth_port_ctrl->port_config_extend);
1602
1603 MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
1604 p_eth_port_ctrl->port_serial_control);
1605
1606 MV_SET_REG_BITS (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
1607 ETH_SERIAL_PORT_ENABLE);
1608
1609 /* Assign port SDMA configuration */
1610 MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
1611 p_eth_port_ctrl->port_sdma_config);
1612
1613 MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
1614 (eth_port_num), 0x3fffffff);
1615 MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
1616 (eth_port_num), 0x03fffcff);
1617 /* Turn off the port/queue bandwidth limitation */
1618 MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
1619
1620 /* Enable port Rx. */
1621 MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
1622 p_eth_port_ctrl->port_rx_queue_command);
1623
1624 /* Check if link is up */
1625 eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
1626
1627 if (!(phy_reg_data & 0x20))
1628 return false;
1629
1630 return true;
1631 }
1632
1633 /*******************************************************************************
1634 * eth_port_uc_addr_set - This function Set the port Unicast address.
1635 *
1636 * DESCRIPTION:
1637 * This function Set the port Ethernet MAC address.
1638 *
1639 * INPUT:
1640 * ETH_PORT eth_port_num Port number.
1641 * char * p_addr Address to be set
1642 * ETH_QUEUE queue Rx queue number for this MAC address.
1643 *
1644 * OUTPUT:
1645 * Set MAC address low and high registers. also calls eth_port_uc_addr()
1646 * To set the unicast table with the proper information.
1647 *
1648 * RETURN:
1649 * N/A.
1650 *
1651 *******************************************************************************/
1652 static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
1653 unsigned char *p_addr, ETH_QUEUE queue)
1654 {
1655 unsigned int mac_h;
1656 unsigned int mac_l;
1657
1658 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1659 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
1660 (p_addr[2] << 8) | (p_addr[3] << 0);
1661
1662 MV_REG_WRITE (MV64460_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
1663 MV_REG_WRITE (MV64460_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
1664
1665 /* Accept frames of this address */
1666 eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
1667
1668 return;
1669 }
1670
1671 /*******************************************************************************
1672 * eth_port_uc_addr - This function Set the port unicast address table
1673 *
1674 * DESCRIPTION:
1675 * This function locates the proper entry in the Unicast table for the
1676 * specified MAC nibble and sets its properties according to function
1677 * parameters.
1678 *
1679 * INPUT:
1680 * ETH_PORT eth_port_num Port number.
1681 * unsigned char uc_nibble Unicast MAC Address last nibble.
1682 * ETH_QUEUE queue Rx queue number for this MAC address.
1683 * int option 0 = Add, 1 = remove address.
1684 *
1685 * OUTPUT:
1686 * This function add/removes MAC addresses from the port unicast address
1687 * table.
1688 *
1689 * RETURN:
1690 * true is output succeeded.
1691 * false if option parameter is invalid.
1692 *
1693 *******************************************************************************/
1694 static bool eth_port_uc_addr (ETH_PORT eth_port_num,
1695 unsigned char uc_nibble,
1696 ETH_QUEUE queue, int option)
1697 {
1698 unsigned int unicast_reg;
1699 unsigned int tbl_offset;
1700 unsigned int reg_offset;
1701
1702 /* Locate the Unicast table entry */
1703 uc_nibble = (0xf & uc_nibble);
1704 tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
1705 reg_offset = uc_nibble % 4; /* Entry offset within the above register */
1706
1707 switch (option) {
1708 case REJECT_MAC_ADDR:
1709 /* Clear accepts frame bit at specified unicast DA table entry */
1710 unicast_reg =
1711 MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
1712 (eth_port_num)
1713 + tbl_offset));
1714
1715 unicast_reg &= (0x0E << (8 * reg_offset));
1716
1717 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
1718 (eth_port_num)
1719 + tbl_offset), unicast_reg);
1720 break;
1721
1722 case ACCEPT_MAC_ADDR:
1723 /* Set accepts frame bit at unicast DA filter table entry */
1724 unicast_reg =
1725 MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
1726 (eth_port_num)
1727 + tbl_offset));
1728
1729 unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
1730
1731 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
1732 (eth_port_num)
1733 + tbl_offset), unicast_reg);
1734
1735 break;
1736
1737 default:
1738 return false;
1739 }
1740 return true;
1741 }
1742
1743 #if 0 /* FIXME */
1744 /*******************************************************************************
1745 * eth_port_mc_addr - Multicast address settings.
1746 *
1747 * DESCRIPTION:
1748 * This API controls the MV device MAC multicast support.
1749 * The MV device supports multicast using two tables:
1750 * 1) Special Multicast Table for MAC addresses of the form
1751 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
1752 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1753 * Table entries in the DA-Filter table.
1754 * In this case, the function calls eth_port_smc_addr() routine to set the
1755 * Special Multicast Table.
1756 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
1757 * is used as an index to the Other Multicast Table entries in the
1758 * DA-Filter table.
1759 * In this case, the function calculates the CRC-8bit value and calls
1760 * eth_port_omc_addr() routine to set the Other Multicast Table.
1761 * INPUT:
1762 * ETH_PORT eth_port_num Port number.
1763 * unsigned char *p_addr Unicast MAC Address.
1764 * ETH_QUEUE queue Rx queue number for this MAC address.
1765 * int option 0 = Add, 1 = remove address.
1766 *
1767 * OUTPUT:
1768 * See description.
1769 *
1770 * RETURN:
1771 * true is output succeeded.
1772 * false if add_address_table_entry( ) failed.
1773 *
1774 *******************************************************************************/
1775 static void eth_port_mc_addr (ETH_PORT eth_port_num,
1776 unsigned char *p_addr,
1777 ETH_QUEUE queue, int option)
1778 {
1779 unsigned int mac_h;
1780 unsigned int mac_l;
1781 unsigned char crc_result = 0;
1782 int mac_array[48];
1783 int crc[8];
1784 int i;
1785
1786
1787 if ((p_addr[0] == 0x01) &&
1788 (p_addr[1] == 0x00) &&
1789 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
1790
1791 eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
1792 else {
1793 /* Calculate CRC-8 out of the given address */
1794 mac_h = (p_addr[0] << 8) | (p_addr[1]);
1795 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
1796 (p_addr[4] << 8) | (p_addr[5] << 0);
1797
1798 for (i = 0; i < 32; i++)
1799 mac_array[i] = (mac_l >> i) & 0x1;
1800 for (i = 32; i < 48; i++)
1801 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1802
1803
1804 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
1805 mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
1806 mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
1807 mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
1808 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
1809 mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
1810 mac_array[6] ^ mac_array[0];
1811
1812 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
1813 mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
1814 mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
1815 mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
1816 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
1817 mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
1818 mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
1819 mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
1820 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
1821 mac_array[0];
1822
1823 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
1824 mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
1825 mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
1826 mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
1827 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
1828 mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
1829 mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
1830 mac_array[2] ^ mac_array[1] ^ mac_array[0];
1831
1832 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
1833 mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
1834 mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
1835 mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
1836 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
1837 mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
1838 mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
1839 mac_array[2] ^ mac_array[1];
1840
1841 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
1842 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
1843 mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
1844 mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
1845 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
1846 mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
1847 mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
1848 mac_array[2];
1849
1850 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
1851 mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
1852 mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
1853 mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
1854 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
1855 mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
1856 mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
1857 mac_array[3];
1858
1859 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
1860 mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
1861 mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
1862 mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
1863 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
1864 mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
1865 mac_array[6] ^ mac_array[5] ^ mac_array[4];
1866
1867 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
1868 mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
1869 mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
1870 mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
1871 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
1872 mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
1873 mac_array[6] ^ mac_array[5];
1874
1875 for (i = 0; i < 8; i++)
1876 crc_result = crc_result | (crc[i] << i);
1877
1878 eth_port_omc_addr (eth_port_num, crc_result, queue, option);
1879 }
1880 return;
1881 }
1882
1883 /*******************************************************************************
1884 * eth_port_smc_addr - Special Multicast address settings.
1885 *
1886 * DESCRIPTION:
1887 * This routine controls the MV device special MAC multicast support.
1888 * The Special Multicast Table for MAC addresses supports MAC of the form
1889 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
1890 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1891 * Table entries in the DA-Filter table.
1892 * This function set the Special Multicast Table appropriate entry
1893 * according to the argument given.
1894 *
1895 * INPUT:
1896 * ETH_PORT eth_port_num Port number.
1897 * unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits).
1898 * ETH_QUEUE queue Rx queue number for this MAC address.
1899 * int option 0 = Add, 1 = remove address.
1900 *
1901 * OUTPUT:
1902 * See description.
1903 *
1904 * RETURN:
1905 * true is output succeeded.
1906 * false if option parameter is invalid.
1907 *
1908 *******************************************************************************/
1909 static bool eth_port_smc_addr (ETH_PORT eth_port_num,
1910 unsigned char mc_byte,
1911 ETH_QUEUE queue, int option)
1912 {
1913 unsigned int smc_table_reg;
1914 unsigned int tbl_offset;
1915 unsigned int reg_offset;
1916
1917 /* Locate the SMC table entry */
1918 tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */
1919 reg_offset = mc_byte % 4; /* Entry offset within the above register */
1920 queue &= 0x7;
1921
1922 switch (option) {
1923 case REJECT_MAC_ADDR:
1924 /* Clear accepts frame bit at specified Special DA table entry */
1925 smc_table_reg =
1926 MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1927 smc_table_reg &= (0x0E << (8 * reg_offset));
1928
1929 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
1930 break;
1931
1932 case ACCEPT_MAC_ADDR:
1933 /* Set accepts frame bit at specified Special DA table entry */
1934 smc_table_reg =
1935 MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1936 smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
1937
1938 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
1939 break;
1940
1941 default:
1942 return false;
1943 }
1944 return true;
1945 }
1946
1947 /*******************************************************************************
1948 * eth_port_omc_addr - Multicast address settings.
1949 *
1950 * DESCRIPTION:
1951 * This routine controls the MV device Other MAC multicast support.
1952 * The Other Multicast Table is used for multicast of another type.
1953 * A CRC-8bit is used as an index to the Other Multicast Table entries
1954 * in the DA-Filter table.
1955 * The function gets the CRC-8bit value from the calling routine and
1956 * set the Other Multicast Table appropriate entry according to the
1957 * CRC-8 argument given.
1958 *
1959 * INPUT:
1960 * ETH_PORT eth_port_num Port number.
1961 * unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
1962 * ETH_QUEUE queue Rx queue number for this MAC address.
1963 * int option 0 = Add, 1 = remove address.
1964 *
1965 * OUTPUT:
1966 * See description.
1967 *
1968 * RETURN:
1969 * true is output succeeded.
1970 * false if option parameter is invalid.
1971 *
1972 *******************************************************************************/
1973 static bool eth_port_omc_addr (ETH_PORT eth_port_num,
1974 unsigned char crc8,
1975 ETH_QUEUE queue, int option)
1976 {
1977 unsigned int omc_table_reg;
1978 unsigned int tbl_offset;
1979 unsigned int reg_offset;
1980
1981 /* Locate the OMC table entry */
1982 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
1983 reg_offset = crc8 % 4; /* Entry offset within the above register */
1984 queue &= 0x7;
1985
1986 switch (option) {
1987 case REJECT_MAC_ADDR:
1988 /* Clear accepts frame bit at specified Other DA table entry */
1989 omc_table_reg =
1990 MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1991 omc_table_reg &= (0x0E << (8 * reg_offset));
1992
1993 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
1994 break;
1995
1996 case ACCEPT_MAC_ADDR:
1997 /* Set accepts frame bit at specified Other DA table entry */
1998 omc_table_reg =
1999 MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
2000 omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
2001
2002 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
2003 break;
2004
2005 default:
2006 return false;
2007 }
2008 return true;
2009 }
2010 #endif
2011
2012 /*******************************************************************************
2013 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2014 *
2015 * DESCRIPTION:
2016 * Go through all the DA filter tables (Unicast, Special Multicast & Other
2017 * Multicast) and set each entry to 0.
2018 *
2019 * INPUT:
2020 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2021 *
2022 * OUTPUT:
2023 * Multicast and Unicast packets are rejected.
2024 *
2025 * RETURN:
2026 * None.
2027 *
2028 *******************************************************************************/
2029 static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
2030 {
2031 int table_index;
2032
2033 /* Clear DA filter unicast table (Ex_dFUT) */
2034 for (table_index = 0; table_index <= 0xC; table_index += 4)
2035 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
2036 (eth_port_num) + table_index), 0);
2037
2038 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2039 /* Clear DA filter special multicast table (Ex_dFSMT) */
2040 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
2041 /* Clear DA filter other multicast table (Ex_dFOMT) */
2042 MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
2043 }
2044 }
2045
2046 /*******************************************************************************
2047 * eth_clear_mib_counters - Clear all MIB counters
2048 *
2049 * DESCRIPTION:
2050 * This function clears all MIB counters of a specific ethernet port.
2051 * A read from the MIB counter will reset the counter.
2052 *
2053 * INPUT:
2054 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2055 *
2056 * OUTPUT:
2057 * After reading all MIB counters, the counters resets.
2058 *
2059 * RETURN:
2060 * MIB counter value.
2061 *
2062 *******************************************************************************/
2063 static void eth_clear_mib_counters (ETH_PORT eth_port_num)
2064 {
2065 int i;
2066 unsigned int dummy;
2067
2068 /* Perform dummy reads from MIB counters */
2069 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2070 i += 4)
2071 dummy = MV_REG_READ ((MV64460_ETH_MIB_COUNTERS_BASE
2072 (eth_port_num) + i));
2073
2074 return;
2075 }
2076
2077 /*******************************************************************************
2078 * eth_read_mib_counter - Read a MIB counter
2079 *
2080 * DESCRIPTION:
2081 * This function reads a MIB counter of a specific ethernet port.
2082 * NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
2083 * following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
2084 * register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
2085 * ETH_MIB_GOOD_OCTETS_SENT_HIGH
2086 *
2087 * INPUT:
2088 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2089 * unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros).
2090 *
2091 * OUTPUT:
2092 * After reading the MIB counter, the counter resets.
2093 *
2094 * RETURN:
2095 * MIB counter value.
2096 *
2097 *******************************************************************************/
2098 unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
2099 unsigned int mib_offset)
2100 {
2101 return (MV_REG_READ (MV64460_ETH_MIB_COUNTERS_BASE (eth_port_num)
2102 + mib_offset));
2103 }
2104
2105 /*******************************************************************************
2106 * ethernet_phy_set - Set the ethernet port PHY address.
2107 *
2108 * DESCRIPTION:
2109 * This routine set the ethernet port PHY address according to given
2110 * parameter.
2111 *
2112 * INPUT:
2113 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2114 *
2115 * OUTPUT:
2116 * Set PHY Address Register with given PHY address parameter.
2117 *
2118 * RETURN:
2119 * None.
2120 *
2121 *******************************************************************************/
2122 static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
2123 {
2124 unsigned int reg_data;
2125
2126 reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
2127
2128 reg_data &= ~(0x1F << (5 * eth_port_num));
2129 reg_data |= (phy_addr << (5 * eth_port_num));
2130
2131 MV_REG_WRITE (MV64460_ETH_PHY_ADDR_REG, reg_data);
2132
2133 return;
2134 }
2135
2136 /*******************************************************************************
2137 * ethernet_phy_get - Get the ethernet port PHY address.
2138 *
2139 * DESCRIPTION:
2140 * This routine returns the given ethernet port PHY address.
2141 *
2142 * INPUT:
2143 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2144 *
2145 * OUTPUT:
2146 * None.
2147 *
2148 * RETURN:
2149 * PHY address.
2150 *
2151 *******************************************************************************/
2152 static int ethernet_phy_get (ETH_PORT eth_port_num)
2153 {
2154 unsigned int reg_data;
2155
2156 reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
2157
2158 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2159 }
2160
2161 /*******************************************************************************
2162 * ethernet_phy_reset - Reset Ethernet port PHY.
2163 *
2164 * DESCRIPTION:
2165 * This routine utilize the SMI interface to reset the ethernet port PHY.
2166 * The routine waits until the link is up again or link up is timeout.
2167 *
2168 * INPUT:
2169 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2170 *
2171 * OUTPUT:
2172 * The ethernet port PHY renew its link.
2173 *
2174 * RETURN:
2175 * None.
2176 *
2177 *******************************************************************************/
2178 static bool ethernet_phy_reset (ETH_PORT eth_port_num)
2179 {
2180 unsigned int time_out = 50;
2181 unsigned int phy_reg_data;
2182
2183 /* Reset the PHY */
2184 eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
2185 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2186 eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
2187
2188 /* Poll on the PHY LINK */
2189 do {
2190 eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
2191
2192 if (time_out-- == 0)
2193 return false;
2194 }
2195 while (!(phy_reg_data & 0x20));
2196
2197 return true;
2198 }
2199
2200 /*******************************************************************************
2201 * eth_port_reset - Reset Ethernet port
2202 *
2203 * DESCRIPTION:
2204 * This routine resets the chip by aborting any SDMA engine activity and
2205 * clearing the MIB counters. The Receiver and the Transmit unit are in
2206 * idle state after this command is performed and the port is disabled.
2207 *
2208 * INPUT:
2209 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2210 *
2211 * OUTPUT:
2212 * Channel activity is halted.
2213 *
2214 * RETURN:
2215 * None.
2216 *
2217 *******************************************************************************/
2218 static void eth_port_reset (ETH_PORT eth_port_num)
2219 {
2220 unsigned int reg_data;
2221
2222 /* Stop Tx port activity. Check port Tx activity. */
2223 reg_data =
2224 MV_REG_READ (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
2225 (eth_port_num));
2226
2227 if (reg_data & 0xFF) {
2228 /* Issue stop command for active channels only */
2229 MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
2230 (eth_port_num), (reg_data << 8));
2231
2232 /* Wait for all Tx activity to terminate. */
2233 do {
2234 /* Check port cause register that all Tx queues are stopped */
2235 reg_data =
2236 MV_REG_READ
2237 (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
2238 (eth_port_num));
2239 }
2240 while (reg_data & 0xFF);
2241 }
2242
2243 /* Stop Rx port activity. Check port Rx activity. */
2244 reg_data =
2245 MV_REG_READ (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
2246 (eth_port_num));
2247
2248 if (reg_data & 0xFF) {
2249 /* Issue stop command for active channels only */
2250 MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
2251 (eth_port_num), (reg_data << 8));
2252
2253 /* Wait for all Rx activity to terminate. */
2254 do {
2255 /* Check port cause register that all Rx queues are stopped */
2256 reg_data =
2257 MV_REG_READ
2258 (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
2259 (eth_port_num));
2260 }
2261 while (reg_data & 0xFF);
2262 }
2263
2264
2265 /* Clear all MIB counters */
2266 eth_clear_mib_counters (eth_port_num);
2267
2268 /* Reset the Enable bit in the Configuration Register */
2269 reg_data =
2270 MV_REG_READ (MV64460_ETH_PORT_SERIAL_CONTROL_REG
2271 (eth_port_num));
2272 reg_data &= ~ETH_SERIAL_PORT_ENABLE;
2273 MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
2274 reg_data);
2275
2276 return;
2277 }
2278
2279 #if 0 /* Not needed here */
2280 /*******************************************************************************
2281 * ethernet_set_config_reg - Set specified bits in configuration register.
2282 *
2283 * DESCRIPTION:
2284 * This function sets specified bits in the given ethernet
2285 * configuration register.
2286 *
2287 * INPUT:
2288 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2289 * unsigned int value 32 bit value.
2290 *
2291 * OUTPUT:
2292 * The set bits in the value parameter are set in the configuration
2293 * register.
2294 *
2295 * RETURN:
2296 * None.
2297 *
2298 *******************************************************************************/
2299 static void ethernet_set_config_reg (ETH_PORT eth_port_num,
2300 unsigned int value)
2301 {
2302 unsigned int eth_config_reg;
2303
2304 eth_config_reg =
2305 MV_REG_READ (MV64460_ETH_PORT_CONFIG_REG (eth_port_num));
2306 eth_config_reg |= value;
2307 MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
2308 eth_config_reg);
2309
2310 return;
2311 }
2312 #endif
2313
2314 #if 0 /* FIXME */
2315 /*******************************************************************************
2316 * ethernet_reset_config_reg - Reset specified bits in configuration register.
2317 *
2318 * DESCRIPTION:
2319 * This function resets specified bits in the given Ethernet
2320 * configuration register.
2321 *
2322 * INPUT:
2323 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2324 * unsigned int value 32 bit value.
2325 *
2326 * OUTPUT:
2327 * The set bits in the value parameter are reset in the configuration
2328 * register.
2329 *
2330 * RETURN:
2331 * None.
2332 *
2333 *******************************************************************************/
2334 static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
2335 unsigned int value)
2336 {
2337 unsigned int eth_config_reg;
2338
2339 eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
2340 (eth_port_num));
2341 eth_config_reg &= ~value;
2342 MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
2343 eth_config_reg);
2344
2345 return;
2346 }
2347 #endif
2348
2349 #if 0 /* Not needed here */
2350 /*******************************************************************************
2351 * ethernet_get_config_reg - Get the port configuration register
2352 *
2353 * DESCRIPTION:
2354 * This function returns the configuration register value of the given
2355 * ethernet port.
2356 *
2357 * INPUT:
2358 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2359 *
2360 * OUTPUT:
2361 * None.
2362 *
2363 * RETURN:
2364 * Port configuration register value.
2365 *
2366 *******************************************************************************/
2367 static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
2368 {
2369 unsigned int eth_config_reg;
2370
2371 eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
2372 (eth_port_num));
2373 return eth_config_reg;
2374 }
2375
2376 #endif
2377
2378 /*******************************************************************************
2379 * eth_port_read_smi_reg - Read PHY registers
2380 *
2381 * DESCRIPTION:
2382 * This routine utilize the SMI interface to interact with the PHY in
2383 * order to perform PHY register read.
2384 *
2385 * INPUT:
2386 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2387 * unsigned int phy_reg PHY register address offset.
2388 * unsigned int *value Register value buffer.
2389 *
2390 * OUTPUT:
2391 * Write the value of a specified PHY register into given buffer.
2392 *
2393 * RETURN:
2394 * false if the PHY is busy or read data is not in valid state.
2395 * true otherwise.
2396 *
2397 *******************************************************************************/
2398 static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
2399 unsigned int phy_reg, unsigned int *value)
2400 {
2401 unsigned int reg_value;
2402 unsigned int time_out = PHY_BUSY_TIMEOUT;
2403 int phy_addr;
2404
2405 phy_addr = ethernet_phy_get (eth_port_num);
2406 /* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/
2407
2408 /* first check that it is not busy */
2409 do {
2410 reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
2411 if (time_out-- == 0) {
2412 return false;
2413 }
2414 }
2415 while (reg_value & ETH_SMI_BUSY);
2416
2417 /* not busy */
2418
2419 MV_REG_WRITE (MV64460_ETH_SMI_REG,
2420 (phy_addr << 16) | (phy_reg << 21) |
2421 ETH_SMI_OPCODE_READ);
2422
2423 time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */
2424
2425 do {
2426 reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
2427 if (time_out-- == 0) {
2428 return false;
2429 }
2430 }
2431 while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
2432
2433 /* Wait for the data to update in the SMI register */
2434 #define PHY_UPDATE_TIMEOUT 10000
2435 for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
2436
2437 reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
2438
2439 *value = reg_value & 0xffff;
2440
2441 return true;
2442 }
2443
2444 /*******************************************************************************
2445 * eth_port_write_smi_reg - Write to PHY registers
2446 *
2447 * DESCRIPTION:
2448 * This routine utilize the SMI interface to interact with the PHY in
2449 * order to perform writes to PHY registers.
2450 *
2451 * INPUT:
2452 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2453 * unsigned int phy_reg PHY register address offset.
2454 * unsigned int value Register value.
2455 *
2456 * OUTPUT:
2457 * Write the given value to the specified PHY register.
2458 *
2459 * RETURN:
2460 * false if the PHY is busy.
2461 * true otherwise.
2462 *
2463 *******************************************************************************/
2464 static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
2465 unsigned int phy_reg, unsigned int value)
2466 {
2467 unsigned int reg_value;
2468 unsigned int time_out = PHY_BUSY_TIMEOUT;
2469 int phy_addr;
2470
2471 phy_addr = ethernet_phy_get (eth_port_num);
2472
2473 /* first check that it is not busy */
2474 do {
2475 reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
2476 if (time_out-- == 0) {
2477 return false;
2478 }
2479 }
2480 while (reg_value & ETH_SMI_BUSY);
2481
2482 /* not busy */
2483 MV_REG_WRITE (MV64460_ETH_SMI_REG,
2484 (phy_addr << 16) | (phy_reg << 21) |
2485 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2486 return true;
2487 }
2488
2489 /*******************************************************************************
2490 * eth_set_access_control - Config address decode parameters for Ethernet unit
2491 *
2492 * DESCRIPTION:
2493 * This function configures the address decode parameters for the Gigabit
2494 * Ethernet Controller according the given parameters struct.
2495 *
2496 * INPUT:
2497 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2498 * ETH_WIN_PARAM *param Address decode parameter struct.
2499 *
2500 * OUTPUT:
2501 * An access window is opened using the given access parameters.
2502 *
2503 * RETURN:
2504 * None.
2505 *
2506 *******************************************************************************/
2507 static void eth_set_access_control (ETH_PORT eth_port_num,
2508 ETH_WIN_PARAM * param)
2509 {
2510 unsigned int access_prot_reg;
2511
2512 /* Set access control register */
2513 access_prot_reg = MV_REG_READ (MV64460_ETH_ACCESS_PROTECTION_REG
2514 (eth_port_num));
2515 access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */
2516 access_prot_reg |= (param->access_ctrl << (param->win * 2));
2517 MV_REG_WRITE (MV64460_ETH_ACCESS_PROTECTION_REG (eth_port_num),
2518 access_prot_reg);
2519
2520 /* Set window Size reg (SR) */
2521 MV_REG_WRITE ((MV64460_ETH_SIZE_REG_0 +
2522 (ETH_SIZE_REG_GAP * param->win)),
2523 (((param->size / 0x10000) - 1) << 16));
2524
2525 /* Set window Base address reg (BA) */
2526 MV_REG_WRITE ((MV64460_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
2527 (param->target | param->attributes | param->base_addr));
2528 /* High address remap reg (HARR) */
2529 if (param->win < 4)
2530 MV_REG_WRITE ((MV64460_ETH_HIGH_ADDR_REMAP_REG_0 +
2531 (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
2532 param->high_addr);
2533
2534 /* Base address enable reg (BARER) */
2535 if (param->enable == 1)
2536 MV_RESET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
2537 (1 << param->win));
2538 else
2539 MV_SET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
2540 (1 << param->win));
2541 }
2542
2543 /*******************************************************************************
2544 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
2545 *
2546 * DESCRIPTION:
2547 * This function prepares a Rx chained list of descriptors and packet
2548 * buffers in a form of a ring. The routine must be called after port
2549 * initialization routine and before port start routine.
2550 * The Ethernet SDMA engine uses CPU bus addresses to access the various
2551 * devices in the system (i.e. DRAM). This function uses the ethernet
2552 * struct 'virtual to physical' routine (set by the user) to set the ring
2553 * with physical addresses.
2554 *
2555 * INPUT:
2556 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2557 * ETH_QUEUE rx_queue Number of Rx queue.
2558 * int rx_desc_num Number of Rx descriptors
2559 * int rx_buff_size Size of Rx buffer
2560 * unsigned int rx_desc_base_addr Rx descriptors memory area base addr.
2561 * unsigned int rx_buff_base_addr Rx buffer memory area base addr.
2562 *
2563 * OUTPUT:
2564 * The routine updates the Ethernet port control struct with information
2565 * regarding the Rx descriptors and buffers.
2566 *
2567 * RETURN:
2568 * false if the given descriptors memory area is not aligned according to
2569 * Ethernet SDMA specifications.
2570 * true otherwise.
2571 *
2572 *******************************************************************************/
2573 static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
2574 ETH_QUEUE rx_queue,
2575 int rx_desc_num,
2576 int rx_buff_size,
2577 unsigned int rx_desc_base_addr,
2578 unsigned int rx_buff_base_addr)
2579 {
2580 ETH_RX_DESC *p_rx_desc;
2581 ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */
2582 unsigned int buffer_addr;
2583 int ix; /* a counter */
2584
2585
2586 p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
2587 p_rx_prev_desc = p_rx_desc;
2588 buffer_addr = rx_buff_base_addr;
2589
2590 /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
2591 if (rx_buff_base_addr & 0xF)
2592 return false;
2593
2594 /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */
2595 if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
2596 return false;
2597
2598 /* Rx buffers must be 64-bit aligned. */
2599 if ((rx_buff_base_addr + rx_buff_size) & 0x7)
2600 return false;
2601
2602 /* initialize the Rx descriptors ring */
2603 for (ix = 0; ix < rx_desc_num; ix++) {
2604 p_rx_desc->buf_size = rx_buff_size;
2605 p_rx_desc->byte_cnt = 0x0000;
2606 p_rx_desc->cmd_sts =
2607 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2608 p_rx_desc->next_desc_ptr =
2609 ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
2610 p_rx_desc->buf_ptr = buffer_addr;
2611 p_rx_desc->return_info = 0x00000000;
2612 D_CACHE_FLUSH_LINE (p_rx_desc, 0);
2613 buffer_addr += rx_buff_size;
2614 p_rx_prev_desc = p_rx_desc;
2615 p_rx_desc = (ETH_RX_DESC *)
2616 ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
2617 }
2618
2619 /* Closing Rx descriptors ring */
2620 p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
2621 D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
2622
2623 /* Save Rx desc pointer to driver struct. */
2624 CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
2625 USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
2626
2627 p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
2628 (ETH_RX_DESC *) rx_desc_base_addr;
2629 p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
2630 rx_desc_num * RX_DESC_ALIGNED_SIZE;
2631
2632 p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
2633
2634 return true;
2635 }
2636
2637 /*******************************************************************************
2638 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
2639 *
2640 * DESCRIPTION:
2641 * This function prepares a Tx chained list of descriptors and packet
2642 * buffers in a form of a ring. The routine must be called after port
2643 * initialization routine and before port start routine.
2644 * The Ethernet SDMA engine uses CPU bus addresses to access the various
2645 * devices in the system (i.e. DRAM). This function uses the ethernet
2646 * struct 'virtual to physical' routine (set by the user) to set the ring
2647 * with physical addresses.
2648 *
2649 * INPUT:
2650 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2651 * ETH_QUEUE tx_queue Number of Tx queue.
2652 * int tx_desc_num Number of Tx descriptors
2653 * int tx_buff_size Size of Tx buffer
2654 * unsigned int tx_desc_base_addr Tx descriptors memory area base addr.
2655 * unsigned int tx_buff_base_addr Tx buffer memory area base addr.
2656 *
2657 * OUTPUT:
2658 * The routine updates the Ethernet port control struct with information
2659 * regarding the Tx descriptors and buffers.
2660 *
2661 * RETURN:
2662 * false if the given descriptors memory area is not aligned according to
2663 * Ethernet SDMA specifications.
2664 * true otherwise.
2665 *
2666 *******************************************************************************/
2667 static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
2668 ETH_QUEUE tx_queue,
2669 int tx_desc_num,
2670 int tx_buff_size,
2671 unsigned int tx_desc_base_addr,
2672 unsigned int tx_buff_base_addr)
2673 {
2674
2675 ETH_TX_DESC *p_tx_desc;
2676 ETH_TX_DESC *p_tx_prev_desc;
2677 unsigned int buffer_addr;
2678 int ix; /* a counter */
2679
2680
2681 /* save the first desc pointer to link with the last descriptor */
2682 p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
2683 p_tx_prev_desc = p_tx_desc;
2684 buffer_addr = tx_buff_base_addr;
2685
2686 /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
2687 if (tx_buff_base_addr & 0xF)
2688 return false;
2689
2690 /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */
2691 if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
2692 || (tx_buff_size < TX_BUFFER_MIN_SIZE))
2693 return false;
2694
2695 /* Initialize the Tx descriptors ring */
2696 for (ix = 0; ix < tx_desc_num; ix++) {
2697 p_tx_desc->byte_cnt = 0x0000;
2698 p_tx_desc->l4i_chk = 0x0000;
2699 p_tx_desc->cmd_sts = 0x00000000;
2700 p_tx_desc->next_desc_ptr =
2701 ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
2702
2703 p_tx_desc->buf_ptr = buffer_addr;
2704 p_tx_desc->return_info = 0x00000000;
2705 D_CACHE_FLUSH_LINE (p_tx_desc, 0);
2706 buffer_addr += tx_buff_size;
2707 p_tx_prev_desc = p_tx_desc;
2708 p_tx_desc = (ETH_TX_DESC *)
2709 ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
2710
2711 }
2712 /* Closing Tx descriptors ring */
2713 p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
2714 D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
2715 /* Set Tx desc pointer in driver struct. */
2716 CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
2717 USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
2718
2719 /* Init Tx ring base and size parameters */
2720 p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
2721 (ETH_TX_DESC *) tx_desc_base_addr;
2722 p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
2723 (tx_desc_num * TX_DESC_ALIGNED_SIZE);
2724
2725 /* Add the queue to the list of Tx queues of this port */
2726 p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
2727
2728 return true;
2729 }
2730
2731 /*******************************************************************************
2732 * eth_port_send - Send an Ethernet packet
2733 *
2734 * DESCRIPTION:
2735 * This routine send a given packet described by p_pktinfo parameter. It
2736 * supports transmitting of a packet spaned over multiple buffers. The
2737 * routine updates 'curr' and 'first' indexes according to the packet
2738 * segment passed to the routine. In case the packet segment is first,
2739 * the 'first' index is update. In any case, the 'curr' index is updated.
2740 * If the routine get into Tx resource error it assigns 'curr' index as
2741 * 'first'. This way the function can abort Tx process of multiple
2742 * descriptors per packet.
2743 *
2744 * INPUT:
2745 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2746 * ETH_QUEUE tx_queue Number of Tx queue.
2747 * PKT_INFO *p_pkt_info User packet buffer.
2748 *
2749 * OUTPUT:
2750 * Tx ring 'curr' and 'first' indexes are updated.
2751 *
2752 * RETURN:
2753 * ETH_QUEUE_FULL in case of Tx resource error.
2754 * ETH_ERROR in case the routine can not access Tx desc ring.
2755 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2756 * ETH_OK otherwise.
2757 *
2758 *******************************************************************************/
2759 static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
2760 ETH_QUEUE tx_queue,
2761 PKT_INFO * p_pkt_info)
2762 {
2763 volatile ETH_TX_DESC *p_tx_desc_first;
2764 volatile ETH_TX_DESC *p_tx_desc_curr;
2765 volatile ETH_TX_DESC *p_tx_next_desc_curr;
2766 volatile ETH_TX_DESC *p_tx_desc_used;
2767 unsigned int command_status;
2768
2769 /* Do not process Tx ring in case of Tx ring resource error */
2770 if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
2771 return ETH_QUEUE_FULL;
2772
2773 /* Get the Tx Desc ring indexes */
2774 CURR_TFD_GET (p_tx_desc_curr, tx_queue);
2775 USED_TFD_GET (p_tx_desc_used, tx_queue);
2776
2777 if (p_tx_desc_curr == NULL)
2778 return ETH_ERROR;
2779
2780 /* The following parameters are used to save readings from memory */
2781 p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
2782 command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
2783
2784 if (command_status & (ETH_TX_FIRST_DESC)) {
2785 /* Update first desc */
2786 FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
2787 p_tx_desc_first = p_tx_desc_curr;
2788 } else {
2789 FIRST_TFD_GET (p_tx_desc_first, tx_queue);
2790 command_status |= ETH_BUFFER_OWNED_BY_DMA;
2791 }
2792
2793 /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
2794 /* boundary. We use the memory allocated for Tx descriptor. This memory */
2795 /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
2796 if (p_pkt_info->byte_cnt <= 8) {
2797 printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */
2798 return ETH_ERROR;
2799
2800 p_tx_desc_curr->buf_ptr =
2801 (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
2802 eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
2803 p_pkt_info->byte_cnt);
2804 } else
2805 p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
2806
2807 p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
2808 p_tx_desc_curr->return_info = p_pkt_info->return_info;
2809
2810 if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
2811 /* Set last desc with DMA ownership and interrupt enable. */
2812 p_tx_desc_curr->cmd_sts = command_status |
2813 ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
2814
2815 if (p_tx_desc_curr != p_tx_desc_first)
2816 p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
2817
2818 /* Flush CPU pipe */
2819
2820 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
2821 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
2822 CPU_PIPE_FLUSH;
2823
2824 /* Apply send command */
2825 ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
2826
2827 /* Finish Tx packet. Update first desc in case of Tx resource error */
2828 p_tx_desc_first = p_tx_next_desc_curr;
2829 FIRST_TFD_SET (p_tx_desc_first, tx_queue);
2830
2831 } else {
2832 p_tx_desc_curr->cmd_sts = command_status;
2833 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
2834 }
2835
2836 /* Check for ring index overlap in the Tx desc ring */
2837 if (p_tx_next_desc_curr == p_tx_desc_used) {
2838 /* Update the current descriptor */
2839 CURR_TFD_SET (p_tx_desc_first, tx_queue);
2840
2841 p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
2842 return ETH_QUEUE_LAST_RESOURCE;
2843 } else {
2844 /* Update the current descriptor */
2845 CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
2846 return ETH_OK;
2847 }
2848 }
2849
2850 /*******************************************************************************
2851 * eth_tx_return_desc - Free all used Tx descriptors
2852 *
2853 * DESCRIPTION:
2854 * This routine returns the transmitted packet information to the caller.
2855 * It uses the 'first' index to support Tx desc return in case a transmit
2856 * of a packet spanned over multiple buffer still in process.
2857 * In case the Tx queue was in "resource error" condition, where there are
2858 * no available Tx resources, the function resets the resource error flag.
2859 *
2860 * INPUT:
2861 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2862 * ETH_QUEUE tx_queue Number of Tx queue.
2863 * PKT_INFO *p_pkt_info User packet buffer.
2864 *
2865 * OUTPUT:
2866 * Tx ring 'first' and 'used' indexes are updated.
2867 *
2868 * RETURN:
2869 * ETH_ERROR in case the routine can not access Tx desc ring.
2870 * ETH_RETRY in case there is transmission in process.
2871 * ETH_END_OF_JOB if the routine has nothing to release.
2872 * ETH_OK otherwise.
2873 *
2874 *******************************************************************************/
2875 static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
2876 p_eth_port_ctrl,
2877 ETH_QUEUE tx_queue,
2878 PKT_INFO * p_pkt_info)
2879 {
2880 volatile ETH_TX_DESC *p_tx_desc_used = NULL;
2881 volatile ETH_TX_DESC *p_tx_desc_first = NULL;
2882 unsigned int command_status;
2883
2884
2885 /* Get the Tx Desc ring indexes */
2886 USED_TFD_GET (p_tx_desc_used, tx_queue);
2887 FIRST_TFD_GET (p_tx_desc_first, tx_queue);
2888
2889
2890 /* Sanity check */
2891 if (p_tx_desc_used == NULL)
2892 return ETH_ERROR;
2893
2894 command_status = p_tx_desc_used->cmd_sts;
2895
2896 /* Still transmitting... */
2897 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2898 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
2899 return ETH_RETRY;
2900 }
2901
2902 /* Stop release. About to overlap the current available Tx descriptor */
2903 if ((p_tx_desc_used == p_tx_desc_first) &&
2904 (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
2905 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
2906 return ETH_END_OF_JOB;
2907 }
2908
2909 /* Pass the packet information to the caller */
2910 p_pkt_info->cmd_sts = command_status;
2911 p_pkt_info->return_info = p_tx_desc_used->return_info;
2912 p_tx_desc_used->return_info = 0;
2913
2914 /* Update the next descriptor to release. */
2915 USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
2916
2917 /* Any Tx return cancels the Tx resource error status */
2918 if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
2919 p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
2920
2921 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
2922
2923 return ETH_OK;
2924
2925 }
2926
2927 /*******************************************************************************
2928 * eth_port_receive - Get received information from Rx ring.
2929 *
2930 * DESCRIPTION:
2931 * This routine returns the received data to the caller. There is no
2932 * data copying during routine operation. All information is returned
2933 * using pointer to packet information struct passed from the caller.
2934 * If the routine exhausts Rx ring resources then the resource error flag
2935 * is set.
2936 *
2937 * INPUT:
2938 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2939 * ETH_QUEUE rx_queue Number of Rx queue.
2940 * PKT_INFO *p_pkt_info User packet buffer.
2941 *
2942 * OUTPUT:
2943 * Rx ring current and used indexes are updated.
2944 *
2945 * RETURN:
2946 * ETH_ERROR in case the routine can not access Rx desc ring.
2947 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2948 * ETH_END_OF_JOB if there is no received data.
2949 * ETH_OK otherwise.
2950 *
2951 *******************************************************************************/
2952 static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
2953 ETH_QUEUE rx_queue,
2954 PKT_INFO * p_pkt_info)
2955 {
2956 volatile ETH_RX_DESC *p_rx_curr_desc;
2957 volatile ETH_RX_DESC *p_rx_next_curr_desc;
2958 volatile ETH_RX_DESC *p_rx_used_desc;
2959 unsigned int command_status;
2960
2961 /* Do not process Rx ring in case of Rx ring resource error */
2962 if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
2963 printf ("\nRx Queue is full ...\n");
2964 return ETH_QUEUE_FULL;
2965 }
2966
2967 /* Get the Rx Desc ring 'curr and 'used' indexes */
2968 CURR_RFD_GET (p_rx_curr_desc, rx_queue);
2969 USED_RFD_GET (p_rx_used_desc, rx_queue);
2970
2971 /* Sanity check */
2972 if (p_rx_curr_desc == NULL)
2973 return ETH_ERROR;
2974
2975 /* The following parameters are used to save readings from memory */
2976 p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
2977 command_status = p_rx_curr_desc->cmd_sts;
2978
2979 /* Nothing to receive... */
2980 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2981 /* DP(printf("Rx: command_status: %08x\n", command_status)); */
2982 D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
2983 /* DP(printf("\nETH_END_OF_JOB ...\n"));*/
2984 return ETH_END_OF_JOB;
2985 }
2986
2987 p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
2988 p_pkt_info->cmd_sts = command_status;
2989 p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
2990 p_pkt_info->return_info = p_rx_curr_desc->return_info;
2991 p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */
2992
2993 /* Clean the return info field to indicate that the packet has been */
2994 /* moved to the upper layers */
2995 p_rx_curr_desc->return_info = 0;
2996
2997 /* Update 'curr' in data structure */
2998 CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
2999
3000 /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
3001 if (p_rx_next_curr_desc == p_rx_used_desc)
3002 p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
3003
3004 D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
3005 CPU_PIPE_FLUSH;
3006 return ETH_OK;
3007 }
3008
3009 /*******************************************************************************
3010 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
3011 *
3012 * DESCRIPTION:
3013 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
3014 * next 'used' descriptor and attached the returned buffer to it.
3015 * In case the Rx ring was in "resource error" condition, where there are
3016 * no available Rx resources, the function resets the resource error flag.
3017 *
3018 * INPUT:
3019 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
3020 * ETH_QUEUE rx_queue Number of Rx queue.
3021 * PKT_INFO *p_pkt_info Information on the returned buffer.
3022 *
3023 * OUTPUT:
3024 * New available Rx resource in Rx descriptor ring.
3025 *
3026 * RETURN:
3027 * ETH_ERROR in case the routine can not access Rx desc ring.
3028 * ETH_OK otherwise.
3029 *
3030 *******************************************************************************/
3031 static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
3032 p_eth_port_ctrl,
3033 ETH_QUEUE rx_queue,
3034 PKT_INFO * p_pkt_info)
3035 {
3036 volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */
3037
3038 /* Get 'used' Rx descriptor */
3039 USED_RFD_GET (p_used_rx_desc, rx_queue);
3040
3041 /* Sanity check */
3042 if (p_used_rx_desc == NULL)
3043 return ETH_ERROR;
3044
3045 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
3046 p_used_rx_desc->return_info = p_pkt_info->return_info;
3047 p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
3048 p_used_rx_desc->buf_size = MV64460_RX_BUFFER_SIZE; /* Reset Buffer size */
3049
3050 /* Flush the write pipe */
3051 CPU_PIPE_FLUSH;
3052
3053 /* Return the descriptor to DMA ownership */
3054 p_used_rx_desc->cmd_sts =
3055 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
3056
3057 /* Flush descriptor and CPU pipe */
3058 D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
3059 CPU_PIPE_FLUSH;
3060
3061 /* Move the used descriptor pointer to the next descriptor */
3062 USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
3063
3064 /* Any Rx return cancels the Rx resource error status */
3065 if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
3066 p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
3067
3068 return ETH_OK;
3069 }
3070
3071 /*******************************************************************************
3072 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
3073 *
3074 * DESCRIPTION:
3075 * This routine sets the RX coalescing interrupt mechanism parameter.
3076 * This parameter is a timeout counter, that counts in 64 t_clk
3077 * chunks ; that when timeout event occurs a maskable interrupt
3078 * occurs.
3079 * The parameter is calculated using the tClk of the MV-643xx chip
3080 * , and the required delay of the interrupt in usec.
3081 *
3082 * INPUT:
3083 * ETH_PORT eth_port_num Ethernet port number
3084 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
3085 * unsigned int delay Delay in usec
3086 *
3087 * OUTPUT:
3088 * Interrupt coalescing mechanism value is set in MV-643xx chip.
3089 *
3090 * RETURN:
3091 * The interrupt coalescing value set in the gigE port.
3092 *
3093 *******************************************************************************/
3094 #if 0 /* FIXME */
3095 static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
3096 unsigned int t_clk,
3097 unsigned int delay)
3098 {
3099 unsigned int coal;
3100
3101 coal = ((t_clk / 1000000) * delay) / 64;
3102 /* Set RX Coalescing mechanism */
3103 MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
3104 ((coal & 0x3fff) << 8) |
3105 (MV_REG_READ
3106 (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num))
3107 & 0xffc000ff));
3108 return coal;
3109 }
3110
3111 #endif
3112 /*******************************************************************************
3113 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
3114 *
3115 * DESCRIPTION:
3116 * This routine sets the TX coalescing interrupt mechanism parameter.
3117 * This parameter is a timeout counter, that counts in 64 t_clk
3118 * chunks ; that when timeout event occurs a maskable interrupt
3119 * occurs.
3120 * The parameter is calculated using the t_cLK frequency of the
3121 * MV-643xx chip and the required delay in the interrupt in uSec
3122 *
3123 * INPUT:
3124 * ETH_PORT eth_port_num Ethernet port number
3125 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
3126 * unsigned int delay Delay in uSeconds
3127 *
3128 * OUTPUT:
3129 * Interrupt coalescing mechanism value is set in MV-643xx chip.
3130 *
3131 * RETURN:
3132 * The interrupt coalescing value set in the gigE port.
3133 *
3134 *******************************************************************************/
3135 #if 0 /* FIXME */
3136 static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
3137 unsigned int t_clk,
3138 unsigned int delay)
3139 {
3140 unsigned int coal;
3141
3142 coal = ((t_clk / 1000000) * delay) / 64;
3143 /* Set TX Coalescing mechanism */
3144 MV_REG_WRITE (MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
3145 coal << 4);
3146 return coal;
3147 }
3148 #endif
3149
3150 /*******************************************************************************
3151 * eth_b_copy - Copy bytes from source to destination
3152 *
3153 * DESCRIPTION:
3154 * This function supports the eight bytes limitation on Tx buffer size.
3155 * The routine will zero eight bytes starting from the destination address
3156 * followed by copying bytes from the source address to the destination.
3157 *
3158 * INPUT:
3159 * unsigned int src_addr 32 bit source address.
3160 * unsigned int dst_addr 32 bit destination address.
3161 * int byte_count Number of bytes to copy.
3162 *
3163 * OUTPUT:
3164 * See description.
3165 *
3166 * RETURN:
3167 * None.
3168 *
3169 *******************************************************************************/
3170 static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
3171 int byte_count)
3172 {
3173 /* Zero the dst_addr area */
3174 *(unsigned int *) dst_addr = 0x0;
3175
3176 while (byte_count != 0) {
3177 *(char *) dst_addr = *(char *) src_addr;
3178 dst_addr++;
3179 src_addr++;
3180 byte_count--;
3181 }
3182 }
"Das U-Boot" Source Tree