board/Marvell/gplugd/gplugd.c

   1 /*
   2  * (C) Copyright 2011
   3  * eInfochips Ltd. <www.einfochips.com>
   4  * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
   5  *
   6  * Based on Aspenite:
   7  * (C) Copyright 2010
   8  * Marvell Semiconductor <www.marvell.com>
   9  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  10  * Contributor: Mahavir Jain <mjain@marvell.com>
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14
  15 #include <common.h>
  16 #include <mvmfp.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/mfp.h>
  19 #include <asm/arch/armada100.h>
  20 #include <asm/gpio.h>
  21 #include <miiphy.h>
  22
  23 #ifdef CONFIG_ARMADA100_FEC
  24 #include <net.h>
  25 #include <netdev.h>
  26 #endif /* CONFIG_ARMADA100_FEC */
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 int board_early_init_f(void)
  31 {
  32         u32 mfp_cfg[] = {
  33                 /* I2C */
  34                 MFP105_CI2C_SDA,
  35                 MFP106_CI2C_SCL,
  36
  37                 /* Enable Console on UART3 */
  38                 MFPO8_UART3_TXD,
  39                 MFPO9_UART3_RXD,
  40
  41                 /* Ethernet PHY Interface */
  42                 MFP086_ETH_TXCLK,
  43                 MFP087_ETH_TXEN,
  44                 MFP088_ETH_TXDQ3,
  45                 MFP089_ETH_TXDQ2,
  46                 MFP090_ETH_TXDQ1,
  47                 MFP091_ETH_TXDQ0,
  48                 MFP092_ETH_CRS,
  49                 MFP093_ETH_COL,
  50                 MFP094_ETH_RXCLK,
  51                 MFP095_ETH_RXER,
  52                 MFP096_ETH_RXDQ3,
  53                 MFP097_ETH_RXDQ2,
  54                 MFP098_ETH_RXDQ1,
  55                 MFP099_ETH_RXDQ0,
  56                 MFP100_ETH_MDC,
  57                 MFP101_ETH_MDIO,
  58                 MFP103_ETH_RXDV,
  59
  60                 /* SSP2 */
  61                 MFP107_SSP2_RXD,
  62                 MFP108_SSP2_TXD,
  63                 MFP110_SSP2_CS,
  64                 MFP111_SSP2_CLK,
  65
  66                 MFP_EOC         /*End of configuration*/
  67         };
  68         /* configure MFP's */
  69         mfp_config(mfp_cfg);
  70         return 0;
  71 }
  72
  73 int board_init(void)
  74 {
  75         struct armd1apb2_registers *apb2_regs =
  76                 (struct armd1apb2_registers *)ARMD1_APBC2_BASE;
  77
  78         /* arch number of Board */
  79         gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD;
  80         /* adress of boot parameters */
  81         gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
  82         /* Assert PHY_RST# */
  83         gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_LOW);
  84         udelay(10);
  85         /* Deassert PHY_RST# */
  86         gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH);
  87
  88         /* Enable SSP2 clock */
  89         writel(SSP2_APBCLK | SSP2_FNCLK, &apb2_regs->ssp2_clkrst);
  90         return 0;
  91 }
  92
  93 #ifdef CONFIG_ARMADA100_FEC
  94 int board_eth_init(bd_t *bis)
  95 {
  96         struct armd1apmu_registers *apmu_regs =
  97                 (struct armd1apmu_registers *)ARMD1_APMU_BASE;
  98
  99         /* Enable clock of ethernet controller */
 100         writel(FE_CLK_RST | FE_CLK_ENA, &apmu_regs->fecrc);
 101
 102         return armada100_fec_register(ARMD1_FEC_BASE);
 103 }
 104
 105 #ifdef CONFIG_RESET_PHY_R
 106 /* Configure and initialize PHY chip 88E3015 */
 107 void reset_phy(void)
 108 {
 109         u16 phy_adr;
 110         const char *name = "armd-fec0";
 111
 112         if (miiphy_set_current_dev(name))
 113                 return;
 114
 115         /* command to read PHY dev address */
 116         if (miiphy_read(name, 0xff, 0xff, &phy_adr)) {
 117                 printf("Err..%s could not read PHY dev address\n", __func__);
 118                 return;
 119         }
 120
 121         /* Set Ethernet LED in TX blink mode */
 122         miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00);
 123         miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL);
 124
 125         /* reset the phy */
 126         miiphy_reset(name, phy_adr);
 127         debug("88E3015 Initialized on %s\n", name);
 128 }
 129 #endif /* CONFIG_RESET_PHY_R */
 130 #endif /* CONFIG_ARMADA100_FEC */