3 * Net Insight <www.netinsight.net>
4 * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
6 * Based on sheevaplug.c:
8 * Marvell Semiconductor <www.marvell.com>
9 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/soc.h>
18 #include <asm/arch/mpp.h>
21 DECLARE_GLOBAL_DATA_PTR
;
23 int board_early_init_f(void)
26 * default gpio configuration
27 * There are maximum 64 gpios controlled through 2 sets of registers
28 * the below configuration configures mainly initial LED status
30 mvebu_config_gpio(OPENRD_OE_VAL_LOW
,
32 OPENRD_OE_LOW
, OPENRD_OE_HIGH
);
34 /* Multi-Purpose Pins Functionality configuration */
35 static const u32 kwmpp_config
[] = {
49 MPP13_SD_CMD
, /* Alt UART1_TXD */
50 MPP14_SD_D0
, /* Alt UART1_RXD */
70 MPP34_GPIO
, /* UART1 / SD sel */
89 kirkwood_mpp_conf(kwmpp_config
, NULL
);
96 * arch number of board
98 #if defined(CONFIG_BOARD_IS_OPENRD_BASE)
99 gd
->bd
->bi_arch_number
= MACH_TYPE_OPENRD_BASE
;
100 #elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT)
101 gd
->bd
->bi_arch_number
= MACH_TYPE_OPENRD_CLIENT
;
102 #elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
103 gd
->bd
->bi_arch_number
= MACH_TYPE_OPENRD_ULTIMATE
;
106 /* adress of boot parameters */
107 gd
->bd
->bi_boot_params
= mvebu_sdram_bar(0) + 0x100;
111 #ifdef CONFIG_RESET_PHY_R
112 /* Configure and enable MV88E1116/88E1121 PHY */
113 void mv_phy_init(char *name
)
118 if (miiphy_set_current_dev(name
))
121 /* command to read PHY dev address */
122 if (miiphy_read(name
, 0xEE, 0xEE, (u16
*)&devadr
)) {
123 printf("Err..%s could not read PHY dev address\n", __func__
);
128 * Enable RGMII delay on Tx and Rx for CPU port
129 * Ref: sec 4.7.2 of chip datasheet
131 miiphy_write(name
, devadr
, MV88E1116_PGADR_REG
, 2);
132 miiphy_read(name
, devadr
, MV88E1116_MAC_CTRL_REG
, ®
);
133 reg
|= (MV88E1116_RGMII_RXTM_CTRL
| MV88E1116_RGMII_TXTM_CTRL
);
134 miiphy_write(name
, devadr
, MV88E1116_MAC_CTRL_REG
, reg
);
135 miiphy_write(name
, devadr
, MV88E1116_PGADR_REG
, 0);
138 miiphy_reset(name
, devadr
);
140 printf(PHY_NO
" Initialized on %s\n", name
);
145 mv_phy_init("egiga0");
147 #ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
148 /* Kirkwood ethernet driver is written with the assumption that in case
149 * of multiple PHYs, their addresses are consecutive. But unfortunately
150 * in case of OpenRD-Client, PHY addresses are not consecutive.*/
151 miiphy_write("egiga1", 0xEE, 0xEE, 24);
154 #if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \
155 defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
156 /* configure and initialize both PHY's */
157 mv_phy_init("egiga1");
160 #endif /* CONFIG_RESET_PHY_R */