board/Seagate/dockstar/dockstar.c

   1 /*
   2  * Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
   3  *
   4  * Based on sheevaplug.c originally written by
   5  * Prafulla Wadaskar <prafulla@marvell.com>
   6  * (C) Copyright 2009
   7  * Marvell Semiconductor <www.marvell.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <miiphy.h>
  14 #include <asm/arch/soc.h>
  15 #include <asm/arch/mpp.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/io.h>
  18 #include "dockstar.h"
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 int board_early_init_f(void)
  23 {
  24         /*
  25          * default gpio configuration
  26          * There are maximum 64 gpios controlled through 2 sets of registers
  27          * the  below configuration configures mainly initial LED status
  28          */
  29         mvebu_config_gpio(DOCKSTAR_OE_VAL_LOW,
  30                           DOCKSTAR_OE_VAL_HIGH,
  31                           DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
  32
  33         /* Multi-Purpose Pins Functionality configuration */
  34         static const u32 kwmpp_config[] = {
  35                 MPP0_NF_IO2,
  36                 MPP1_NF_IO3,
  37                 MPP2_NF_IO4,
  38                 MPP3_NF_IO5,
  39                 MPP4_NF_IO6,
  40                 MPP5_NF_IO7,
  41                 MPP6_SYSRST_OUTn,
  42                 MPP7_GPO,
  43                 MPP8_UART0_RTS,
  44                 MPP9_UART0_CTS,
  45                 MPP10_UART0_TXD,
  46                 MPP11_UART0_RXD,
  47                 MPP12_SD_CLK,
  48                 MPP13_SD_CMD,
  49                 MPP14_SD_D0,
  50                 MPP15_SD_D1,
  51                 MPP16_SD_D2,
  52                 MPP17_SD_D3,
  53                 MPP18_NF_IO0,
  54                 MPP19_NF_IO1,
  55                 MPP20_GPIO,
  56                 MPP21_GPIO,
  57                 MPP22_GPIO,
  58                 MPP23_GPIO,
  59                 MPP24_GPIO,
  60                 MPP25_GPIO,
  61                 MPP26_GPIO,
  62                 MPP27_GPIO,
  63                 MPP28_GPIO,
  64                 MPP29_TSMP9,
  65                 MPP30_GPIO,
  66                 MPP31_GPIO,
  67                 MPP32_GPIO,
  68                 MPP33_GPIO,
  69                 MPP34_GPIO,
  70                 MPP35_GPIO,
  71                 MPP36_GPIO,
  72                 MPP37_GPIO,
  73                 MPP38_GPIO,
  74                 MPP39_GPIO,
  75                 MPP40_GPIO,
  76                 MPP41_GPIO,
  77                 MPP42_GPIO,
  78                 MPP43_GPIO,
  79                 MPP44_GPIO,
  80                 MPP45_GPIO,
  81                 MPP46_GPIO,
  82                 MPP47_GPIO,
  83                 MPP48_GPIO,
  84                 MPP49_GPIO,
  85                 0
  86         };
  87         kirkwood_mpp_conf(kwmpp_config, NULL);
  88         return 0;
  89 }
  90
  91 int board_init(void)
  92 {
  93         /*
  94          * arch number of board
  95          */
  96         gd->bd->bi_arch_number = MACH_TYPE_DOCKSTAR;
  97
  98         /* address of boot parameters */
  99         gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
 100
 101         return 0;
 102 }
 103
 104 #ifdef CONFIG_RESET_PHY_R
 105 /* Configure and enable MV88E1116 PHY */
 106 void reset_phy(void)
 107 {
 108         u16 reg;
 109         u16 devadr;
 110         char *name = "egiga0";
 111
 112         if (miiphy_set_current_dev(name))
 113                 return;
 114
 115         /* command to read PHY dev address */
 116         if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
 117                 printf("Err..%s could not read PHY dev address\n",
 118                         __FUNCTION__);
 119                 return;
 120         }
 121
 122         /*
 123          * Enable RGMII delay on Tx and Rx for CPU port
 124          * Ref: sec 4.7.2 of chip datasheet
 125          */
 126         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
 127         miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
 128         reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
 129         miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
 130         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
 131
 132         /* reset the phy */
 133         miiphy_reset(name, devadr);
 134
 135         printf("88E1116 Initialized on %s\n", name);
 136 }
 137 #endif /* CONFIG_RESET_PHY_R */
 138
 139 #define GREEN_LED       (1 << 14)
 140 #define ORANGE_LED      (1 << 15)
 141 #define BOTH_LEDS       (GREEN_LED | ORANGE_LED)
 142 #define NEITHER_LED     0
 143
 144 static void set_leds(u32 leds, u32 blinking)
 145 {
 146         struct kwgpio_registers *r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
 147         u32 oe = readl(&r->oe) | BOTH_LEDS;
 148         writel(oe & ~leds, &r->oe);     /* active low */
 149         u32 bl = readl(&r->blink_en) & ~BOTH_LEDS;
 150         writel(bl | blinking, &r->blink_en);
 151 }
 152
 153 void show_boot_progress(int val)
 154 {
 155         switch (val) {
 156         case BOOTSTAGE_ID_RUN_OS:               /* booting Linux */
 157                 set_leds(BOTH_LEDS, NEITHER_LED);
 158                 break;
 159         case BOOTSTAGE_ID_NET_ETH_START:        /* Ethernet initialization */
 160                 set_leds(GREEN_LED, GREEN_LED);
 161                 break;
 162         default:
 163                 if (val < 0)    /* error */
 164                         set_leds(ORANGE_LED, ORANGE_LED);
 165                 break;
 166         }
 167 }