board/adder/adder.c

   1 /*
   2  * Copyright (C) 2004-2005 Arabella Software Ltd.
   3  * Yuli Barcohen <yuli@arabellasw.com>
   4  *
   5  * Support for Analogue&Micro Adder boards family.
   6  * Tested on AdderII and Adder87x.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <mpc8xx.h>
  13 #if defined(CONFIG_OF_LIBFDT)
  14         #include <libfdt.h>
  15 #endif
  16
  17 /*
  18  * SDRAM is single Samsung K4S643232F-T70   chip (8MB)
  19  *       or single Micron  MT48LC4M32B2TG-7 chip (16MB).
  20  * Minimal CPU frequency is 40MHz.
  21  */
  22 static uint sdram_table[] = {
  23         /* Single read  (offset 0x00 in UPM RAM) */
  24         0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
  25         0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
  26
  27         /* Burst read   (offset 0x08 in UPM RAM) */
  28         0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
  29         0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
  30         0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
  31         0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
  32
  33         /* Single write (offset 0x18 in UPM RAM) */
  34         0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
  35         0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
  36
  37         /* Burst write  (offset 0x20 in UPM RAM) */
  38         0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
  39         0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
  40         0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
  41         0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
  42
  43         /* Refresh      (offset 0x30 in UPM RAM) */
  44         0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
  45         0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
  46         0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
  47
  48         /* Exception    (offset 0x3C in UPM RAM) */
  49         0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
  50 };
  51
  52 phys_size_t initdram (int board_type)
  53 {
  54         long int msize;
  55         volatile immap_t     *immap  = (volatile immap_t *)CONFIG_SYS_IMMR;
  56         volatile memctl8xx_t *memctl = &immap->im_memctl;
  57
  58         upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
  59
  60         /* Configure SDRAM refresh */
  61         memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
  62
  63         memctl->memc_mamr = (94 << 24) | CONFIG_SYS_MAMR; /* No refresh */
  64         udelay(200);
  65
  66         /* Run precharge from location 0x15 */
  67         memctl->memc_mar = 0x0;
  68         memctl->memc_mcr = 0x80002115;
  69         udelay(200);
  70
  71         /* Run 8 refresh cycles */
  72         memctl->memc_mcr = 0x80002830;
  73         udelay(200);
  74
  75         /* Run MRS pattern from location 0x16 */
  76         memctl->memc_mar = 0x88;
  77         memctl->memc_mcr = 0x80002116;
  78         udelay(200);
  79
  80         memctl->memc_mamr |=  MAMR_PTAE; /* Enable refresh */
  81         memctl->memc_or1   = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
  82         memctl->memc_br1   =  CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
  83
  84         msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE);
  85         memctl->memc_or1  |= ~(msize - 1);
  86
  87         return msize;
  88 }
  89
  90 int checkboard( void )
  91 {
  92         puts("Board: Adder");
  93 #if defined(CONFIG_MPC885_FAMILY)
  94         puts("87x\n");
  95 #elif defined(CONFIG_MPC866_FAMILY)
  96         puts("II\n");
  97 #endif
  98
  99         return 0;
 100 }
 101
 102 #if defined(CONFIG_OF_BOARD_SETUP)
 103 void ft_board_setup(void *blob, bd_t *bd)
 104 {
 105         ft_cpu_setup(blob, bd);
 106
 107 }
 108 #endif