board/ads5121/ads5121.c

   1 /*
   2  * (C) Copyright 2007 DENX Software Engineering
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  *
  22  */
  23
  24 #include <common.h>
  25 #include <mpc512x.h>
  26 #include <asm/bitops.h>
  27 #include <command.h>
  28 #include <fdt_support.h>
  29
  30 /* Clocks in use */
  31 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN |                           \
  32                          CLOCK_SCCR1_LPC_EN |                           \
  33                          CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
  34                          CLOCK_SCCR1_PSCFIFO_EN |                       \
  35                          CLOCK_SCCR1_DDR_EN |                           \
  36                          CLOCK_SCCR1_FEC_EN |                           \
  37                          CLOCK_SCCR1_PCI_EN |                           \
  38                          CLOCK_SCCR1_TPR_EN)
  39
  40 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN |           \
  41                          CLOCK_SCCR2_SPDIF_EN |         \
  42                          CLOCK_SCCR2_I2C_EN)
  43
  44 #define CSAW_START(start)       ((start) & 0xFFFF0000)
  45 #define CSAW_STOP(start, size)  (((start) + (size) - 1) >> 16)
  46
  47 long int fixed_sdram(void);
  48
  49 int board_early_init_f (void)
  50 {
  51         volatile immap_t *im = (immap_t *) CFG_IMMR;
  52         u32 lpcaw;
  53
  54         /*
  55          * Initialize Local Window for the CPLD registers access (CS2 selects
  56          * the CPLD chip)
  57          */
  58         im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) |
  59                               CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE);
  60         im->lpc.cs_cfg[2] = CFG_CS2_CFG;
  61
  62         /*
  63          * According to MPC5121e RM, configuring local access windows should
  64          * be followed by a dummy read of the config register that was
  65          * modified last and an isync
  66          */
  67         lpcaw = im->sysconf.lpcs2aw;
  68         __asm__ __volatile__ ("isync");
  69
  70         /*
  71          * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
  72          *
  73          * Without this the flash identification routine fails, as it needs to issue
  74          * write commands in order to establish the device ID.
  75          */
  76         *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
  77
  78         /*
  79          * Enable clocks
  80          */
  81         im->clk.sccr[0] = SCCR1_CLOCKS_EN;
  82         im->clk.sccr[1] = SCCR2_CLOCKS_EN;
  83
  84         return 0;
  85 }
  86
  87 long int initdram (int board_type)
  88 {
  89         u32 msize = 0;
  90
  91         msize = fixed_sdram ();
  92
  93         return msize;
  94 }
  95
  96 /*
  97  * fixed sdram init -- the board doesn't use memory modules that have serial presence
  98  * detect or similar mechanism for discovery of the DRAM settings
  99  */
 100 long int fixed_sdram (void)
 101 {
 102         volatile immap_t *im = (immap_t *) CFG_IMMR;
 103         u32 msize = CFG_DDR_SIZE * 1024 * 1024;
 104         u32 msize_log2 = __ilog2 (msize);
 105         u32 i;
 106
 107         /* Initialize IO Control */
 108         im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR;
 109
 110         /* Initialize DDR Local Window */
 111         im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000;
 112         im->sysconf.ddrlaw.ar = msize_log2 - 1;
 113
 114         /*
 115          * According to MPC5121e RM, configuring local access windows should
 116          * be followed by a dummy read of the config register that was
 117          * modified last and an isync
 118          */
 119         i = im->sysconf.ddrlaw.ar;
 120         __asm__ __volatile__ ("isync");
 121
 122         /* Enable DDR */
 123         im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_EN;
 124
 125         /* Initialize DDR Priority Manager */
 126         im->mddrc.prioman_config1 = CFG_MDDRCGRP_PM_CFG1;
 127         im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2;
 128         im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG;
 129         im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU;
 130         im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML;
 131         im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
 132         im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML;
 133         im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
 134         im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML;
 135         im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
 136         im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML;
 137         im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
 138         im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML;
 139         im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU;
 140         im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AL;
 141         im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
 142         im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL;
 143         im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
 144         im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL;
 145         im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
 146         im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL;
 147         im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
 148         im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL;
 149
 150         /* Initialize MDDRC */
 151         im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG;
 152         im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0;
 153         im->mddrc.ddr_time_config1 = CFG_MDDRC_TIME_CFG1;
 154         im->mddrc.ddr_time_config2 = CFG_MDDRC_TIME_CFG2;
 155
 156         /* Initialize DDR */
 157         for (i = 0; i < 10; i++)
 158                 im->mddrc.ddr_command = CFG_MICRON_NOP;
 159
 160         im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
 161         im->mddrc.ddr_command = CFG_MICRON_NOP;
 162         im->mddrc.ddr_command = CFG_MICRON_RFSH;
 163         im->mddrc.ddr_command = CFG_MICRON_NOP;
 164         im->mddrc.ddr_command = CFG_MICRON_RFSH;
 165         im->mddrc.ddr_command = CFG_MICRON_NOP;
 166         im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
 167         im->mddrc.ddr_command = CFG_MICRON_NOP;
 168         im->mddrc.ddr_command = CFG_MICRON_EM2;
 169         im->mddrc.ddr_command = CFG_MICRON_NOP;
 170         im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
 171         im->mddrc.ddr_command = CFG_MICRON_EM2;
 172         im->mddrc.ddr_command = CFG_MICRON_EM3;
 173         im->mddrc.ddr_command = CFG_MICRON_EN_DLL;
 174         im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
 175         im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
 176         im->mddrc.ddr_command = CFG_MICRON_RFSH;
 177         im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
 178         im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT;
 179         im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
 180         im->mddrc.ddr_command = CFG_MICRON_NOP;
 181
 182         /* Start MDDRC */
 183         im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN;
 184         im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_RUN;
 185
 186         return msize;
 187 }
 188
 189 int checkboard (void)
 190 {
 191         ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);
 192         uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02);
 193         volatile immap_t *im = (immap_t *) CFG_IMMR;
 194         volatile unsigned long *reg;
 195         int i;
 196
 197         printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
 198                 brd_rev, cpld_rev);
 199
 200         /* change the slew rate on all pata pins to max */
 201         reg = (unsigned long *) &(im->io_ctrl.regs[PATA_CE1_IDX]);
 202         for (i = 0; i < 9; i++)
 203                 reg[i] |= 0x00000003;
 204         return 0;
 205 }
 206
 207 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 208 void ft_board_setup(void *blob, bd_t *bd)
 209 {
 210         ft_cpu_setup(blob, bd);
 211         fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 212 }
 213 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */