board/amcc/acadia/acadia.c

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/processor.h>
  10
  11 extern void board_pll_init_f(void);
  12
  13 static void acadia_gpio_init(void)
  14 {
  15         /*
  16          * GPIO0 setup (select GPIO or alternate function)
  17          */
  18         out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
  19         out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH);       /* output select */
  20         out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
  21         out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H);     /* input select */
  22         out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
  23         out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH);       /* three-state select */
  24         out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR);  /* enable output driver for outputs */
  25
  26         /*
  27          * Ultra (405EZ) was nice enough to add another GPIO controller
  28          */
  29         out32(GPIO1_OSRH, CONFIG_SYS_GPIO1_OSRH);       /* output select */
  30         out32(GPIO1_OSRL, CONFIG_SYS_GPIO1_OSRL);
  31         out32(GPIO1_ISR1H, CONFIG_SYS_GPIO1_ISR1H);     /* input select */
  32         out32(GPIO1_ISR1L, CONFIG_SYS_GPIO1_ISR1L);
  33         out32(GPIO1_TSRH, CONFIG_SYS_GPIO1_TSRH);       /* three-state select */
  34         out32(GPIO1_TSRL, CONFIG_SYS_GPIO1_TSRL);
  35         out32(GPIO1_TCR, CONFIG_SYS_GPIO1_TCR);  /* enable output driver for outputs */
  36 }
  37
  38 int board_early_init_f(void)
  39 {
  40         unsigned int reg;
  41
  42         /* don't reinit PLL when booting via I2C bootstrap option */
  43         mfsdr(SDR0_PINSTP, reg);
  44         if (reg != 0xf0000000)
  45                 board_pll_init_f();
  46
  47         acadia_gpio_init();
  48
  49         /* Configure 405EZ for NAND usage */
  50         mtsdr(SDR0_NAND0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
  51         mfsdr(SDR0_ULTRA0, reg);
  52         reg &= ~SDR_ULTRA0_CSN_MASK;
  53         reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) |
  54                 SDR_ULTRA0_NDGPIOBP |
  55                 SDR_ULTRA0_EBCRDYEN |
  56                 SDR_ULTRA0_NFSRSTEN;
  57         mtsdr(SDR0_ULTRA0, reg);
  58
  59         /* USB Host core needs this bit set */
  60         mfsdr(SDR0_ULTRA1, reg);
  61         mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE);
  62
  63         mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
  64         mtdcr(UIC0ER, 0x00000000);      /* disable all ints */
  65         mtdcr(UIC0CR, 0x00000010);
  66         mtdcr(UIC0PR, 0xFE7FFFF0);      /* set int polarities */
  67         mtdcr(UIC0TR, 0x00000010);      /* set int trigger levels */
  68         mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
  69
  70         return 0;
  71 }
  72
  73 int misc_init_f(void)
  74 {
  75         /* Set EPLD to take PHY out of reset */
  76         out8(CONFIG_SYS_CPLD_BASE + 0x05, 0x00);
  77         udelay(100000);
  78
  79         return 0;
  80 }
  81
  82 /*
  83  * Check Board Identity:
  84  */
  85 int checkboard(void)
  86 {
  87         char buf[64];
  88         int i = getenv_f("serial#", buf, sizeof(buf));
  89         u8 rev;
  90
  91         rev = in8(CONFIG_SYS_CPLD_BASE + 0);
  92         printf("Board: Acadia - AMCC PPC405EZ Evaluation Board, Rev. %X", rev);
  93
  94         if (i > 0) {
  95                 puts(", serial# ");
  96                 puts(buf);
  97         }
  98         putc('\n');
  99
 100         return (0);
 101 }