board/amcc/acadia/memory.c

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* define DEBUG for debugging output (obviously ;-)) */
  25 #if 0
  26 #define DEBUG
  27 #endif
  28
  29 #include <common.h>
  30 #include <asm/processor.h>
  31 #include <asm/io.h>
  32 #include <asm/gpio.h>
  33
  34 /*
  35  * sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
  36  */
  37 void sdram_init(void)
  38 {
  39         return;
  40 }
  41
  42 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  43 static void cram_bcr_write(u32 wr_val)
  44 {
  45         wr_val <<= 2;
  46
  47         /* set CRAM_CRE to 1 */
  48         gpio_write_bit(CFG_GPIO_CRAM_CRE, 1);
  49
  50         /* Write BCR to CRAM on CS1 */
  51         out32(wr_val + 0x00200000, 0);
  52         debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000);
  53
  54         /* Write BCR to CRAM on CS2 */
  55         out32(wr_val + 0x02200000, 0);
  56         debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000);
  57
  58         sync();
  59         eieio();
  60
  61         /* set CRAM_CRE back to 0 (normal operation) */
  62         gpio_write_bit(CFG_GPIO_CRAM_CRE, 0);
  63
  64         return;
  65 }
  66 #endif
  67
  68 long int initdram(int board_type)
  69 {
  70 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  71         int i;
  72         u32 val;
  73
  74         /* 1. EBC need to program READY, CLK, ADV for ASync mode */
  75         gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
  76         gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
  77         gpio_config(CFG_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
  78         gpio_config(CFG_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
  79
  80         /* 2. EBC in Async mode */
  81         mtebc(pb1ap, 0x078F1EC0);
  82         mtebc(pb2ap, 0x078F1EC0);
  83         mtebc(pb1cr, 0x000BC000);
  84         mtebc(pb2cr, 0x020BC000);
  85
  86         /* 3. Set CRAM in Sync mode */
  87         cram_bcr_write(0x7012);         /* CRAM burst setting */
  88
  89         /* 4. EBC in Sync mode */
  90         mtebc(pb1ap, 0x9C0201C0);
  91         mtebc(pb2ap, 0x9C0201C0);
  92
  93         /* Set GPIO pins back to alternate function */
  94         gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
  95         gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
  96
  97         /* Config EBC to use RDY */
  98         mfsdr(sdrultra0, val);
  99         mtsdr(sdrultra0, val | SDR_ULTRA0_EBCRDYEN);
 100
 101         /* Wait a short while, since for NAND booting this is too fast */
 102         for (i=0; i<200000; i++)
 103                 ;
 104 #endif
 105
 106         return (CFG_MBYTES_RAM << 20);
 107 }
 108
 109 int testdram(void)
 110 {
 111         return (0);
 112 }