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Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
[people/ms/u-boot.git] / board / amcc / bamboo / bamboo.c
1 /*
2 * (C) Copyright 2005-2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <common.h>
25 #include <asm/processor.h>
26 #include <asm/ppc4xx-gpio.h>
27 #include <spd_sdram.h>
28 #include <asm/ppc440.h>
29 #include "bamboo.h"
30
31 void ext_bus_cntlr_init(void);
32 void configure_ppc440ep_pins(void);
33 int is_nand_selected(void);
34
35 #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
36 /*************************************************************************
37 *
38 * Bamboo has one bank onboard sdram (plus DIMM)
39 *
40 * Fixed memory is composed of :
41 * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
42 * 13 row add bits, 10 column add bits (but 12 row used only).
43 * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
44 * 12 row add bits, 10 column add bits.
45 * Prepare a subset (only the used ones) of SPD data
46 *
47 * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
48 * the corresponding bank is divided by 2 due to number of Row addresses
49 * 12 in the ECC module
50 *
51 * Assumes: 64 MB, ECC, non-registered
52 * PLB @ 133 MHz
53 *
54 ************************************************************************/
55 const unsigned char cfg_simulate_spd_eeprom[128] = {
56 0x80, /* number of SPD bytes used: 128 */
57 0x08, /* total number bytes in SPD device = 256 */
58 0x07, /* DDR ram */
59 #ifdef CONFIG_DDR_ECC
60 0x0C, /* num Row Addr: 12 */
61 #else
62 0x0D, /* num Row Addr: 13 */
63 #endif
64 0x09, /* numColAddr: 9 */
65 0x01, /* numBanks: 1 */
66 0x20, /* Module data width: 32 bits */
67 0x00, /* Module data width continued: +0 */
68 0x04, /* 2.5 Volt */
69 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
70 0x00, /* SDRAM Access from clock */
71 #ifdef CONFIG_DDR_ECC
72 0x02, /* ECC ON : 02 OFF : 00 */
73 #else
74 0x00, /* ECC ON : 02 OFF : 00 */
75 #endif
76 0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */
77 0,
78 0,
79 0x01, /* wcsbc = 1 */
80 0,
81 0,
82 0x0C, /* casBit (2,2.5) */
83 0,
84 0,
85 0x00, /* not registered: 0 registered : 0x02*/
86 0,
87 0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */
88 0,
89 0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */
90 0,
91 0x50, /* tRpNs = 20 ns */
92 0,
93 0x50, /* tRcdNs = 20 ns */
94 45, /* tRasNs */
95 #ifdef CONFIG_DDR_ECC
96 0x08, /* bankSizeID: 32MB */
97 #else
98 0x10, /* bankSizeID: 64MB */
99 #endif
100 0,
101 0,
102 0,
103 0,
104 0,
105 0,
106 0,
107 0,
108 0,
109 0,
110 0,
111 0,
112 0,
113 0,
114 0,
115 0,
116 0,
117 0,
118 0,
119 0,
120 0,
121 0,
122 0,
123 0,
124 0,
125 0,
126 0,
127 0,
128 0,
129 0,
130 0,
131 0,
132 0,
133 0,
134 0,
135 0,
136 0,
137 0,
138 0,
139 0,
140 0,
141 0,
142 0,
143 0,
144 0,
145 0,
146 0,
147 0,
148 0,
149 0,
150 0,
151 0,
152 0,
153 0,
154 0,
155 0,
156 0,
157 0,
158 0,
159 0,
160 0,
161 0,
162 0,
163 0,
164 0,
165 0,
166 0,
167 0,
168 0,
169 0,
170 0,
171 0,
172 0,
173 0,
174 0,
175 0,
176 0,
177 0,
178 0,
179 0,
180 0,
181 0,
182 0,
183 0,
184 0,
185 0,
186 0,
187 0,
188 0,
189 0,
190 0,
191 0,
192 0,
193 0,
194 0,
195 0
196 };
197 #endif
198
199 #if 0
200 { /* GPIO Alternate1 Alternate2 Alternate3 */
201 {
202 /* GPIO Core 0 */
203 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
204 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
205 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
206 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
207 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
208 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
209 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
210 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
211 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
212 { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
213 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
214 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
215 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
216 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
217 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
218 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
219 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
220 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
221 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
222 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
223 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
224 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
225 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
226 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
227 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
228 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
229 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
230 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
231 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
232 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
233 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
234 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
235 },
236 {
237 /* GPIO Core 1 */
238 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
239 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
240 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
241 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
242 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
243 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
244 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
245 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
246 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
247 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
248 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
249 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
250 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
251 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
252 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
253 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
254 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
255 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
256 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
257 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
258 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
259 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
260 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
261 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
262 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
263 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
264 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
265 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
266 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
267 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
268 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
269 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
270 }
271 };
272 #endif
273
274 /*----------------------------------------------------------------------------+
275 | EBC Devices Characteristics
276 | Peripheral Bank Access Parameters - EBC0_BnAP
277 | Peripheral Bank Configuration Register - EBC0_BnCR
278 +----------------------------------------------------------------------------*/
279 /* Small Flash */
280 #define EBC0_BNAP_SMALL_FLASH \
281 EBC0_BNAP_BME_DISABLED | \
282 EBC0_BNAP_TWT_ENCODE(6) | \
283 EBC0_BNAP_CSN_ENCODE(0) | \
284 EBC0_BNAP_OEN_ENCODE(1) | \
285 EBC0_BNAP_WBN_ENCODE(1) | \
286 EBC0_BNAP_WBF_ENCODE(3) | \
287 EBC0_BNAP_TH_ENCODE(1) | \
288 EBC0_BNAP_RE_ENABLED | \
289 EBC0_BNAP_SOR_DELAYED | \
290 EBC0_BNAP_BEM_WRITEONLY | \
291 EBC0_BNAP_PEN_DISABLED
292
293 #define EBC0_BNCR_SMALL_FLASH_CS0 \
294 EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
295 EBC0_BNCR_BS_1MB | \
296 EBC0_BNCR_BU_RW | \
297 EBC0_BNCR_BW_8BIT
298
299 #define EBC0_BNCR_SMALL_FLASH_CS4 \
300 EBC0_BNCR_BAS_ENCODE(0x87F00000) | \
301 EBC0_BNCR_BS_1MB | \
302 EBC0_BNCR_BU_RW | \
303 EBC0_BNCR_BW_8BIT
304
305 /* Large Flash or SRAM */
306 #define EBC0_BNAP_LARGE_FLASH_OR_SRAM \
307 EBC0_BNAP_BME_DISABLED | \
308 EBC0_BNAP_TWT_ENCODE(8) | \
309 EBC0_BNAP_CSN_ENCODE(0) | \
310 EBC0_BNAP_OEN_ENCODE(1) | \
311 EBC0_BNAP_WBN_ENCODE(1) | \
312 EBC0_BNAP_WBF_ENCODE(1) | \
313 EBC0_BNAP_TH_ENCODE(2) | \
314 EBC0_BNAP_SOR_DELAYED | \
315 EBC0_BNAP_BEM_RW | \
316 EBC0_BNAP_PEN_DISABLED
317
318 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \
319 EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
320 EBC0_BNCR_BS_8MB | \
321 EBC0_BNCR_BU_RW | \
322 EBC0_BNCR_BW_16BIT
323
324
325 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \
326 EBC0_BNCR_BAS_ENCODE(0x87800000) | \
327 EBC0_BNCR_BS_8MB | \
328 EBC0_BNCR_BU_RW | \
329 EBC0_BNCR_BW_16BIT
330
331 /* NVRAM - FPGA */
332 #define EBC0_BNAP_NVRAM_FPGA \
333 EBC0_BNAP_BME_DISABLED | \
334 EBC0_BNAP_TWT_ENCODE(9) | \
335 EBC0_BNAP_CSN_ENCODE(0) | \
336 EBC0_BNAP_OEN_ENCODE(1) | \
337 EBC0_BNAP_WBN_ENCODE(1) | \
338 EBC0_BNAP_WBF_ENCODE(0) | \
339 EBC0_BNAP_TH_ENCODE(2) | \
340 EBC0_BNAP_RE_ENABLED | \
341 EBC0_BNAP_SOR_DELAYED | \
342 EBC0_BNAP_BEM_WRITEONLY | \
343 EBC0_BNAP_PEN_DISABLED
344
345 #define EBC0_BNCR_NVRAM_FPGA_CS5 \
346 EBC0_BNCR_BAS_ENCODE(0x80000000) | \
347 EBC0_BNCR_BS_1MB | \
348 EBC0_BNCR_BU_RW | \
349 EBC0_BNCR_BW_8BIT
350
351 /* Nand Flash */
352 #define EBC0_BNAP_NAND_FLASH \
353 EBC0_BNAP_BME_DISABLED | \
354 EBC0_BNAP_TWT_ENCODE(3) | \
355 EBC0_BNAP_CSN_ENCODE(0) | \
356 EBC0_BNAP_OEN_ENCODE(0) | \
357 EBC0_BNAP_WBN_ENCODE(0) | \
358 EBC0_BNAP_WBF_ENCODE(0) | \
359 EBC0_BNAP_TH_ENCODE(1) | \
360 EBC0_BNAP_RE_ENABLED | \
361 EBC0_BNAP_SOR_NOT_DELAYED | \
362 EBC0_BNAP_BEM_RW | \
363 EBC0_BNAP_PEN_DISABLED
364
365
366 #define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
367
368 /* NAND0 */
369 #define EBC0_BNCR_NAND_FLASH_CS1 \
370 EBC0_BNCR_BAS_ENCODE(0x90000000) | \
371 EBC0_BNCR_BS_1MB | \
372 EBC0_BNCR_BU_RW | \
373 EBC0_BNCR_BW_32BIT
374 /* NAND1 - Bank2 */
375 #define EBC0_BNCR_NAND_FLASH_CS2 \
376 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
377 EBC0_BNCR_BS_1MB | \
378 EBC0_BNCR_BU_RW | \
379 EBC0_BNCR_BW_32BIT
380
381 /* NAND1 - Bank3 */
382 #define EBC0_BNCR_NAND_FLASH_CS3 \
383 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
384 EBC0_BNCR_BS_1MB | \
385 EBC0_BNCR_BU_RW | \
386 EBC0_BNCR_BW_32BIT
387
388 int board_early_init_f(void)
389 {
390 ext_bus_cntlr_init();
391
392 /*--------------------------------------------------------------------
393 * Setup the interrupt controller polarities, triggers, etc.
394 *-------------------------------------------------------------------*/
395 mtdcr(UIC0SR, 0xffffffff); /* clear all */
396 mtdcr(UIC0ER, 0x00000000); /* disable all */
397 mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
398 mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
399 mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
400 mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
401 mtdcr(UIC0SR, 0xffffffff); /* clear all */
402
403 mtdcr(UIC1SR, 0xffffffff); /* clear all */
404 mtdcr(UIC1ER, 0x00000000); /* disable all */
405 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
406 mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
407 mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
408 mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
409 mtdcr(UIC1SR, 0xffffffff); /* clear all */
410
411 /*--------------------------------------------------------------------
412 * Setup the GPIO pins
413 *-------------------------------------------------------------------*/
414 out32(GPIO0_OSRL, 0x00000400);
415 out32(GPIO0_OSRH, 0x00000000);
416 out32(GPIO0_TSRL, 0x00000400);
417 out32(GPIO0_TSRH, 0x00000000);
418 out32(GPIO0_ISR1L, 0x00000000);
419 out32(GPIO0_ISR1H, 0x00000000);
420 out32(GPIO0_ISR2L, 0x00000000);
421 out32(GPIO0_ISR2H, 0x00000000);
422 out32(GPIO0_ISR3L, 0x00000000);
423 out32(GPIO0_ISR3H, 0x00000000);
424
425 out32(GPIO1_OSRL, 0x0C380000);
426 out32(GPIO1_OSRH, 0x00000000);
427 out32(GPIO1_TSRL, 0x0C380000);
428 out32(GPIO1_TSRH, 0x00000000);
429 out32(GPIO1_ISR1L, 0x0FC30000);
430 out32(GPIO1_ISR1H, 0x00000000);
431 out32(GPIO1_ISR2L, 0x0C010000);
432 out32(GPIO1_ISR2H, 0x00000000);
433 out32(GPIO1_ISR3L, 0x01400000);
434 out32(GPIO1_ISR3H, 0x00000000);
435
436 configure_ppc440ep_pins();
437
438 return 0;
439 }
440
441 int checkboard(void)
442 {
443 char buf[64];
444 int i = getenv_f("serial#", buf, sizeof(buf));
445
446 printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
447 if (i > 0) {
448 puts(", serial# ");
449 puts(buf);
450 }
451 putc('\n');
452
453 return (0);
454 }
455
456
457 phys_size_t initdram (int board_type)
458 {
459 #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
460 long dram_size;
461
462 dram_size = spd_sdram();
463
464 return dram_size;
465 #else
466 return CONFIG_SYS_MBYTES_SDRAM << 20;
467 #endif
468 }
469
470 /*----------------------------------------------------------------------------+
471 | is_powerpc440ep_pass1.
472 +----------------------------------------------------------------------------*/
473 int is_powerpc440ep_pass1(void)
474 {
475 unsigned long pvr;
476
477 pvr = get_pvr();
478
479 if (pvr == PVR_POWERPC_440EP_PASS1)
480 return true;
481 else if (pvr == PVR_POWERPC_440EP_PASS2)
482 return false;
483 else {
484 printf("brdutil error 3\n");
485 for (;;)
486 ;
487 }
488
489 return false;
490 }
491
492 /*----------------------------------------------------------------------------+
493 | is_nand_selected.
494 +----------------------------------------------------------------------------*/
495 int is_nand_selected(void)
496 {
497 #ifdef CONFIG_BAMBOO_NAND
498 return true;
499 #else
500 return false;
501 #endif
502 }
503
504 /*----------------------------------------------------------------------------+
505 | config_on_ebc_cs4_is_small_flash => from EPLD
506 +----------------------------------------------------------------------------*/
507 unsigned char config_on_ebc_cs4_is_small_flash(void)
508 {
509 /* Not implemented yet => returns constant value */
510 return true;
511 }
512
513 /*----------------------------------------------------------------------------+
514 | Ext_bus_cntlr_init.
515 | Initialize the external bus controller
516 +----------------------------------------------------------------------------*/
517 void ext_bus_cntlr_init(void)
518 {
519 unsigned long sdr0_pstrp0, sdr0_sdstp1;
520 unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
521 int computed_boot_device = BOOT_DEVICE_UNKNOWN;
522 unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
523 unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
524 unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
525 unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
526 unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
527
528
529 /*-------------------------------------------------------------------------+
530 |
531 | PART 1 : Initialize EBC Bank 5
532 | ==============================
533 | Bank5 is always associated to the NVRAM/EPLD.
534 | It has to be initialized prior to other banks settings computation since
535 | some board registers values may be needed
536 |
537 +-------------------------------------------------------------------------*/
538 /* NVRAM - FPGA */
539 mtebc(PB5AP, EBC0_BNAP_NVRAM_FPGA);
540 mtebc(PB5CR, EBC0_BNCR_NVRAM_FPGA_CS5);
541
542 /*-------------------------------------------------------------------------+
543 |
544 | PART 2 : Determine which boot device was selected
545 | =========================================
546 |
547 | Read Pin Strap Register in PPC440EP
548 | In case of boot from IIC, read Serial Device Strap Register1
549 |
550 | Result can either be :
551 | - Boot from EBC 8bits => SMALL FLASH
552 | - Boot from EBC 16bits => Large Flash or SRAM
553 | - Boot from NAND Flash
554 | - Boot from PCI
555 |
556 +-------------------------------------------------------------------------*/
557 /* Read Pin Strap Register in PPC440EP */
558 mfsdr(SDR0_PINSTP, sdr0_pstrp0);
559 bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
560
561 /*-------------------------------------------------------------------------+
562 | PPC440EP Pass1
563 +-------------------------------------------------------------------------*/
564 if (is_powerpc440ep_pass1() == true) {
565 switch(bootstrap_settings) {
566 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
567 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
568 /* Boot from Small Flash */
569 computed_boot_device = BOOT_FROM_SMALL_FLASH;
570 break;
571 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
572 /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
573 /* Boot from PCI */
574 computed_boot_device = BOOT_FROM_PCI;
575 break;
576
577 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
578 /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
579 /* Boot from Nand Flash */
580 computed_boot_device = BOOT_FROM_NAND_FLASH0;
581 break;
582
583 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
584 /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
585 /* Boot from Small Flash */
586 computed_boot_device = BOOT_FROM_SMALL_FLASH;
587 break;
588
589 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
590 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
591 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
592 /* Read Serial Device Strap Register1 in PPC440EP */
593 mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
594 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
595 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
596
597 switch(boot_selection) {
598 case SDR0_SDSTP1_BOOT_SEL_EBC:
599 switch(ebc_boot_size) {
600 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
601 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
602 break;
603 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
604 computed_boot_device = BOOT_FROM_SMALL_FLASH;
605 break;
606 }
607 break;
608
609 case SDR0_SDSTP1_BOOT_SEL_PCI:
610 computed_boot_device = BOOT_FROM_PCI;
611 break;
612
613 case SDR0_SDSTP1_BOOT_SEL_NDFC:
614 computed_boot_device = BOOT_FROM_NAND_FLASH0;
615 break;
616 }
617 break;
618 }
619 }
620
621 /*-------------------------------------------------------------------------+
622 | PPC440EP Pass2
623 +-------------------------------------------------------------------------*/
624 else {
625 switch(bootstrap_settings) {
626 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
627 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
628 /* Boot from Small Flash */
629 computed_boot_device = BOOT_FROM_SMALL_FLASH;
630 break;
631 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
632 /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
633 /* Boot from PCI */
634 computed_boot_device = BOOT_FROM_PCI;
635 break;
636
637 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
638 /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
639 /* Boot from Nand Flash */
640 computed_boot_device = BOOT_FROM_NAND_FLASH0;
641 break;
642
643 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
644 /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
645 /* Boot from Large Flash or SRAM */
646 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
647 break;
648
649 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
650 /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
651 /* Boot from Large Flash or SRAM */
652 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
653 break;
654
655 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
656 /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
657 /* Boot from PCI */
658 computed_boot_device = BOOT_FROM_PCI;
659 break;
660
661 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
662 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
663 /* Default Strap Settings 5-7 */
664 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
665 /* Read Serial Device Strap Register1 in PPC440EP */
666 mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
667 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
668 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
669
670 switch(boot_selection) {
671 case SDR0_SDSTP1_BOOT_SEL_EBC:
672 switch(ebc_boot_size) {
673 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
674 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
675 break;
676 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
677 computed_boot_device = BOOT_FROM_SMALL_FLASH;
678 break;
679 }
680 break;
681
682 case SDR0_SDSTP1_BOOT_SEL_PCI:
683 computed_boot_device = BOOT_FROM_PCI;
684 break;
685
686 case SDR0_SDSTP1_BOOT_SEL_NDFC:
687 computed_boot_device = BOOT_FROM_NAND_FLASH0;
688 break;
689 }
690 break;
691 }
692 }
693
694 /*-------------------------------------------------------------------------+
695 |
696 | PART 3 : Compute EBC settings depending on selected boot device
697 | ====== ======================================================
698 |
699 | Resulting EBC init will be among following configurations :
700 |
701 | - Boot from EBC 8bits => boot from SMALL FLASH selected
702 | EBC-CS0 = Small Flash
703 | EBC-CS1,2,3 = NAND Flash or
704 | Exp.Slot depending on Soft Config
705 | EBC-CS4 = SRAM/Large Flash or
706 | Large Flash/SRAM depending on jumpers
707 | EBC-CS5 = NVRAM / EPLD
708 |
709 | - Boot from EBC 16bits => boot from Large Flash or SRAM selected
710 | EBC-CS0 = SRAM/Large Flash or
711 | Large Flash/SRAM depending on jumpers
712 | EBC-CS1,2,3 = NAND Flash or
713 | Exp.Slot depending on Software Configuration
714 | EBC-CS4 = Small Flash
715 | EBC-CS5 = NVRAM / EPLD
716 |
717 | - Boot from NAND Flash
718 | EBC-CS0 = NAND Flash0
719 | EBC-CS1,2,3 = NAND Flash1
720 | EBC-CS4 = SRAM/Large Flash or
721 | Large Flash/SRAM depending on jumpers
722 | EBC-CS5 = NVRAM / EPLD
723 |
724 | - Boot from PCI
725 | EBC-CS0 = ...
726 | EBC-CS1,2,3 = NAND Flash or
727 | Exp.Slot depending on Software Configuration
728 | EBC-CS4 = SRAM/Large Flash or
729 | Large Flash/SRAM or
730 | Small Flash depending on jumpers
731 | EBC-CS5 = NVRAM / EPLD
732 |
733 +-------------------------------------------------------------------------*/
734
735 switch(computed_boot_device) {
736 /*------------------------------------------------------------------------- */
737 case BOOT_FROM_SMALL_FLASH:
738 /*------------------------------------------------------------------------- */
739 ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
740 ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
741 if ((is_nand_selected()) == true) {
742 /* NAND Flash */
743 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
744 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
745 ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
746 ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
747 ebc0_cs3_bnap_value = 0;
748 ebc0_cs3_bncr_value = 0;
749 } else {
750 /* Expansion Slot */
751 ebc0_cs1_bnap_value = 0;
752 ebc0_cs1_bncr_value = 0;
753 ebc0_cs2_bnap_value = 0;
754 ebc0_cs2_bncr_value = 0;
755 ebc0_cs3_bnap_value = 0;
756 ebc0_cs3_bncr_value = 0;
757 }
758 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
759 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
760
761 break;
762
763 /*------------------------------------------------------------------------- */
764 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
765 /*------------------------------------------------------------------------- */
766 ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
767 ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
768 if ((is_nand_selected()) == true) {
769 /* NAND Flash */
770 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
771 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
772 ebc0_cs2_bnap_value = 0;
773 ebc0_cs2_bncr_value = 0;
774 ebc0_cs3_bnap_value = 0;
775 ebc0_cs3_bncr_value = 0;
776 } else {
777 /* Expansion Slot */
778 ebc0_cs1_bnap_value = 0;
779 ebc0_cs1_bncr_value = 0;
780 ebc0_cs2_bnap_value = 0;
781 ebc0_cs2_bncr_value = 0;
782 ebc0_cs3_bnap_value = 0;
783 ebc0_cs3_bncr_value = 0;
784 }
785 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
786 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
787
788 break;
789
790 /*------------------------------------------------------------------------- */
791 case BOOT_FROM_NAND_FLASH0:
792 /*------------------------------------------------------------------------- */
793 ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH;
794 ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
795
796 ebc0_cs1_bnap_value = 0;
797 ebc0_cs1_bncr_value = 0;
798 ebc0_cs2_bnap_value = 0;
799 ebc0_cs2_bncr_value = 0;
800 ebc0_cs3_bnap_value = 0;
801 ebc0_cs3_bncr_value = 0;
802
803 /* Large Flash or SRAM */
804 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
805 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
806
807 break;
808
809 /*------------------------------------------------------------------------- */
810 case BOOT_FROM_PCI:
811 /*------------------------------------------------------------------------- */
812 ebc0_cs0_bnap_value = 0;
813 ebc0_cs0_bncr_value = 0;
814
815 if ((is_nand_selected()) == true) {
816 /* NAND Flash */
817 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
818 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
819 ebc0_cs2_bnap_value = 0;
820 ebc0_cs2_bncr_value = 0;
821 ebc0_cs3_bnap_value = 0;
822 ebc0_cs3_bncr_value = 0;
823 } else {
824 /* Expansion Slot */
825 ebc0_cs1_bnap_value = 0;
826 ebc0_cs1_bncr_value = 0;
827 ebc0_cs2_bnap_value = 0;
828 ebc0_cs2_bncr_value = 0;
829 ebc0_cs3_bnap_value = 0;
830 ebc0_cs3_bncr_value = 0;
831 }
832
833 if ((config_on_ebc_cs4_is_small_flash()) == true) {
834 /* Small Flash */
835 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
836 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
837 } else {
838 /* Large Flash or SRAM */
839 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
840 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
841 }
842
843 break;
844
845 /*------------------------------------------------------------------------- */
846 case BOOT_DEVICE_UNKNOWN:
847 /*------------------------------------------------------------------------- */
848 /* Error */
849 break;
850
851 }
852
853
854 /*-------------------------------------------------------------------------+
855 | Initialize EBC CONFIG
856 +-------------------------------------------------------------------------*/
857 mtdcr(EBC0_CFGADDR, EBC0_CFG);
858 mtdcr(EBC0_CFGDATA, EBC0_CFG_EBTC_DRIVEN |
859 EBC0_CFG_PTD_ENABLED |
860 EBC0_CFG_RTC_2048PERCLK |
861 EBC0_CFG_EMPL_LOW |
862 EBC0_CFG_EMPH_LOW |
863 EBC0_CFG_CSTC_DRIVEN |
864 EBC0_CFG_BPF_ONEDW |
865 EBC0_CFG_EMS_8BIT |
866 EBC0_CFG_PME_DISABLED |
867 EBC0_CFG_PMT_ENCODE(0) );
868
869 /*-------------------------------------------------------------------------+
870 | Initialize EBC Bank 0-4
871 +-------------------------------------------------------------------------*/
872 /* EBC Bank0 */
873 mtebc(PB0AP, ebc0_cs0_bnap_value);
874 mtebc(PB0CR, ebc0_cs0_bncr_value);
875 /* EBC Bank1 */
876 mtebc(PB1AP, ebc0_cs1_bnap_value);
877 mtebc(PB1CR, ebc0_cs1_bncr_value);
878 /* EBC Bank2 */
879 mtebc(PB2AP, ebc0_cs2_bnap_value);
880 mtebc(PB2CR, ebc0_cs2_bncr_value);
881 /* EBC Bank3 */
882 mtebc(PB3AP, ebc0_cs3_bnap_value);
883 mtebc(PB3CR, ebc0_cs3_bncr_value);
884 /* EBC Bank4 */
885 mtebc(PB4AP, ebc0_cs4_bnap_value);
886 mtebc(PB4CR, ebc0_cs4_bncr_value);
887
888 return;
889 }
890
891
892 /*----------------------------------------------------------------------------+
893 | get_uart_configuration.
894 +----------------------------------------------------------------------------*/
895 uart_config_nb_t get_uart_configuration(void)
896 {
897 return (L4);
898 }
899
900 /*----------------------------------------------------------------------------+
901 | set_phy_configuration_through_fpga => to EPLD
902 +----------------------------------------------------------------------------*/
903 void set_phy_configuration_through_fpga(zmii_config_t config)
904 {
905
906 unsigned long fpga_selection_reg;
907
908 fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
909
910 switch(config)
911 {
912 case ZMII_CONFIGURATION_IS_MII:
913 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
914 break;
915 case ZMII_CONFIGURATION_IS_RMII:
916 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
917 break;
918 case ZMII_CONFIGURATION_IS_SMII:
919 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
920 break;
921 case ZMII_CONFIGURATION_UNKNOWN:
922 default:
923 break;
924 }
925 out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
926
927 }
928
929 /*----------------------------------------------------------------------------+
930 | scp_selection_in_fpga.
931 +----------------------------------------------------------------------------*/
932 void scp_selection_in_fpga(void)
933 {
934 unsigned long fpga_selection_2_reg;
935
936 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
937 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
938 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
939 }
940
941 /*----------------------------------------------------------------------------+
942 | iic1_selection_in_fpga.
943 +----------------------------------------------------------------------------*/
944 void iic1_selection_in_fpga(void)
945 {
946 unsigned long fpga_selection_2_reg;
947
948 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
949 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
950 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
951 }
952
953 /*----------------------------------------------------------------------------+
954 | dma_a_b_selection_in_fpga.
955 +----------------------------------------------------------------------------*/
956 void dma_a_b_selection_in_fpga(void)
957 {
958 unsigned long fpga_selection_2_reg;
959
960 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
961 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
962 }
963
964 /*----------------------------------------------------------------------------+
965 | dma_a_b_unselect_in_fpga.
966 +----------------------------------------------------------------------------*/
967 void dma_a_b_unselect_in_fpga(void)
968 {
969 unsigned long fpga_selection_2_reg;
970
971 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
972 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
973 }
974
975 /*----------------------------------------------------------------------------+
976 | dma_c_d_selection_in_fpga.
977 +----------------------------------------------------------------------------*/
978 void dma_c_d_selection_in_fpga(void)
979 {
980 unsigned long fpga_selection_2_reg;
981
982 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
983 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
984 }
985
986 /*----------------------------------------------------------------------------+
987 | dma_c_d_unselect_in_fpga.
988 +----------------------------------------------------------------------------*/
989 void dma_c_d_unselect_in_fpga(void)
990 {
991 unsigned long fpga_selection_2_reg;
992
993 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
994 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
995 }
996
997 /*----------------------------------------------------------------------------+
998 | usb2_device_selection_in_fpga.
999 +----------------------------------------------------------------------------*/
1000 void usb2_device_selection_in_fpga(void)
1001 {
1002 unsigned long fpga_selection_1_reg;
1003
1004 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
1005 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1006 }
1007
1008 /*----------------------------------------------------------------------------+
1009 | usb2_device_reset_through_fpga.
1010 +----------------------------------------------------------------------------*/
1011 void usb2_device_reset_through_fpga(void)
1012 {
1013 /* Perform soft Reset pulse */
1014 unsigned long fpga_reset_reg;
1015 int i;
1016
1017 fpga_reset_reg = in8(FPGA_RESET_REG);
1018 out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
1019 for (i=0; i<500; i++)
1020 udelay(1000);
1021 out8(FPGA_RESET_REG,fpga_reset_reg);
1022 }
1023
1024 /*----------------------------------------------------------------------------+
1025 | usb2_host_selection_in_fpga.
1026 +----------------------------------------------------------------------------*/
1027 void usb2_host_selection_in_fpga(void)
1028 {
1029 unsigned long fpga_selection_1_reg;
1030
1031 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
1032 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1033 }
1034
1035 /*----------------------------------------------------------------------------+
1036 | ndfc_selection_in_fpga.
1037 +----------------------------------------------------------------------------*/
1038 void ndfc_selection_in_fpga(void)
1039 {
1040 unsigned long fpga_selection_1_reg;
1041
1042 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
1043 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
1044 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
1045 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1046 }
1047
1048 /*----------------------------------------------------------------------------+
1049 | uart_selection_in_fpga.
1050 +----------------------------------------------------------------------------*/
1051 void uart_selection_in_fpga(uart_config_nb_t uart_config)
1052 {
1053 /* FPGA register */
1054 unsigned char fpga_selection_3_reg;
1055
1056 /* Read FPGA Reagister */
1057 fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
1058
1059 switch (uart_config)
1060 {
1061 case L1:
1062 /* ----------------------------------------------------------------------- */
1063 /* L1 configuration: UART0 = 8 pins */
1064 /* ----------------------------------------------------------------------- */
1065 /* Configure FPGA */
1066 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1067 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
1068 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1069
1070 break;
1071
1072 case L2:
1073 /* ----------------------------------------------------------------------- */
1074 /* L2 configuration: UART0 = 4 pins */
1075 /* UART1 = 4 pins */
1076 /* ----------------------------------------------------------------------- */
1077 /* Configure FPGA */
1078 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1079 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
1080 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1081
1082 break;
1083
1084 case L3:
1085 /* ----------------------------------------------------------------------- */
1086 /* L3 configuration: UART0 = 4 pins */
1087 /* UART1 = 2 pins */
1088 /* UART2 = 2 pins */
1089 /* ----------------------------------------------------------------------- */
1090 /* Configure FPGA */
1091 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1092 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
1093 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1094 break;
1095
1096 case L4:
1097 /* Configure FPGA */
1098 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1099 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
1100 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1101
1102 break;
1103
1104 default:
1105 /* Unsupported UART configuration number */
1106 for (;;)
1107 ;
1108 break;
1109
1110 }
1111 }
1112
1113
1114 /*----------------------------------------------------------------------------+
1115 | init_default_gpio
1116 +----------------------------------------------------------------------------*/
1117 void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX])
1118 {
1119 int i;
1120
1121 /* Init GPIO0 */
1122 for(i=0; i<GPIO_MAX; i++)
1123 {
1124 gpio_tab[GPIO0][i].add = GPIO0_BASE;
1125 gpio_tab[GPIO0][i].in_out = GPIO_DIS;
1126 gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
1127 }
1128
1129 /* Init GPIO1 */
1130 for(i=0; i<GPIO_MAX; i++)
1131 {
1132 gpio_tab[GPIO1][i].add = GPIO1_BASE;
1133 gpio_tab[GPIO1][i].in_out = GPIO_DIS;
1134 gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
1135 }
1136
1137 /* EBC_CS_N(5) - GPIO0_10 */
1138 gpio_tab[GPIO0][10].in_out = GPIO_OUT;
1139 gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1;
1140
1141 /* EBC_CS_N(4) - GPIO0_9 */
1142 gpio_tab[GPIO0][9].in_out = GPIO_OUT;
1143 gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1;
1144 }
1145
1146 /*----------------------------------------------------------------------------+
1147 | update_uart_ios
1148 +------------------------------------------------------------------------------
1149 |
1150 | Set UART Configuration in PowerPC440EP
1151 |
1152 | +---------------------------------------------------------------------+
1153 | | Configuartion | Connector | Nb of pins | Pins | Associated |
1154 | | Number | Port Name | available | naming | CORE |
1155 | +-----------------+---------------+------------+--------+-------------+
1156 | | L1 | Port_A | 8 | UART | UART core 0 |
1157 | +-----------------+---------------+------------+--------+-------------+
1158 | | L2 | Port_A | 4 | UART1 | UART core 0 |
1159 | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
1160 | +-----------------+---------------+------------+--------+-------------+
1161 | | L3 | Port_A | 4 | UART1 | UART core 0 |
1162 | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
1163 | | | Port_C | 2 | UART3 | UART core 2 |
1164 | +-----------------+---------------+------------+--------+-------------+
1165 | | | Port_A | 2 | UART1 | UART core 0 |
1166 | | L4 | Port_B | 2 | UART2 | UART core 1 |
1167 | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
1168 | | | Port_D | 2 | UART4 | UART core 3 |
1169 | +-----------------+---------------+------------+--------+-------------+
1170 |
1171 | Involved GPIOs
1172 |
1173 | +------------------------------------------------------------------------------+
1174 | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
1175 | +---------+------------------+-----+-----------------+-----+-------------+-----+
1176 | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
1177 | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
1178 | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
1179 | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
1180 | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
1181 | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
1182 | +------------------------------------------------------------------------------+
1183 |
1184 |
1185 +----------------------------------------------------------------------------*/
1186
1187 void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX])
1188 {
1189 switch (uart_config)
1190 {
1191 case L1:
1192 /* ----------------------------------------------------------------------- */
1193 /* L1 configuration: UART0 = 8 pins */
1194 /* ----------------------------------------------------------------------- */
1195 /* Update GPIO Configuration Table */
1196 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1197 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
1198
1199 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1200 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
1201
1202 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1203 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1204
1205 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1206 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1207
1208 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1209 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
1210
1211 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1212 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
1213
1214 break;
1215
1216 case L2:
1217 /* ----------------------------------------------------------------------- */
1218 /* L2 configuration: UART0 = 4 pins */
1219 /* UART1 = 4 pins */
1220 /* ----------------------------------------------------------------------- */
1221 /* Update GPIO Configuration Table */
1222 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1223 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
1224
1225 gpio_tab[GPIO1][3].in_out = GPIO_OUT;
1226 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
1227
1228 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1229 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1230
1231 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1232 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1233
1234 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1235 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1236
1237 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1238 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1239
1240 break;
1241
1242 case L3:
1243 /* ----------------------------------------------------------------------- */
1244 /* L3 configuration: UART0 = 4 pins */
1245 /* UART1 = 2 pins */
1246 /* UART2 = 2 pins */
1247 /* ----------------------------------------------------------------------- */
1248 /* Update GPIO Configuration Table */
1249 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1250 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1251
1252 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1253 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1254
1255 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1256 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1257
1258 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1259 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1260
1261 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1262 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1263
1264 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1265 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1266
1267 break;
1268
1269 case L4:
1270 /* ----------------------------------------------------------------------- */
1271 /* L4 configuration: UART0 = 2 pins */
1272 /* UART1 = 2 pins */
1273 /* UART2 = 2 pins */
1274 /* UART3 = 2 pins */
1275 /* ----------------------------------------------------------------------- */
1276 /* Update GPIO Configuration Table */
1277 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1278 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1279
1280 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1281 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1282
1283 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1284 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
1285
1286 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1287 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
1288
1289 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1290 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1291
1292 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1293 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1294
1295 break;
1296
1297 default:
1298 /* Unsupported UART configuration number */
1299 printf("ERROR - Unsupported UART configuration number.\n\n");
1300 for (;;)
1301 ;
1302 break;
1303
1304 }
1305
1306 /* Set input Selection Register on Alt_Receive for UART Input Core */
1307 out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
1308 out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
1309 out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
1310 }
1311
1312 /*----------------------------------------------------------------------------+
1313 | update_ndfc_ios(void).
1314 +----------------------------------------------------------------------------*/
1315 void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1316 {
1317 /* Update GPIO Configuration Table */
1318 gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
1319 gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
1320
1321 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
1322 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1323
1324 #if 0
1325 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
1326 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1327 #endif
1328 }
1329
1330 /*----------------------------------------------------------------------------+
1331 | update_zii_ios(void).
1332 +----------------------------------------------------------------------------*/
1333 void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1334 {
1335 /* Update GPIO Configuration Table */
1336 gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
1337 gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
1338
1339 gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
1340 gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
1341
1342 gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
1343 gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
1344
1345 gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
1346 gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
1347
1348 gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
1349 gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
1350
1351 gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
1352 gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
1353
1354 gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
1355 gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
1356
1357 gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
1358 gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
1359
1360 gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
1361 gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
1362
1363 gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
1364 gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
1365
1366 gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
1367 gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
1368
1369 gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
1370 gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
1371
1372 gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
1373 gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
1374
1375 gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
1376 gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
1377
1378 }
1379
1380 /*----------------------------------------------------------------------------+
1381 | update_uic_0_3_irq_ios().
1382 +----------------------------------------------------------------------------*/
1383 void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1384 {
1385 gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
1386 gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
1387
1388 gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
1389 gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
1390
1391 gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
1392 gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
1393
1394 gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
1395 gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
1396 }
1397
1398 /*----------------------------------------------------------------------------+
1399 | update_uic_4_9_irq_ios().
1400 +----------------------------------------------------------------------------*/
1401 void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1402 {
1403 gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
1404 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
1405
1406 gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
1407 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
1408
1409 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
1410 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
1411
1412 gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
1413 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
1414
1415 gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
1416 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
1417 }
1418
1419 /*----------------------------------------------------------------------------+
1420 | update_dma_a_b_ios().
1421 +----------------------------------------------------------------------------*/
1422 void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1423 {
1424 gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
1425 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
1426
1427 gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
1428 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
1429
1430 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
1431 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
1432
1433 gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
1434 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
1435
1436 gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
1437 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
1438 }
1439
1440 /*----------------------------------------------------------------------------+
1441 | update_dma_c_d_ios().
1442 +----------------------------------------------------------------------------*/
1443 void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1444 {
1445 gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
1446 gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
1447
1448 gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
1449 gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
1450
1451 gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
1452 gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
1453
1454 gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
1455 gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
1456
1457 gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
1458 gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
1459
1460 gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
1461 gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
1462
1463 }
1464
1465 /*----------------------------------------------------------------------------+
1466 | update_ebc_master_ios().
1467 +----------------------------------------------------------------------------*/
1468 void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1469 {
1470 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
1471 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
1472
1473 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
1474 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1475
1476 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
1477 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
1478
1479 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
1480 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
1481 }
1482
1483 /*----------------------------------------------------------------------------+
1484 | update_usb2_device_ios().
1485 +----------------------------------------------------------------------------*/
1486 void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1487 {
1488 gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
1489 gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
1490
1491 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
1492 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
1493
1494 gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
1495 gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
1496
1497 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
1498 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
1499
1500 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
1501 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
1502
1503 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
1504 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
1505
1506 gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
1507 gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
1508
1509 gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
1510 gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
1511
1512 }
1513
1514 /*----------------------------------------------------------------------------+
1515 | update_pci_patch_ios().
1516 +----------------------------------------------------------------------------*/
1517 void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1518 {
1519 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
1520 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1521 }
1522
1523 /*----------------------------------------------------------------------------+
1524 | set_chip_gpio_configuration(unsigned char gpio_core,
1525 | gpio_param_s (*gpio_tab)[GPIO_MAX])
1526 | Put the core impacted by clock modification and sharing in reset.
1527 | Config the select registers to resolve the sharing depending of the config.
1528 | Configure the GPIO registers.
1529 |
1530 +----------------------------------------------------------------------------*/
1531 void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX])
1532 {
1533 unsigned char i=0, j=0, reg_offset = 0;
1534 unsigned long gpio_reg, gpio_core_add;
1535
1536 /* GPIO config of the GPIOs 0 to 31 */
1537 for (i=0; i<GPIO_MAX; i++, j++)
1538 {
1539 if (i == GPIO_MAX/2)
1540 {
1541 reg_offset = 4;
1542 j = i-16;
1543 }
1544
1545 gpio_core_add = gpio_tab[gpio_core][i].add;
1546
1547 if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
1548 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1549 {
1550 switch (gpio_tab[gpio_core][i].alt_nb)
1551 {
1552 case GPIO_SEL:
1553 break;
1554
1555 case GPIO_ALT1:
1556 gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1557 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1558 out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
1559 break;
1560
1561 case GPIO_ALT2:
1562 gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1563 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1564 out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
1565 break;
1566
1567 case GPIO_ALT3:
1568 gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1569 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1570 out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
1571 break;
1572 }
1573 }
1574 if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
1575 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1576 {
1577
1578 switch (gpio_tab[gpio_core][i].alt_nb)
1579 {
1580 case GPIO_SEL:
1581 break;
1582 case GPIO_ALT1:
1583 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1584 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1585 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1586 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1587 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1588 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1589 break;
1590 case GPIO_ALT2:
1591 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1592 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1593 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1594 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1595 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1596 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1597 break;
1598 case GPIO_ALT3:
1599 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1600 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1601 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1602 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1603 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1604 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1605 break;
1606 }
1607 }
1608 }
1609 }
1610
1611 /*----------------------------------------------------------------------------+
1612 | force_bup_core_selection.
1613 +----------------------------------------------------------------------------*/
1614 void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
1615 {
1616 /* Pointer invalid */
1617 if (core_select_P == NULL)
1618 {
1619 printf("Configuration invalid pointer 1\n");
1620 for (;;)
1621 ;
1622 }
1623
1624 /* L4 Selection */
1625 *(core_select_P+UART_CORE0) = CORE_SELECTED;
1626 *(core_select_P+UART_CORE1) = CORE_SELECTED;
1627 *(core_select_P+UART_CORE2) = CORE_SELECTED;
1628 *(core_select_P+UART_CORE3) = CORE_SELECTED;
1629
1630 /* RMII Selection */
1631 *(core_select_P+RMII_SEL) = CORE_SELECTED;
1632
1633 /* External Interrupt 0-9 selection */
1634 *(core_select_P+UIC_0_3) = CORE_SELECTED;
1635 *(core_select_P+UIC_4_9) = CORE_SELECTED;
1636
1637 *(core_select_P+SCP_CORE) = CORE_SELECTED;
1638 *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
1639 *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
1640 *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
1641
1642 if (is_nand_selected()) {
1643 *(core_select_P+NAND_FLASH) = CORE_SELECTED;
1644 }
1645
1646 *config_val_P = CONFIG_IS_VALID;
1647
1648 }
1649
1650 /*----------------------------------------------------------------------------+
1651 | configure_ppc440ep_pins.
1652 +----------------------------------------------------------------------------*/
1653 void configure_ppc440ep_pins(void)
1654 {
1655 uart_config_nb_t uart_configuration;
1656 config_validity_t config_val = CONFIG_IS_INVALID;
1657
1658 /* Create Core Selection Table */
1659 core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
1660 {
1661 CORE_NOT_SELECTED, /* IIC_CORE, */
1662 CORE_NOT_SELECTED, /* SPC_CORE, */
1663 CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
1664 CORE_NOT_SELECTED, /* UIC_4_9, */
1665 CORE_NOT_SELECTED, /* USB2_HOST, */
1666 CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
1667 CORE_NOT_SELECTED, /* USB2_DEVICE, */
1668 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
1669 CORE_NOT_SELECTED, /* USB1_DEVICE, */
1670 CORE_NOT_SELECTED, /* EBC_MASTER, */
1671 CORE_NOT_SELECTED, /* NAND_FLASH, */
1672 CORE_NOT_SELECTED, /* UART_CORE0, */
1673 CORE_NOT_SELECTED, /* UART_CORE1, */
1674 CORE_NOT_SELECTED, /* UART_CORE2, */
1675 CORE_NOT_SELECTED, /* UART_CORE3, */
1676 CORE_NOT_SELECTED, /* MII_SEL, */
1677 CORE_NOT_SELECTED, /* RMII_SEL, */
1678 CORE_NOT_SELECTED, /* SMII_SEL, */
1679 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
1680 CORE_NOT_SELECTED, /* UIC_0_3 */
1681 CORE_NOT_SELECTED, /* USB1_HOST */
1682 CORE_NOT_SELECTED /* PCI_PATCH */
1683 };
1684
1685 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
1686
1687 /* Table Default Initialisation + FPGA Access */
1688 init_default_gpio(gpio_tab);
1689 set_chip_gpio_configuration(GPIO0, gpio_tab);
1690 set_chip_gpio_configuration(GPIO1, gpio_tab);
1691
1692 /* Update Table */
1693 force_bup_core_selection(ppc440ep_core_selection, &config_val);
1694 #if 0 /* test-only */
1695 /* If we are running PIBS 1, force known configuration */
1696 update_core_selection_table(ppc440ep_core_selection, &config_val);
1697 #endif
1698
1699 /*----------------------------------------------------------------------------+
1700 | SDR + ios table update + fpga initialization
1701 +----------------------------------------------------------------------------*/
1702 unsigned long sdr0_pfc1 = 0;
1703 unsigned long sdr0_usb0 = 0;
1704 unsigned long sdr0_mfr = 0;
1705
1706 /* PCI Always selected */
1707
1708 /* I2C Selection */
1709 if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
1710 {
1711 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
1712 iic1_selection_in_fpga();
1713 }
1714
1715 /* SCP Selection */
1716 if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
1717 {
1718 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
1719 scp_selection_in_fpga();
1720 }
1721
1722 /* UIC 0:3 Selection */
1723 if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
1724 {
1725 update_uic_0_3_irq_ios(gpio_tab);
1726 dma_a_b_unselect_in_fpga();
1727 }
1728
1729 /* UIC 4:9 Selection */
1730 if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
1731 {
1732 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
1733 update_uic_4_9_irq_ios(gpio_tab);
1734 }
1735
1736 /* DMA AB Selection */
1737 if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
1738 {
1739 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
1740 update_dma_a_b_ios(gpio_tab);
1741 dma_a_b_selection_in_fpga();
1742 }
1743
1744 /* DMA CD Selection */
1745 if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
1746 {
1747 update_dma_c_d_ios(gpio_tab);
1748 dma_c_d_selection_in_fpga();
1749 }
1750
1751 /* EBC Master Selection */
1752 if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
1753 {
1754 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
1755 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1756 update_ebc_master_ios(gpio_tab);
1757 }
1758
1759 /* PCI Patch Enable */
1760 if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
1761 {
1762 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1763 update_pci_patch_ios(gpio_tab);
1764 }
1765
1766 /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
1767 if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
1768 {
1769 /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
1770 printf("Invalid configuration => USB2 Host selected\n");
1771 for (;;)
1772 ;
1773 /*usb2_host_selection_in_fpga(); */
1774 }
1775
1776 /* USB2.0 Device Selection */
1777 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
1778 {
1779 update_usb2_device_ios(gpio_tab);
1780 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
1781 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
1782
1783 mfsdr(SDR0_USB0, sdr0_usb0);
1784 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1785 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
1786 mtsdr(SDR0_USB0, sdr0_usb0);
1787
1788 usb2_device_selection_in_fpga();
1789 }
1790
1791 /* USB1.1 Device Selection */
1792 if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
1793 {
1794 mfsdr(SDR0_USB0, sdr0_usb0);
1795 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1796 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
1797 mtsdr(SDR0_USB0, sdr0_usb0);
1798 }
1799
1800 /* USB1.1 Host Selection */
1801 if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
1802 {
1803 mfsdr(SDR0_USB0, sdr0_usb0);
1804 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
1805 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
1806 mtsdr(SDR0_USB0, sdr0_usb0);
1807 }
1808
1809 /* NAND Flash Selection */
1810 if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
1811 {
1812 update_ndfc_ios(gpio_tab);
1813
1814 #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
1815 mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
1816 SDR0_CUST0_NDFC_ENABLE |
1817 SDR0_CUST0_NDFC_BW_8_BIT |
1818 SDR0_CUST0_NDFC_ARE_MASK |
1819 SDR0_CUST0_CHIPSELGAT_EN1 |
1820 SDR0_CUST0_CHIPSELGAT_EN2);
1821 #else
1822 mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
1823 SDR0_CUST0_NDFC_ENABLE |
1824 SDR0_CUST0_NDFC_BW_8_BIT |
1825 SDR0_CUST0_NDFC_ARE_MASK |
1826 SDR0_CUST0_CHIPSELGAT_EN0 |
1827 SDR0_CUST0_CHIPSELGAT_EN2);
1828 #endif
1829
1830 ndfc_selection_in_fpga();
1831 }
1832 else
1833 {
1834 /* Set Mux on EMAC */
1835 mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_EMAC_SEL);
1836 }
1837
1838 /* MII Selection */
1839 if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
1840 {
1841 update_zii_ios(gpio_tab);
1842 mfsdr(SDR0_MFR, sdr0_mfr);
1843 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
1844 mtsdr(SDR0_MFR, sdr0_mfr);
1845
1846 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
1847 }
1848
1849 /* RMII Selection */
1850 if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
1851 {
1852 update_zii_ios(gpio_tab);
1853 mfsdr(SDR0_MFR, sdr0_mfr);
1854 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
1855 mtsdr(SDR0_MFR, sdr0_mfr);
1856
1857 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
1858 }
1859
1860 /* SMII Selection */
1861 if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
1862 {
1863 update_zii_ios(gpio_tab);
1864 mfsdr(SDR0_MFR, sdr0_mfr);
1865 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
1866 mtsdr(SDR0_MFR, sdr0_mfr);
1867
1868 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
1869 }
1870
1871 /* UART Selection */
1872 uart_configuration = get_uart_configuration();
1873 switch (uart_configuration)
1874 {
1875 case L1: /* L1 Selection */
1876 /* UART0 8 pins Only */
1877 /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
1878 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
1879 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
1880 break;
1881 case L2: /* L2 Selection */
1882 /* UART0 and UART1 4 pins */
1883 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1884 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1885 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1886 break;
1887 case L3: /* L3 Selection */
1888 /* UART0 4 pins, UART1 and UART2 2 pins */
1889 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1890 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1891 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1892 break;
1893 case L4: /* L4 Selection */
1894 /* UART0, UART1, UART2 and UART3 2 pins */
1895 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
1896 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1897 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1898 break;
1899 }
1900 update_uart_ios(uart_configuration, gpio_tab);
1901
1902 /* UART Selection in all cases */
1903 uart_selection_in_fpga(uart_configuration);
1904
1905 /* Packet Reject Function Available */
1906 if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
1907 {
1908 /* Set UPR Bit in SDR0_PFC1 Register */
1909 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
1910 }
1911
1912 /* Packet Reject Function Enable */
1913 if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
1914 {
1915 mfsdr(SDR0_MFR, sdr0_mfr);
1916 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
1917 mtsdr(SDR0_MFR, sdr0_mfr);
1918 }
1919
1920 /* Perform effective access to hardware */
1921 mtsdr(SDR0_PFC1, sdr0_pfc1);
1922 set_chip_gpio_configuration(GPIO0, gpio_tab);
1923 set_chip_gpio_configuration(GPIO1, gpio_tab);
1924
1925 /* USB2.0 Device Reset must be done after GPIO setting */
1926 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
1927 usb2_device_reset_through_fpga();
1928
1929 }
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