]> git.ipfire.org Git - people/ms/u-boot.git/blob - board/amcc/bamboo/bamboo.c
projects / people / ms / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge remote branch 'u-boot-ppc4xx/master'
[people/ms/u-boot.git] / board / amcc / bamboo / bamboo.c
1 /*
2 * (C) Copyright 2005-2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <common.h>
25 #include <asm/processor.h>
26 #include <asm/gpio.h>
27 #include <spd_sdram.h>
28 #include <ppc440.h>
29 #include "bamboo.h"
30
31 void ext_bus_cntlr_init(void);
32 void configure_ppc440ep_pins(void);
33 int is_nand_selected(void);
34
35 #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
36 /*************************************************************************
37 *
38 * Bamboo has one bank onboard sdram (plus DIMM)
39 *
40 * Fixed memory is composed of :
41 * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
42 * 13 row add bits, 10 column add bits (but 12 row used only).
43 * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
44 * 12 row add bits, 10 column add bits.
45 * Prepare a subset (only the used ones) of SPD data
46 *
47 * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
48 * the corresponding bank is divided by 2 due to number of Row addresses
49 * 12 in the ECC module
50 *
51 * Assumes: 64 MB, ECC, non-registered
52 * PLB @ 133 MHz
53 *
54 ************************************************************************/
55 const unsigned char cfg_simulate_spd_eeprom[128] = {
56 0x80, /* number of SPD bytes used: 128 */
57 0x08, /* total number bytes in SPD device = 256 */
58 0x07, /* DDR ram */
59 #ifdef CONFIG_DDR_ECC
60 0x0C, /* num Row Addr: 12 */
61 #else
62 0x0D, /* num Row Addr: 13 */
63 #endif
64 0x09, /* numColAddr: 9 */
65 0x01, /* numBanks: 1 */
66 0x20, /* Module data width: 32 bits */
67 0x00, /* Module data width continued: +0 */
68 0x04, /* 2.5 Volt */
69 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
70 0x00, /* SDRAM Access from clock */
71 #ifdef CONFIG_DDR_ECC
72 0x02, /* ECC ON : 02 OFF : 00 */
73 #else
74 0x00, /* ECC ON : 02 OFF : 00 */
75 #endif
76 0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */
77 0,
78 0,
79 0x01, /* wcsbc = 1 */
80 0,
81 0,
82 0x0C, /* casBit (2,2.5) */
83 0,
84 0,
85 0x00, /* not registered: 0 registered : 0x02*/
86 0,
87 0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */
88 0,
89 0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */
90 0,
91 0x50, /* tRpNs = 20 ns */
92 0,
93 0x50, /* tRcdNs = 20 ns */
94 45, /* tRasNs */
95 #ifdef CONFIG_DDR_ECC
96 0x08, /* bankSizeID: 32MB */
97 #else
98 0x10, /* bankSizeID: 64MB */
99 #endif
100 0,
101 0,
102 0,
103 0,
104 0,
105 0,
106 0,
107 0,
108 0,
109 0,
110 0,
111 0,
112 0,
113 0,
114 0,
115 0,
116 0,
117 0,
118 0,
119 0,
120 0,
121 0,
122 0,
123 0,
124 0,
125 0,
126 0,
127 0,
128 0,
129 0,
130 0,
131 0,
132 0,
133 0,
134 0,
135 0,
136 0,
137 0,
138 0,
139 0,
140 0,
141 0,
142 0,
143 0,
144 0,
145 0,
146 0,
147 0,
148 0,
149 0,
150 0,
151 0,
152 0,
153 0,
154 0,
155 0,
156 0,
157 0,
158 0,
159 0,
160 0,
161 0,
162 0,
163 0,
164 0,
165 0,
166 0,
167 0,
168 0,
169 0,
170 0,
171 0,
172 0,
173 0,
174 0,
175 0,
176 0,
177 0,
178 0,
179 0,
180 0,
181 0,
182 0,
183 0,
184 0,
185 0,
186 0,
187 0,
188 0,
189 0,
190 0,
191 0,
192 0,
193 0,
194 0,
195 0
196 };
197 #endif
198
199 #if 0
200 { /* GPIO Alternate1 Alternate2 Alternate3 */
201 {
202 /* GPIO Core 0 */
203 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
204 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
205 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
206 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
207 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
208 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
209 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
210 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
211 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
212 { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
213 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
214 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
215 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
216 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
217 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
218 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
219 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
220 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
221 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
222 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
223 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
224 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
225 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
226 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
227 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
228 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
229 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
230 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
231 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
232 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
233 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
234 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
235 },
236 {
237 /* GPIO Core 1 */
238 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
239 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
240 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
241 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
242 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
243 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
244 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
245 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
246 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
247 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
248 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
249 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
250 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
251 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
252 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
253 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
254 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
255 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
256 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
257 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
258 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
259 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
260 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
261 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
262 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
263 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
264 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
265 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
266 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
267 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
268 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
269 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
270 }
271 };
272 #endif
273
274 /*----------------------------------------------------------------------------+
275 | EBC Devices Characteristics
276 | Peripheral Bank Access Parameters - EBC0_BnAP
277 | Peripheral Bank Configuration Register - EBC0_BnCR
278 +----------------------------------------------------------------------------*/
279 /* Small Flash */
280 #define EBC0_BNAP_SMALL_FLASH \
281 EBC0_BNAP_BME_DISABLED | \
282 EBC0_BNAP_TWT_ENCODE(6) | \
283 EBC0_BNAP_CSN_ENCODE(0) | \
284 EBC0_BNAP_OEN_ENCODE(1) | \
285 EBC0_BNAP_WBN_ENCODE(1) | \
286 EBC0_BNAP_WBF_ENCODE(3) | \
287 EBC0_BNAP_TH_ENCODE(1) | \
288 EBC0_BNAP_RE_ENABLED | \
289 EBC0_BNAP_SOR_DELAYED | \
290 EBC0_BNAP_BEM_WRITEONLY | \
291 EBC0_BNAP_PEN_DISABLED
292
293 #define EBC0_BNCR_SMALL_FLASH_CS0 \
294 EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
295 EBC0_BNCR_BS_1MB | \
296 EBC0_BNCR_BU_RW | \
297 EBC0_BNCR_BW_8BIT
298
299 #define EBC0_BNCR_SMALL_FLASH_CS4 \
300 EBC0_BNCR_BAS_ENCODE(0x87F00000) | \
301 EBC0_BNCR_BS_1MB | \
302 EBC0_BNCR_BU_RW | \
303 EBC0_BNCR_BW_8BIT
304
305 /* Large Flash or SRAM */
306 #define EBC0_BNAP_LARGE_FLASH_OR_SRAM \
307 EBC0_BNAP_BME_DISABLED | \
308 EBC0_BNAP_TWT_ENCODE(8) | \
309 EBC0_BNAP_CSN_ENCODE(0) | \
310 EBC0_BNAP_OEN_ENCODE(1) | \
311 EBC0_BNAP_WBN_ENCODE(1) | \
312 EBC0_BNAP_WBF_ENCODE(1) | \
313 EBC0_BNAP_TH_ENCODE(2) | \
314 EBC0_BNAP_SOR_DELAYED | \
315 EBC0_BNAP_BEM_RW | \
316 EBC0_BNAP_PEN_DISABLED
317
318 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \
319 EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
320 EBC0_BNCR_BS_8MB | \
321 EBC0_BNCR_BU_RW | \
322 EBC0_BNCR_BW_16BIT
323
324
325 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \
326 EBC0_BNCR_BAS_ENCODE(0x87800000) | \
327 EBC0_BNCR_BS_8MB | \
328 EBC0_BNCR_BU_RW | \
329 EBC0_BNCR_BW_16BIT
330
331 /* NVRAM - FPGA */
332 #define EBC0_BNAP_NVRAM_FPGA \
333 EBC0_BNAP_BME_DISABLED | \
334 EBC0_BNAP_TWT_ENCODE(9) | \
335 EBC0_BNAP_CSN_ENCODE(0) | \
336 EBC0_BNAP_OEN_ENCODE(1) | \
337 EBC0_BNAP_WBN_ENCODE(1) | \
338 EBC0_BNAP_WBF_ENCODE(0) | \
339 EBC0_BNAP_TH_ENCODE(2) | \
340 EBC0_BNAP_RE_ENABLED | \
341 EBC0_BNAP_SOR_DELAYED | \
342 EBC0_BNAP_BEM_WRITEONLY | \
343 EBC0_BNAP_PEN_DISABLED
344
345 #define EBC0_BNCR_NVRAM_FPGA_CS5 \
346 EBC0_BNCR_BAS_ENCODE(0x80000000) | \
347 EBC0_BNCR_BS_1MB | \
348 EBC0_BNCR_BU_RW | \
349 EBC0_BNCR_BW_8BIT
350
351 /* Nand Flash */
352 #define EBC0_BNAP_NAND_FLASH \
353 EBC0_BNAP_BME_DISABLED | \
354 EBC0_BNAP_TWT_ENCODE(3) | \
355 EBC0_BNAP_CSN_ENCODE(0) | \
356 EBC0_BNAP_OEN_ENCODE(0) | \
357 EBC0_BNAP_WBN_ENCODE(0) | \
358 EBC0_BNAP_WBF_ENCODE(0) | \
359 EBC0_BNAP_TH_ENCODE(1) | \
360 EBC0_BNAP_RE_ENABLED | \
361 EBC0_BNAP_SOR_NOT_DELAYED | \
362 EBC0_BNAP_BEM_RW | \
363 EBC0_BNAP_PEN_DISABLED
364
365
366 #define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
367
368 /* NAND0 */
369 #define EBC0_BNCR_NAND_FLASH_CS1 \
370 EBC0_BNCR_BAS_ENCODE(0x90000000) | \
371 EBC0_BNCR_BS_1MB | \
372 EBC0_BNCR_BU_RW | \
373 EBC0_BNCR_BW_32BIT
374 /* NAND1 - Bank2 */
375 #define EBC0_BNCR_NAND_FLASH_CS2 \
376 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
377 EBC0_BNCR_BS_1MB | \
378 EBC0_BNCR_BU_RW | \
379 EBC0_BNCR_BW_32BIT
380
381 /* NAND1 - Bank3 */
382 #define EBC0_BNCR_NAND_FLASH_CS3 \
383 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
384 EBC0_BNCR_BS_1MB | \
385 EBC0_BNCR_BU_RW | \
386 EBC0_BNCR_BW_32BIT
387
388 int board_early_init_f(void)
389 {
390 ext_bus_cntlr_init();
391
392 /*--------------------------------------------------------------------
393 * Setup the interrupt controller polarities, triggers, etc.
394 *-------------------------------------------------------------------*/
395 mtdcr(uic0sr, 0xffffffff); /* clear all */
396 mtdcr(uic0er, 0x00000000); /* disable all */
397 mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
398 mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
399 mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
400 mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
401 mtdcr(uic0sr, 0xffffffff); /* clear all */
402
403 mtdcr(uic1sr, 0xffffffff); /* clear all */
404 mtdcr(uic1er, 0x00000000); /* disable all */
405 mtdcr(uic1cr, 0x00000000); /* all non-critical */
406 mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
407 mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
408 mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
409 mtdcr(uic1sr, 0xffffffff); /* clear all */
410
411 /*--------------------------------------------------------------------
412 * Setup the GPIO pins
413 *-------------------------------------------------------------------*/
414 out32(GPIO0_OSRL, 0x00000400);
415 out32(GPIO0_OSRH, 0x00000000);
416 out32(GPIO0_TSRL, 0x00000400);
417 out32(GPIO0_TSRH, 0x00000000);
418 out32(GPIO0_ISR1L, 0x00000000);
419 out32(GPIO0_ISR1H, 0x00000000);
420 out32(GPIO0_ISR2L, 0x00000000);
421 out32(GPIO0_ISR2H, 0x00000000);
422 out32(GPIO0_ISR3L, 0x00000000);
423 out32(GPIO0_ISR3H, 0x00000000);
424
425 out32(GPIO1_OSRL, 0x0C380000);
426 out32(GPIO1_OSRH, 0x00000000);
427 out32(GPIO1_TSRL, 0x0C380000);
428 out32(GPIO1_TSRH, 0x00000000);
429 out32(GPIO1_ISR1L, 0x0FC30000);
430 out32(GPIO1_ISR1H, 0x00000000);
431 out32(GPIO1_ISR2L, 0x0C010000);
432 out32(GPIO1_ISR2H, 0x00000000);
433 out32(GPIO1_ISR3L, 0x01400000);
434 out32(GPIO1_ISR3H, 0x00000000);
435
436 configure_ppc440ep_pins();
437
438 return 0;
439 }
440
441 int checkboard(void)
442 {
443 char *s = getenv("serial#");
444
445 printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
446 if (s != NULL) {
447 puts(", serial# ");
448 puts(s);
449 }
450 putc('\n');
451
452 return (0);
453 }
454
455
456 long int initdram (int board_type)
457 {
458 #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
459 long dram_size;
460
461 dram_size = spd_sdram();
462
463 return dram_size;
464 #else
465 return CFG_MBYTES_SDRAM << 20;
466 #endif
467 }
468
469 #if defined(CFG_DRAM_TEST)
470 int testdram(void)
471 {
472 unsigned long *mem = (unsigned long *)0;
473 const unsigned long kend = (1024 / sizeof(unsigned long));
474 unsigned long k, n, *p32, ctr;
475 const unsigned long bend = CFG_MBYTES_SDRAM * 1024 * 1024;
476
477 mtmsr(0);
478
479 for (k = 0; k < CFG_MBYTES_SDRAM*1024;
480 ++k, mem += (1024 / sizeof(unsigned long))) {
481 if ((k & 1023) == 0) {
482 printf("%3d MB\r", k / 1024);
483 }
484
485 memset(mem, 0xaaaaaaaa, 1024);
486 for (n = 0; n < kend; ++n) {
487 if (mem[n] != 0xaaaaaaaa) {
488 printf("SDRAM test fails at: %08x\n",
489 (uint) & mem[n]);
490 return 1;
491 }
492 }
493
494 memset(mem, 0x55555555, 1024);
495 for (n = 0; n < kend; ++n) {
496 if (mem[n] != 0x55555555) {
497 printf("SDRAM test fails at: %08x\n",
498 (uint) & mem[n]);
499 return 1;
500 }
501 }
502 }
503
504 /*
505 * Perform a sequence test to ensure that all
506 * memory locations are uniquely addressable
507 */
508 ctr = 0;
509 p32 = 0;
510 while ((unsigned long)p32 != bend) {
511 if (0 == ((unsigned long)p32 & ((1<<20)-1)))
512 printf("Writing %3d MB\r", (unsigned long)p32 >> 20);
513 *p32++ = ctr++;
514 }
515
516 ctr = 0;
517 p32 = 0;
518 while ((unsigned long)p32 != bend) {
519 if (0 == ((unsigned long)p32 & ((1<<20)-1)))
520 printf("Verifying %3d MB\r", (unsigned long)p32 >> 20);
521
522 if (*p32 != ctr) {
523 printf("SDRAM test fails at: %08x\n", p32);
524 return 1;
525 }
526
527 ctr++;
528 p32++;
529 }
530
531 printf("SDRAM test passes\n");
532 return 0;
533 }
534 #endif
535
536 /*************************************************************************
537 * pci_pre_init
538 *
539 * This routine is called just prior to registering the hose and gives
540 * the board the opportunity to check things. Returning a value of zero
541 * indicates that things are bad & PCI initialization should be aborted.
542 *
543 * Different boards may wish to customize the pci controller structure
544 * (add regions, override default access routines, etc) or perform
545 * certain pre-initialization actions.
546 *
547 ************************************************************************/
548 #if defined(CONFIG_PCI)
549 int pci_pre_init(struct pci_controller *hose)
550 {
551 unsigned long addr;
552
553 /*-------------------------------------------------------------------------+
554 | Set priority for all PLB3 devices to 0.
555 | Set PLB3 arbiter to fair mode.
556 +-------------------------------------------------------------------------*/
557 mfsdr(sdr_amp1, addr);
558 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
559 addr = mfdcr(plb3_acr);
560 mtdcr(plb3_acr, addr | 0x80000000);
561
562 /*-------------------------------------------------------------------------+
563 | Set priority for all PLB4 devices to 0.
564 +-------------------------------------------------------------------------*/
565 mfsdr(sdr_amp0, addr);
566 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
567 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
568 mtdcr(plb4_acr, addr);
569
570 /*-------------------------------------------------------------------------+
571 | Set Nebula PLB4 arbiter to fair mode.
572 +-------------------------------------------------------------------------*/
573 /* Segment0 */
574 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
575 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
576 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
577 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
578 mtdcr(plb0_acr, addr);
579
580 /* Segment1 */
581 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
582 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
583 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
584 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
585 mtdcr(plb1_acr, addr);
586
587 return 1;
588 }
589 #endif /* defined(CONFIG_PCI) */
590
591 /*************************************************************************
592 * pci_target_init
593 *
594 * The bootstrap configuration provides default settings for the pci
595 * inbound map (PIM). But the bootstrap config choices are limited and
596 * may not be sufficient for a given board.
597 *
598 ************************************************************************/
599 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
600 void pci_target_init(struct pci_controller *hose)
601 {
602 /*--------------------------------------------------------------------------+
603 * Set up Direct MMIO registers
604 *--------------------------------------------------------------------------*/
605 /*--------------------------------------------------------------------------+
606 | PowerPC440 EP PCI Master configuration.
607 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
608 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
609 | Use byte reversed out routines to handle endianess.
610 | Make this region non-prefetchable.
611 +--------------------------------------------------------------------------*/
612 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
613 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
614 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
615 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
616 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
617
618 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
619 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
620 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
621 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
622 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
623
624 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
625 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
626 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
627 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
628
629 /*--------------------------------------------------------------------------+
630 * Set up Configuration registers
631 *--------------------------------------------------------------------------*/
632
633 /* Program the board's subsystem id/vendor id */
634 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
635 CFG_PCI_SUBSYS_VENDORID);
636 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
637
638 /* Configure command register as bus master */
639 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
640
641 /* 240nS PCI clock */
642 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
643
644 /* No error reporting */
645 pci_write_config_word(0, PCI_ERREN, 0);
646
647 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
648
649 }
650 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
651
652 /*************************************************************************
653 * pci_master_init
654 *
655 ************************************************************************/
656 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
657 void pci_master_init(struct pci_controller *hose)
658 {
659 unsigned short temp_short;
660
661 /*--------------------------------------------------------------------------+
662 | Write the PowerPC440 EP PCI Configuration regs.
663 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
664 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
665 +--------------------------------------------------------------------------*/
666 pci_read_config_word(0, PCI_COMMAND, &temp_short);
667 pci_write_config_word(0, PCI_COMMAND,
668 temp_short | PCI_COMMAND_MASTER |
669 PCI_COMMAND_MEMORY);
670 }
671 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
672
673 /*************************************************************************
674 * is_pci_host
675 *
676 * This routine is called to determine if a pci scan should be
677 * performed. With various hardware environments (especially cPCI and
678 * PPMC) it's insufficient to depend on the state of the arbiter enable
679 * bit in the strap register, or generic host/adapter assumptions.
680 *
681 * Rather than hard-code a bad assumption in the general 440 code, the
682 * 440 pci code requires the board to decide at runtime.
683 *
684 * Return 0 for adapter mode, non-zero for host (monarch) mode.
685 *
686 *
687 ************************************************************************/
688 #if defined(CONFIG_PCI)
689 int is_pci_host(struct pci_controller *hose)
690 {
691 /* Bamboo is always configured as host. */
692 return (1);
693 }
694 #endif /* defined(CONFIG_PCI) */
695
696 /*----------------------------------------------------------------------------+
697 | is_powerpc440ep_pass1.
698 +----------------------------------------------------------------------------*/
699 int is_powerpc440ep_pass1(void)
700 {
701 unsigned long pvr;
702
703 pvr = get_pvr();
704
705 if (pvr == PVR_POWERPC_440EP_PASS1)
706 return TRUE;
707 else if (pvr == PVR_POWERPC_440EP_PASS2)
708 return FALSE;
709 else {
710 printf("brdutil error 3\n");
711 for (;;)
712 ;
713 }
714
715 return(FALSE);
716 }
717
718 /*----------------------------------------------------------------------------+
719 | is_nand_selected.
720 +----------------------------------------------------------------------------*/
721 int is_nand_selected(void)
722 {
723 #ifdef CONFIG_BAMBOO_NAND
724 return TRUE;
725 #else
726 return FALSE;
727 #endif
728 }
729
730 /*----------------------------------------------------------------------------+
731 | config_on_ebc_cs4_is_small_flash => from EPLD
732 +----------------------------------------------------------------------------*/
733 unsigned char config_on_ebc_cs4_is_small_flash(void)
734 {
735 /* Not implemented yet => returns constant value */
736 return TRUE;
737 }
738
739 /*----------------------------------------------------------------------------+
740 | Ext_bus_cntlr_init.
741 | Initialize the external bus controller
742 +----------------------------------------------------------------------------*/
743 void ext_bus_cntlr_init(void)
744 {
745 unsigned long sdr0_pstrp0, sdr0_sdstp1;
746 unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
747 int computed_boot_device = BOOT_DEVICE_UNKNOWN;
748 unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
749 unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
750 unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
751 unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
752 unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
753
754
755 /*-------------------------------------------------------------------------+
756 |
757 | PART 1 : Initialize EBC Bank 5
758 | ==============================
759 | Bank5 is always associated to the NVRAM/EPLD.
760 | It has to be initialized prior to other banks settings computation since
761 | some board registers values may be needed
762 |
763 +-------------------------------------------------------------------------*/
764 /* NVRAM - FPGA */
765 mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA);
766 mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5);
767
768 /*-------------------------------------------------------------------------+
769 |
770 | PART 2 : Determine which boot device was selected
771 | =========================================
772 |
773 | Read Pin Strap Register in PPC440EP
774 | In case of boot from IIC, read Serial Device Strap Register1
775 |
776 | Result can either be :
777 | - Boot from EBC 8bits => SMALL FLASH
778 | - Boot from EBC 16bits => Large Flash or SRAM
779 | - Boot from NAND Flash
780 | - Boot from PCI
781 |
782 +-------------------------------------------------------------------------*/
783 /* Read Pin Strap Register in PPC440EP */
784 mfsdr(sdr_pstrp0, sdr0_pstrp0);
785 bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
786
787 /*-------------------------------------------------------------------------+
788 | PPC440EP Pass1
789 +-------------------------------------------------------------------------*/
790 if (is_powerpc440ep_pass1() == TRUE) {
791 switch(bootstrap_settings) {
792 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
793 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
794 /* Boot from Small Flash */
795 computed_boot_device = BOOT_FROM_SMALL_FLASH;
796 break;
797 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
798 /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
799 /* Boot from PCI */
800 computed_boot_device = BOOT_FROM_PCI;
801 break;
802
803 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
804 /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
805 /* Boot from Nand Flash */
806 computed_boot_device = BOOT_FROM_NAND_FLASH0;
807 break;
808
809 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
810 /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
811 /* Boot from Small Flash */
812 computed_boot_device = BOOT_FROM_SMALL_FLASH;
813 break;
814
815 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
816 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
817 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
818 /* Read Serial Device Strap Register1 in PPC440EP */
819 mfsdr(sdr_sdstp1, sdr0_sdstp1);
820 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
821 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
822
823 switch(boot_selection) {
824 case SDR0_SDSTP1_BOOT_SEL_EBC:
825 switch(ebc_boot_size) {
826 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
827 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
828 break;
829 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
830 computed_boot_device = BOOT_FROM_SMALL_FLASH;
831 break;
832 }
833 break;
834
835 case SDR0_SDSTP1_BOOT_SEL_PCI:
836 computed_boot_device = BOOT_FROM_PCI;
837 break;
838
839 case SDR0_SDSTP1_BOOT_SEL_NDFC:
840 computed_boot_device = BOOT_FROM_NAND_FLASH0;
841 break;
842 }
843 break;
844 }
845 }
846
847 /*-------------------------------------------------------------------------+
848 | PPC440EP Pass2
849 +-------------------------------------------------------------------------*/
850 else {
851 switch(bootstrap_settings) {
852 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
853 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
854 /* Boot from Small Flash */
855 computed_boot_device = BOOT_FROM_SMALL_FLASH;
856 break;
857 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
858 /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
859 /* Boot from PCI */
860 computed_boot_device = BOOT_FROM_PCI;
861 break;
862
863 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
864 /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
865 /* Boot from Nand Flash */
866 computed_boot_device = BOOT_FROM_NAND_FLASH0;
867 break;
868
869 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
870 /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
871 /* Boot from Large Flash or SRAM */
872 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
873 break;
874
875 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
876 /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
877 /* Boot from Large Flash or SRAM */
878 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
879 break;
880
881 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
882 /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
883 /* Boot from PCI */
884 computed_boot_device = BOOT_FROM_PCI;
885 break;
886
887 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
888 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
889 /* Default Strap Settings 5-7 */
890 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
891 /* Read Serial Device Strap Register1 in PPC440EP */
892 mfsdr(sdr_sdstp1, sdr0_sdstp1);
893 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
894 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
895
896 switch(boot_selection) {
897 case SDR0_SDSTP1_BOOT_SEL_EBC:
898 switch(ebc_boot_size) {
899 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
900 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
901 break;
902 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
903 computed_boot_device = BOOT_FROM_SMALL_FLASH;
904 break;
905 }
906 break;
907
908 case SDR0_SDSTP1_BOOT_SEL_PCI:
909 computed_boot_device = BOOT_FROM_PCI;
910 break;
911
912 case SDR0_SDSTP1_BOOT_SEL_NDFC:
913 computed_boot_device = BOOT_FROM_NAND_FLASH0;
914 break;
915 }
916 break;
917 }
918 }
919
920 /*-------------------------------------------------------------------------+
921 |
922 | PART 3 : Compute EBC settings depending on selected boot device
923 | ====== ======================================================
924 |
925 | Resulting EBC init will be among following configurations :
926 |
927 | - Boot from EBC 8bits => boot from SMALL FLASH selected
928 | EBC-CS0 = Small Flash
929 | EBC-CS1,2,3 = NAND Flash or
930 | Exp.Slot depending on Soft Config
931 | EBC-CS4 = SRAM/Large Flash or
932 | Large Flash/SRAM depending on jumpers
933 | EBC-CS5 = NVRAM / EPLD
934 |
935 | - Boot from EBC 16bits => boot from Large Flash or SRAM selected
936 | EBC-CS0 = SRAM/Large Flash or
937 | Large Flash/SRAM depending on jumpers
938 | EBC-CS1,2,3 = NAND Flash or
939 | Exp.Slot depending on Software Configuration
940 | EBC-CS4 = Small Flash
941 | EBC-CS5 = NVRAM / EPLD
942 |
943 | - Boot from NAND Flash
944 | EBC-CS0 = NAND Flash0
945 | EBC-CS1,2,3 = NAND Flash1
946 | EBC-CS4 = SRAM/Large Flash or
947 | Large Flash/SRAM depending on jumpers
948 | EBC-CS5 = NVRAM / EPLD
949 |
950 | - Boot from PCI
951 | EBC-CS0 = ...
952 | EBC-CS1,2,3 = NAND Flash or
953 | Exp.Slot depending on Software Configuration
954 | EBC-CS4 = SRAM/Large Flash or
955 | Large Flash/SRAM or
956 | Small Flash depending on jumpers
957 | EBC-CS5 = NVRAM / EPLD
958 |
959 +-------------------------------------------------------------------------*/
960
961 switch(computed_boot_device) {
962 /*------------------------------------------------------------------------- */
963 case BOOT_FROM_SMALL_FLASH:
964 /*------------------------------------------------------------------------- */
965 ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
966 ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
967 if ((is_nand_selected()) == TRUE) {
968 /* NAND Flash */
969 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
970 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
971 ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
972 ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
973 ebc0_cs3_bnap_value = 0;
974 ebc0_cs3_bncr_value = 0;
975 } else {
976 /* Expansion Slot */
977 ebc0_cs1_bnap_value = 0;
978 ebc0_cs1_bncr_value = 0;
979 ebc0_cs2_bnap_value = 0;
980 ebc0_cs2_bncr_value = 0;
981 ebc0_cs3_bnap_value = 0;
982 ebc0_cs3_bncr_value = 0;
983 }
984 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
985 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
986
987 break;
988
989 /*------------------------------------------------------------------------- */
990 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
991 /*------------------------------------------------------------------------- */
992 ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
993 ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
994 if ((is_nand_selected()) == TRUE) {
995 /* NAND Flash */
996 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
997 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
998 ebc0_cs2_bnap_value = 0;
999 ebc0_cs2_bncr_value = 0;
1000 ebc0_cs3_bnap_value = 0;
1001 ebc0_cs3_bncr_value = 0;
1002 } else {
1003 /* Expansion Slot */
1004 ebc0_cs1_bnap_value = 0;
1005 ebc0_cs1_bncr_value = 0;
1006 ebc0_cs2_bnap_value = 0;
1007 ebc0_cs2_bncr_value = 0;
1008 ebc0_cs3_bnap_value = 0;
1009 ebc0_cs3_bncr_value = 0;
1010 }
1011 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
1012 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
1013
1014 break;
1015
1016 /*------------------------------------------------------------------------- */
1017 case BOOT_FROM_NAND_FLASH0:
1018 /*------------------------------------------------------------------------- */
1019 ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH;
1020 ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
1021
1022 ebc0_cs1_bnap_value = 0;
1023 ebc0_cs1_bncr_value = 0;
1024 ebc0_cs2_bnap_value = 0;
1025 ebc0_cs2_bncr_value = 0;
1026 ebc0_cs3_bnap_value = 0;
1027 ebc0_cs3_bncr_value = 0;
1028
1029 /* Large Flash or SRAM */
1030 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
1031 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
1032
1033 break;
1034
1035 /*------------------------------------------------------------------------- */
1036 case BOOT_FROM_PCI:
1037 /*------------------------------------------------------------------------- */
1038 ebc0_cs0_bnap_value = 0;
1039 ebc0_cs0_bncr_value = 0;
1040
1041 if ((is_nand_selected()) == TRUE) {
1042 /* NAND Flash */
1043 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
1044 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
1045 ebc0_cs2_bnap_value = 0;
1046 ebc0_cs2_bncr_value = 0;
1047 ebc0_cs3_bnap_value = 0;
1048 ebc0_cs3_bncr_value = 0;
1049 } else {
1050 /* Expansion Slot */
1051 ebc0_cs1_bnap_value = 0;
1052 ebc0_cs1_bncr_value = 0;
1053 ebc0_cs2_bnap_value = 0;
1054 ebc0_cs2_bncr_value = 0;
1055 ebc0_cs3_bnap_value = 0;
1056 ebc0_cs3_bncr_value = 0;
1057 }
1058
1059 if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
1060 /* Small Flash */
1061 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
1062 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
1063 } else {
1064 /* Large Flash or SRAM */
1065 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
1066 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
1067 }
1068
1069 break;
1070
1071 /*------------------------------------------------------------------------- */
1072 case BOOT_DEVICE_UNKNOWN:
1073 /*------------------------------------------------------------------------- */
1074 /* Error */
1075 break;
1076
1077 }
1078
1079
1080 /*-------------------------------------------------------------------------+
1081 | Initialize EBC CONFIG
1082 +-------------------------------------------------------------------------*/
1083 mtdcr(ebccfga, xbcfg);
1084 mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN |
1085 EBC0_CFG_PTD_ENABLED |
1086 EBC0_CFG_RTC_2048PERCLK |
1087 EBC0_CFG_EMPL_LOW |
1088 EBC0_CFG_EMPH_LOW |
1089 EBC0_CFG_CSTC_DRIVEN |
1090 EBC0_CFG_BPF_ONEDW |
1091 EBC0_CFG_EMS_8BIT |
1092 EBC0_CFG_PME_DISABLED |
1093 EBC0_CFG_PMT_ENCODE(0) );
1094
1095 /*-------------------------------------------------------------------------+
1096 | Initialize EBC Bank 0-4
1097 +-------------------------------------------------------------------------*/
1098 /* EBC Bank0 */
1099 mtebc(pb0ap, ebc0_cs0_bnap_value);
1100 mtebc(pb0cr, ebc0_cs0_bncr_value);
1101 /* EBC Bank1 */
1102 mtebc(pb1ap, ebc0_cs1_bnap_value);
1103 mtebc(pb1cr, ebc0_cs1_bncr_value);
1104 /* EBC Bank2 */
1105 mtebc(pb2ap, ebc0_cs2_bnap_value);
1106 mtebc(pb2cr, ebc0_cs2_bncr_value);
1107 /* EBC Bank3 */
1108 mtebc(pb3ap, ebc0_cs3_bnap_value);
1109 mtebc(pb3cr, ebc0_cs3_bncr_value);
1110 /* EBC Bank4 */
1111 mtebc(pb4ap, ebc0_cs4_bnap_value);
1112 mtebc(pb4cr, ebc0_cs4_bncr_value);
1113
1114 return;
1115 }
1116
1117
1118 /*----------------------------------------------------------------------------+
1119 | get_uart_configuration.
1120 +----------------------------------------------------------------------------*/
1121 uart_config_nb_t get_uart_configuration(void)
1122 {
1123 return (L4);
1124 }
1125
1126 /*----------------------------------------------------------------------------+
1127 | set_phy_configuration_through_fpga => to EPLD
1128 +----------------------------------------------------------------------------*/
1129 void set_phy_configuration_through_fpga(zmii_config_t config)
1130 {
1131
1132 unsigned long fpga_selection_reg;
1133
1134 fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
1135
1136 switch(config)
1137 {
1138 case ZMII_CONFIGURATION_IS_MII:
1139 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
1140 break;
1141 case ZMII_CONFIGURATION_IS_RMII:
1142 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
1143 break;
1144 case ZMII_CONFIGURATION_IS_SMII:
1145 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
1146 break;
1147 case ZMII_CONFIGURATION_UNKNOWN:
1148 default:
1149 break;
1150 }
1151 out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
1152
1153 }
1154
1155 /*----------------------------------------------------------------------------+
1156 | scp_selection_in_fpga.
1157 +----------------------------------------------------------------------------*/
1158 void scp_selection_in_fpga(void)
1159 {
1160 unsigned long fpga_selection_2_reg;
1161
1162 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1163 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
1164 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1165 }
1166
1167 /*----------------------------------------------------------------------------+
1168 | iic1_selection_in_fpga.
1169 +----------------------------------------------------------------------------*/
1170 void iic1_selection_in_fpga(void)
1171 {
1172 unsigned long fpga_selection_2_reg;
1173
1174 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1175 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
1176 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1177 }
1178
1179 /*----------------------------------------------------------------------------+
1180 | dma_a_b_selection_in_fpga.
1181 +----------------------------------------------------------------------------*/
1182 void dma_a_b_selection_in_fpga(void)
1183 {
1184 unsigned long fpga_selection_2_reg;
1185
1186 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
1187 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1188 }
1189
1190 /*----------------------------------------------------------------------------+
1191 | dma_a_b_unselect_in_fpga.
1192 +----------------------------------------------------------------------------*/
1193 void dma_a_b_unselect_in_fpga(void)
1194 {
1195 unsigned long fpga_selection_2_reg;
1196
1197 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
1198 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1199 }
1200
1201 /*----------------------------------------------------------------------------+
1202 | dma_c_d_selection_in_fpga.
1203 +----------------------------------------------------------------------------*/
1204 void dma_c_d_selection_in_fpga(void)
1205 {
1206 unsigned long fpga_selection_2_reg;
1207
1208 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
1209 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1210 }
1211
1212 /*----------------------------------------------------------------------------+
1213 | dma_c_d_unselect_in_fpga.
1214 +----------------------------------------------------------------------------*/
1215 void dma_c_d_unselect_in_fpga(void)
1216 {
1217 unsigned long fpga_selection_2_reg;
1218
1219 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
1220 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1221 }
1222
1223 /*----------------------------------------------------------------------------+
1224 | usb2_device_selection_in_fpga.
1225 +----------------------------------------------------------------------------*/
1226 void usb2_device_selection_in_fpga(void)
1227 {
1228 unsigned long fpga_selection_1_reg;
1229
1230 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
1231 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1232 }
1233
1234 /*----------------------------------------------------------------------------+
1235 | usb2_device_reset_through_fpga.
1236 +----------------------------------------------------------------------------*/
1237 void usb2_device_reset_through_fpga(void)
1238 {
1239 /* Perform soft Reset pulse */
1240 unsigned long fpga_reset_reg;
1241 int i;
1242
1243 fpga_reset_reg = in8(FPGA_RESET_REG);
1244 out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
1245 for (i=0; i<500; i++)
1246 udelay(1000);
1247 out8(FPGA_RESET_REG,fpga_reset_reg);
1248 }
1249
1250 /*----------------------------------------------------------------------------+
1251 | usb2_host_selection_in_fpga.
1252 +----------------------------------------------------------------------------*/
1253 void usb2_host_selection_in_fpga(void)
1254 {
1255 unsigned long fpga_selection_1_reg;
1256
1257 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
1258 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1259 }
1260
1261 /*----------------------------------------------------------------------------+
1262 | ndfc_selection_in_fpga.
1263 +----------------------------------------------------------------------------*/
1264 void ndfc_selection_in_fpga(void)
1265 {
1266 unsigned long fpga_selection_1_reg;
1267
1268 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
1269 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
1270 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
1271 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1272 }
1273
1274 /*----------------------------------------------------------------------------+
1275 | uart_selection_in_fpga.
1276 +----------------------------------------------------------------------------*/
1277 void uart_selection_in_fpga(uart_config_nb_t uart_config)
1278 {
1279 /* FPGA register */
1280 unsigned char fpga_selection_3_reg;
1281
1282 /* Read FPGA Reagister */
1283 fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
1284
1285 switch (uart_config)
1286 {
1287 case L1:
1288 /* ----------------------------------------------------------------------- */
1289 /* L1 configuration: UART0 = 8 pins */
1290 /* ----------------------------------------------------------------------- */
1291 /* Configure FPGA */
1292 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1293 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
1294 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1295
1296 break;
1297
1298 case L2:
1299 /* ----------------------------------------------------------------------- */
1300 /* L2 configuration: UART0 = 4 pins */
1301 /* UART1 = 4 pins */
1302 /* ----------------------------------------------------------------------- */
1303 /* Configure FPGA */
1304 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1305 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
1306 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1307
1308 break;
1309
1310 case L3:
1311 /* ----------------------------------------------------------------------- */
1312 /* L3 configuration: UART0 = 4 pins */
1313 /* UART1 = 2 pins */
1314 /* UART2 = 2 pins */
1315 /* ----------------------------------------------------------------------- */
1316 /* Configure FPGA */
1317 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1318 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
1319 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1320 break;
1321
1322 case L4:
1323 /* Configure FPGA */
1324 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1325 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
1326 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1327
1328 break;
1329
1330 default:
1331 /* Unsupported UART configuration number */
1332 for (;;)
1333 ;
1334 break;
1335
1336 }
1337 }
1338
1339
1340 /*----------------------------------------------------------------------------+
1341 | init_default_gpio
1342 +----------------------------------------------------------------------------*/
1343 void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX])
1344 {
1345 int i;
1346
1347 /* Init GPIO0 */
1348 for(i=0; i<GPIO_MAX; i++)
1349 {
1350 gpio_tab[GPIO0][i].add = GPIO0_BASE;
1351 gpio_tab[GPIO0][i].in_out = GPIO_DIS;
1352 gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
1353 }
1354
1355 /* Init GPIO1 */
1356 for(i=0; i<GPIO_MAX; i++)
1357 {
1358 gpio_tab[GPIO1][i].add = GPIO1_BASE;
1359 gpio_tab[GPIO1][i].in_out = GPIO_DIS;
1360 gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
1361 }
1362
1363 /* EBC_CS_N(5) - GPIO0_10 */
1364 gpio_tab[GPIO0][10].in_out = GPIO_OUT;
1365 gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1;
1366
1367 /* EBC_CS_N(4) - GPIO0_9 */
1368 gpio_tab[GPIO0][9].in_out = GPIO_OUT;
1369 gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1;
1370 }
1371
1372 /*----------------------------------------------------------------------------+
1373 | update_uart_ios
1374 +------------------------------------------------------------------------------
1375 |
1376 | Set UART Configuration in PowerPC440EP
1377 |
1378 | +---------------------------------------------------------------------+
1379 | | Configuartion | Connector | Nb of pins | Pins | Associated |
1380 | | Number | Port Name | available | naming | CORE |
1381 | +-----------------+---------------+------------+--------+-------------+
1382 | | L1 | Port_A | 8 | UART | UART core 0 |
1383 | +-----------------+---------------+------------+--------+-------------+
1384 | | L2 | Port_A | 4 | UART1 | UART core 0 |
1385 | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
1386 | +-----------------+---------------+------------+--------+-------------+
1387 | | L3 | Port_A | 4 | UART1 | UART core 0 |
1388 | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
1389 | | | Port_C | 2 | UART3 | UART core 2 |
1390 | +-----------------+---------------+------------+--------+-------------+
1391 | | | Port_A | 2 | UART1 | UART core 0 |
1392 | | L4 | Port_B | 2 | UART2 | UART core 1 |
1393 | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
1394 | | | Port_D | 2 | UART4 | UART core 3 |
1395 | +-----------------+---------------+------------+--------+-------------+
1396 |
1397 | Involved GPIOs
1398 |
1399 | +------------------------------------------------------------------------------+
1400 | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
1401 | +---------+------------------+-----+-----------------+-----+-------------+-----+
1402 | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
1403 | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
1404 | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
1405 | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
1406 | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
1407 | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
1408 | +------------------------------------------------------------------------------+
1409 |
1410 |
1411 +----------------------------------------------------------------------------*/
1412
1413 void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX])
1414 {
1415 switch (uart_config)
1416 {
1417 case L1:
1418 /* ----------------------------------------------------------------------- */
1419 /* L1 configuration: UART0 = 8 pins */
1420 /* ----------------------------------------------------------------------- */
1421 /* Update GPIO Configuration Table */
1422 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1423 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
1424
1425 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1426 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
1427
1428 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1429 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1430
1431 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1432 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1433
1434 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1435 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
1436
1437 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1438 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
1439
1440 break;
1441
1442 case L2:
1443 /* ----------------------------------------------------------------------- */
1444 /* L2 configuration: UART0 = 4 pins */
1445 /* UART1 = 4 pins */
1446 /* ----------------------------------------------------------------------- */
1447 /* Update GPIO Configuration Table */
1448 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1449 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
1450
1451 gpio_tab[GPIO1][3].in_out = GPIO_OUT;
1452 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
1453
1454 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1455 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1456
1457 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1458 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1459
1460 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1461 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1462
1463 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1464 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1465
1466 break;
1467
1468 case L3:
1469 /* ----------------------------------------------------------------------- */
1470 /* L3 configuration: UART0 = 4 pins */
1471 /* UART1 = 2 pins */
1472 /* UART2 = 2 pins */
1473 /* ----------------------------------------------------------------------- */
1474 /* Update GPIO Configuration Table */
1475 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1476 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1477
1478 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1479 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1480
1481 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1482 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1483
1484 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1485 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1486
1487 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1488 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1489
1490 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1491 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1492
1493 break;
1494
1495 case L4:
1496 /* ----------------------------------------------------------------------- */
1497 /* L4 configuration: UART0 = 2 pins */
1498 /* UART1 = 2 pins */
1499 /* UART2 = 2 pins */
1500 /* UART3 = 2 pins */
1501 /* ----------------------------------------------------------------------- */
1502 /* Update GPIO Configuration Table */
1503 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1504 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1505
1506 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1507 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1508
1509 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1510 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
1511
1512 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1513 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
1514
1515 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1516 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1517
1518 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1519 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1520
1521 break;
1522
1523 default:
1524 /* Unsupported UART configuration number */
1525 printf("ERROR - Unsupported UART configuration number.\n\n");
1526 for (;;)
1527 ;
1528 break;
1529
1530 }
1531
1532 /* Set input Selection Register on Alt_Receive for UART Input Core */
1533 out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
1534 out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
1535 out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
1536 }
1537
1538 /*----------------------------------------------------------------------------+
1539 | update_ndfc_ios(void).
1540 +----------------------------------------------------------------------------*/
1541 void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1542 {
1543 /* Update GPIO Configuration Table */
1544 gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
1545 gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
1546
1547 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
1548 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1549
1550 #if 0
1551 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
1552 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1553 #endif
1554 }
1555
1556 /*----------------------------------------------------------------------------+
1557 | update_zii_ios(void).
1558 +----------------------------------------------------------------------------*/
1559 void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1560 {
1561 /* Update GPIO Configuration Table */
1562 gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
1563 gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
1564
1565 gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
1566 gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
1567
1568 gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
1569 gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
1570
1571 gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
1572 gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
1573
1574 gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
1575 gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
1576
1577 gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
1578 gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
1579
1580 gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
1581 gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
1582
1583 gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
1584 gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
1585
1586 gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
1587 gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
1588
1589 gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
1590 gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
1591
1592 gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
1593 gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
1594
1595 gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
1596 gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
1597
1598 gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
1599 gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
1600
1601 gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
1602 gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
1603
1604 }
1605
1606 /*----------------------------------------------------------------------------+
1607 | update_uic_0_3_irq_ios().
1608 +----------------------------------------------------------------------------*/
1609 void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1610 {
1611 gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
1612 gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
1613
1614 gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
1615 gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
1616
1617 gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
1618 gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
1619
1620 gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
1621 gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
1622 }
1623
1624 /*----------------------------------------------------------------------------+
1625 | update_uic_4_9_irq_ios().
1626 +----------------------------------------------------------------------------*/
1627 void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1628 {
1629 gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
1630 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
1631
1632 gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
1633 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
1634
1635 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
1636 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
1637
1638 gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
1639 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
1640
1641 gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
1642 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
1643 }
1644
1645 /*----------------------------------------------------------------------------+
1646 | update_dma_a_b_ios().
1647 +----------------------------------------------------------------------------*/
1648 void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1649 {
1650 gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
1651 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
1652
1653 gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
1654 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
1655
1656 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
1657 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
1658
1659 gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
1660 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
1661
1662 gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
1663 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
1664 }
1665
1666 /*----------------------------------------------------------------------------+
1667 | update_dma_c_d_ios().
1668 +----------------------------------------------------------------------------*/
1669 void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1670 {
1671 gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
1672 gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
1673
1674 gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
1675 gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
1676
1677 gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
1678 gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
1679
1680 gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
1681 gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
1682
1683 gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
1684 gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
1685
1686 gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
1687 gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
1688
1689 }
1690
1691 /*----------------------------------------------------------------------------+
1692 | update_ebc_master_ios().
1693 +----------------------------------------------------------------------------*/
1694 void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1695 {
1696 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
1697 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
1698
1699 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
1700 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1701
1702 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
1703 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
1704
1705 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
1706 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
1707 }
1708
1709 /*----------------------------------------------------------------------------+
1710 | update_usb2_device_ios().
1711 +----------------------------------------------------------------------------*/
1712 void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1713 {
1714 gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
1715 gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
1716
1717 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
1718 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
1719
1720 gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
1721 gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
1722
1723 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
1724 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
1725
1726 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
1727 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
1728
1729 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
1730 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
1731
1732 gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
1733 gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
1734
1735 gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
1736 gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
1737
1738 }
1739
1740 /*----------------------------------------------------------------------------+
1741 | update_pci_patch_ios().
1742 +----------------------------------------------------------------------------*/
1743 void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1744 {
1745 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
1746 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1747 }
1748
1749 /*----------------------------------------------------------------------------+
1750 | set_chip_gpio_configuration(unsigned char gpio_core,
1751 | gpio_param_s (*gpio_tab)[GPIO_MAX])
1752 | Put the core impacted by clock modification and sharing in reset.
1753 | Config the select registers to resolve the sharing depending of the config.
1754 | Configure the GPIO registers.
1755 |
1756 +----------------------------------------------------------------------------*/
1757 void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX])
1758 {
1759 unsigned char i=0, j=0, reg_offset = 0;
1760 unsigned long gpio_reg, gpio_core_add;
1761
1762 /* GPIO config of the GPIOs 0 to 31 */
1763 for (i=0; i<GPIO_MAX; i++, j++)
1764 {
1765 if (i == GPIO_MAX/2)
1766 {
1767 reg_offset = 4;
1768 j = i-16;
1769 }
1770
1771 gpio_core_add = gpio_tab[gpio_core][i].add;
1772
1773 if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
1774 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1775 {
1776 switch (gpio_tab[gpio_core][i].alt_nb)
1777 {
1778 case GPIO_SEL:
1779 break;
1780
1781 case GPIO_ALT1:
1782 gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1783 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1784 out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
1785 break;
1786
1787 case GPIO_ALT2:
1788 gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1789 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1790 out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
1791 break;
1792
1793 case GPIO_ALT3:
1794 gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1795 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1796 out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
1797 break;
1798 }
1799 }
1800 if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
1801 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1802 {
1803
1804 switch (gpio_tab[gpio_core][i].alt_nb)
1805 {
1806 case GPIO_SEL:
1807 break;
1808 case GPIO_ALT1:
1809 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1810 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1811 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1812 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1813 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1814 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1815 break;
1816 case GPIO_ALT2:
1817 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1818 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1819 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1820 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1821 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1822 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1823 break;
1824 case GPIO_ALT3:
1825 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1826 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1827 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1828 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1829 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1830 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1831 break;
1832 }
1833 }
1834 }
1835 }
1836
1837 /*----------------------------------------------------------------------------+
1838 | force_bup_core_selection.
1839 +----------------------------------------------------------------------------*/
1840 void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
1841 {
1842 /* Pointer invalid */
1843 if (core_select_P == NULL)
1844 {
1845 printf("Configuration invalid pointer 1\n");
1846 for (;;)
1847 ;
1848 }
1849
1850 /* L4 Selection */
1851 *(core_select_P+UART_CORE0) = CORE_SELECTED;
1852 *(core_select_P+UART_CORE1) = CORE_SELECTED;
1853 *(core_select_P+UART_CORE2) = CORE_SELECTED;
1854 *(core_select_P+UART_CORE3) = CORE_SELECTED;
1855
1856 /* RMII Selection */
1857 *(core_select_P+RMII_SEL) = CORE_SELECTED;
1858
1859 /* External Interrupt 0-9 selection */
1860 *(core_select_P+UIC_0_3) = CORE_SELECTED;
1861 *(core_select_P+UIC_4_9) = CORE_SELECTED;
1862
1863 *(core_select_P+SCP_CORE) = CORE_SELECTED;
1864 *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
1865 *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
1866 *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
1867
1868 if (is_nand_selected()) {
1869 *(core_select_P+NAND_FLASH) = CORE_SELECTED;
1870 }
1871
1872 *config_val_P = CONFIG_IS_VALID;
1873
1874 }
1875
1876 /*----------------------------------------------------------------------------+
1877 | configure_ppc440ep_pins.
1878 +----------------------------------------------------------------------------*/
1879 void configure_ppc440ep_pins(void)
1880 {
1881 uart_config_nb_t uart_configuration;
1882 config_validity_t config_val = CONFIG_IS_INVALID;
1883
1884 /* Create Core Selection Table */
1885 core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
1886 {
1887 CORE_NOT_SELECTED, /* IIC_CORE, */
1888 CORE_NOT_SELECTED, /* SPC_CORE, */
1889 CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
1890 CORE_NOT_SELECTED, /* UIC_4_9, */
1891 CORE_NOT_SELECTED, /* USB2_HOST, */
1892 CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
1893 CORE_NOT_SELECTED, /* USB2_DEVICE, */
1894 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
1895 CORE_NOT_SELECTED, /* USB1_DEVICE, */
1896 CORE_NOT_SELECTED, /* EBC_MASTER, */
1897 CORE_NOT_SELECTED, /* NAND_FLASH, */
1898 CORE_NOT_SELECTED, /* UART_CORE0, */
1899 CORE_NOT_SELECTED, /* UART_CORE1, */
1900 CORE_NOT_SELECTED, /* UART_CORE2, */
1901 CORE_NOT_SELECTED, /* UART_CORE3, */
1902 CORE_NOT_SELECTED, /* MII_SEL, */
1903 CORE_NOT_SELECTED, /* RMII_SEL, */
1904 CORE_NOT_SELECTED, /* SMII_SEL, */
1905 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
1906 CORE_NOT_SELECTED, /* UIC_0_3 */
1907 CORE_NOT_SELECTED, /* USB1_HOST */
1908 CORE_NOT_SELECTED /* PCI_PATCH */
1909 };
1910
1911 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
1912
1913 /* Table Default Initialisation + FPGA Access */
1914 init_default_gpio(gpio_tab);
1915 set_chip_gpio_configuration(GPIO0, gpio_tab);
1916 set_chip_gpio_configuration(GPIO1, gpio_tab);
1917
1918 /* Update Table */
1919 force_bup_core_selection(ppc440ep_core_selection, &config_val);
1920 #if 0 /* test-only */
1921 /* If we are running PIBS 1, force known configuration */
1922 update_core_selection_table(ppc440ep_core_selection, &config_val);
1923 #endif
1924
1925 /*----------------------------------------------------------------------------+
1926 | SDR + ios table update + fpga initialization
1927 +----------------------------------------------------------------------------*/
1928 unsigned long sdr0_pfc1 = 0;
1929 unsigned long sdr0_usb0 = 0;
1930 unsigned long sdr0_mfr = 0;
1931
1932 /* PCI Always selected */
1933
1934 /* I2C Selection */
1935 if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
1936 {
1937 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
1938 iic1_selection_in_fpga();
1939 }
1940
1941 /* SCP Selection */
1942 if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
1943 {
1944 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
1945 scp_selection_in_fpga();
1946 }
1947
1948 /* UIC 0:3 Selection */
1949 if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
1950 {
1951 update_uic_0_3_irq_ios(gpio_tab);
1952 dma_a_b_unselect_in_fpga();
1953 }
1954
1955 /* UIC 4:9 Selection */
1956 if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
1957 {
1958 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
1959 update_uic_4_9_irq_ios(gpio_tab);
1960 }
1961
1962 /* DMA AB Selection */
1963 if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
1964 {
1965 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
1966 update_dma_a_b_ios(gpio_tab);
1967 dma_a_b_selection_in_fpga();
1968 }
1969
1970 /* DMA CD Selection */
1971 if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
1972 {
1973 update_dma_c_d_ios(gpio_tab);
1974 dma_c_d_selection_in_fpga();
1975 }
1976
1977 /* EBC Master Selection */
1978 if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
1979 {
1980 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
1981 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1982 update_ebc_master_ios(gpio_tab);
1983 }
1984
1985 /* PCI Patch Enable */
1986 if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
1987 {
1988 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1989 update_pci_patch_ios(gpio_tab);
1990 }
1991
1992 /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
1993 if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
1994 {
1995 /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
1996 printf("Invalid configuration => USB2 Host selected\n");
1997 for (;;)
1998 ;
1999 /*usb2_host_selection_in_fpga(); */
2000 }
2001
2002 /* USB2.0 Device Selection */
2003 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
2004 {
2005 update_usb2_device_ios(gpio_tab);
2006 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
2007 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
2008
2009 mfsdr(sdr_usb0, sdr0_usb0);
2010 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
2011 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
2012 mtsdr(sdr_usb0, sdr0_usb0);
2013
2014 usb2_device_selection_in_fpga();
2015 }
2016
2017 /* USB1.1 Device Selection */
2018 if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
2019 {
2020 mfsdr(sdr_usb0, sdr0_usb0);
2021 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
2022 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
2023 mtsdr(sdr_usb0, sdr0_usb0);
2024 }
2025
2026 /* USB1.1 Host Selection */
2027 if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
2028 {
2029 mfsdr(sdr_usb0, sdr0_usb0);
2030 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
2031 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
2032 mtsdr(sdr_usb0, sdr0_usb0);
2033 }
2034
2035 /* NAND Flash Selection */
2036 if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
2037 {
2038 update_ndfc_ios(gpio_tab);
2039
2040 #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
2041 mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
2042 SDR0_CUST0_NDFC_ENABLE |
2043 SDR0_CUST0_NDFC_BW_8_BIT |
2044 SDR0_CUST0_NDFC_ARE_MASK |
2045 SDR0_CUST0_CHIPSELGAT_EN1 |
2046 SDR0_CUST0_CHIPSELGAT_EN2);
2047 #else
2048 mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
2049 SDR0_CUST0_NDFC_ENABLE |
2050 SDR0_CUST0_NDFC_BW_8_BIT |
2051 SDR0_CUST0_NDFC_ARE_MASK |
2052 SDR0_CUST0_CHIPSELGAT_EN0 |
2053 SDR0_CUST0_CHIPSELGAT_EN2);
2054 #endif
2055
2056 ndfc_selection_in_fpga();
2057 }
2058 else
2059 {
2060 /* Set Mux on EMAC */
2061 mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL);
2062 }
2063
2064 /* MII Selection */
2065 if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
2066 {
2067 update_zii_ios(gpio_tab);
2068 mfsdr(sdr_mfr, sdr0_mfr);
2069 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
2070 mtsdr(sdr_mfr, sdr0_mfr);
2071
2072 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
2073 }
2074
2075 /* RMII Selection */
2076 if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
2077 {
2078 update_zii_ios(gpio_tab);
2079 mfsdr(sdr_mfr, sdr0_mfr);
2080 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
2081 mtsdr(sdr_mfr, sdr0_mfr);
2082
2083 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
2084 }
2085
2086 /* SMII Selection */
2087 if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
2088 {
2089 update_zii_ios(gpio_tab);
2090 mfsdr(sdr_mfr, sdr0_mfr);
2091 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
2092 mtsdr(sdr_mfr, sdr0_mfr);
2093
2094 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
2095 }
2096
2097 /* UART Selection */
2098 uart_configuration = get_uart_configuration();
2099 switch (uart_configuration)
2100 {
2101 case L1: /* L1 Selection */
2102 /* UART0 8 pins Only */
2103 /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
2104 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
2105 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
2106 break;
2107 case L2: /* L2 Selection */
2108 /* UART0 and UART1 4 pins */
2109 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2110 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2111 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2112 break;
2113 case L3: /* L3 Selection */
2114 /* UART0 4 pins, UART1 and UART2 2 pins */
2115 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2116 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2117 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2118 break;
2119 case L4: /* L4 Selection */
2120 /* UART0, UART1, UART2 and UART3 2 pins */
2121 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
2122 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2123 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2124 break;
2125 }
2126 update_uart_ios(uart_configuration, gpio_tab);
2127
2128 /* UART Selection in all cases */
2129 uart_selection_in_fpga(uart_configuration);
2130
2131 /* Packet Reject Function Available */
2132 if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
2133 {
2134 /* Set UPR Bit in SDR0_PFC1 Register */
2135 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
2136 }
2137
2138 /* Packet Reject Function Enable */
2139 if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
2140 {
2141 mfsdr(sdr_mfr, sdr0_mfr);
2142 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
2143 mtsdr(sdr_mfr, sdr0_mfr);
2144 }
2145
2146 /* Perform effective access to hardware */
2147 mtsdr(sdr_pfc1, sdr0_pfc1);
2148 set_chip_gpio_configuration(GPIO0, gpio_tab);
2149 set_chip_gpio_configuration(GPIO1, gpio_tab);
2150
2151 /* USB2.0 Device Reset must be done after GPIO setting */
2152 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
2153 usb2_device_reset_through_fpga();
2154
2155 }
"Das U-Boot" Source Tree