board/amcc/bamboo/init.S

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <asm-offsets.h>
  11 #include <ppc_asm.tmpl>
  12 #include <config.h>
  13 #include <asm/mmu.h>
  14
  15 /**************************************************************************
  16  * TLB TABLE
  17  *
  18  * This table is used by the cpu boot code to setup the initial tlb
  19  * entries. Rather than make broad assumptions in the cpu source tree,
  20  * this table lets each board set things up however they like.
  21  *
  22  *  Pointer to the table is returned in r1
  23  *
  24  *************************************************************************/
  25         .section .bootpg,"ax"
  26         .globl tlbtab
  27
  28 tlbtab:
  29         tlbtab_start
  30
  31         /*
  32          * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
  33          * speed up boot process. It is patched after relocation to enable SA_I
  34          */
  35 #ifndef CONFIG_NAND_SPL
  36         tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G)
  37 #else
  38         tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_RWX | SA_G)
  39         tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
  40 #endif
  41
  42         /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
  43         tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
  44
  45         /* PCI base & peripherals */
  46         tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG)
  47
  48         tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I)
  49         tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_RWX | SA_W|SA_I)
  50
  51         /* PCI */
  52         tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG)
  53         tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG)
  54         tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG)
  55         tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG)
  56
  57         /* USB 2.0 Device */
  58         tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG)
  59
  60         tlbtab_end
  61
  62 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  63         /*
  64          * For NAND booting the first TLB has to be reconfigured to full size
  65          * and with caching disabled after running from RAM!
  66          */
  67 #define TLB00   TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
  68 #define TLB01   TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0)
  69 #define TLB02   TLB2(AC_RWX | SA_IG)
  70
  71         .globl  reconfig_tlb0
  72 reconfig_tlb0:
  73         sync
  74         isync
  75         addi    r4,r0,0x0000            /* TLB entry #0 */
  76         lis     r5,TLB00@h
  77         ori     r5,r5,TLB00@l
  78         tlbwe   r5,r4,0x0000            /* Save it out */
  79         lis     r5,TLB01@h
  80         ori     r5,r5,TLB01@l
  81         tlbwe   r5,r4,0x0001            /* Save it out */
  82         lis     r5,TLB02@h
  83         ori     r5,r5,TLB02@l
  84         tlbwe   r5,r4,0x0002            /* Save it out */
  85         sync
  86         isync
  87         blr
  88 #endif