board/amcc/bluestone/bluestone.c

   1 /*
   2  * Bluestone board support
   3  *
   4  * Copyright (c) 2010, Applied Micro Circuits Corporation
   5  * Author: Tirumala R Marri <tmarri@apm.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/apm821xx.h>
  25 #include <libfdt.h>
  26 #include <fdt_support.h>
  27 #include <i2c.h>
  28 #include <asm/processor.h>
  29 #include <asm/io.h>
  30 #include <asm/mmu.h>
  31 #include <asm/ppc4xx-gpio.h>
  32
  33 int board_early_init_f(void)
  34 {
  35         /*
  36          * Setup the interrupt controller polarities, triggers, etc.
  37          */
  38         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  39         mtdcr(UIC0ER, 0x00000000);      /* disable all */
  40         mtdcr(UIC0CR, 0x00000005);      /* ATI & UIC1 crit are critical */
  41         mtdcr(UIC0PR, 0xffffffff);      /* per ref-board manual */
  42         mtdcr(UIC0TR, 0x00000000);      /* per ref-board manual */
  43         mtdcr(UIC0VR, 0x00000000);      /* int31 highest, base=0x000 */
  44         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  45
  46         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  47         mtdcr(UIC1ER, 0x00000000);      /* disable all */
  48         mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
  49         mtdcr(UIC1PR, 0xffffffff);      /* per ref-board manual */
  50         mtdcr(UIC1TR, 0x00000000);      /* per ref-board manual */
  51         mtdcr(UIC1VR, 0x00000000);      /* int31 highest, base=0x000 */
  52         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  53
  54         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
  55         mtdcr(UIC2ER, 0x00000000);      /* disable all */
  56         mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
  57         mtdcr(UIC2PR, 0xffffffff);      /* per ref-board manual */
  58         mtdcr(UIC2TR, 0x00000000);      /* per ref-board manual */
  59         mtdcr(UIC2VR, 0x00000000);      /* int31 highest, base=0x000 */
  60         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
  61
  62         mtdcr(UIC3SR, 0xffffffff);      /* clear all */
  63         mtdcr(UIC3ER, 0x00000000);      /* disable all */
  64         mtdcr(UIC3CR, 0x00000000);      /* all non-critical */
  65         mtdcr(UIC3PR, 0xffffffff);      /* per ref-board manual */
  66         mtdcr(UIC3TR, 0x00000000);      /* per ref-board manual */
  67         mtdcr(UIC3VR, 0x00000000);      /* int31 highest, base=0x000 */
  68         mtdcr(UIC3SR, 0xffffffff);      /* clear all */
  69
  70         /*
  71          * Configure PFC (Pin Function Control) registers
  72          * UART0: 2 pins
  73          */
  74         mtsdr(SDR0_PFC1, 0x0000000);
  75
  76         return 0;
  77 }
  78
  79 int checkboard(void)
  80 {
  81         char buf[64];
  82         int i = getenv_f("serial#", buf, sizeof(buf));
  83
  84         puts("Board: Bluestone Evaluation Board");
  85
  86         if (i > 0) {
  87                 puts(", serial# ");
  88                 puts(buf);
  89         }
  90         putc('\n');
  91
  92         return 0;
  93 }
  94
  95 int misc_init_r(void)
  96 {
  97         u32 sdr0_srst1 = 0;
  98
  99         /* Setup PLB4-AHB bridge based on the system address map */
 100         mtdcr(AHB_TOP, 0x8000004B);
 101         mtdcr(AHB_BOT, 0x8000004B);
 102
 103         /*
 104          * The AHB Bridge core is held in reset after power-on or reset
 105          * so enable it now
 106          */
 107         mfsdr(SDR0_SRST1, sdr0_srst1);
 108         sdr0_srst1 &= ~SDR0_SRST1_AHB;
 109         mtsdr(SDR0_SRST1, sdr0_srst1);
 110
 111         return 0;
 112 }