board/amcc/canyonlands/canyonlands.c

   1 /*
   2  * (C) Copyright 2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #include <common.h>
  22 #include <ppc440.h>
  23 #include <libfdt.h>
  24 #include <fdt_support.h>
  25 #include <asm/processor.h>
  26 #include <asm/io.h>
  27 #include <asm/mmu.h>
  28 #include <asm/4xx_pcie.h>
  29 #include <asm/gpio.h>
  30
  31 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #define CFG_BCSR3_PCIE          0x10
  36
  37 #define BOARD_CANYONLANDS_PCIE  1
  38 #define BOARD_CANYONLANDS_SATA  2
  39 #define BOARD_GLACIER           3
  40
  41 int board_early_init_f(void)
  42 {
  43         u32 sdr0_cust0;
  44         u32 pvr = get_pvr();
  45
  46         /*
  47          * Setup the interrupt controller polarities, triggers, etc.
  48          */
  49         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  50         mtdcr(uic0er, 0x00000000);      /* disable all */
  51         mtdcr(uic0cr, 0x00000005);      /* ATI & UIC1 crit are critical */
  52         mtdcr(uic0pr, 0xffffffff);      /* per ref-board manual */
  53         mtdcr(uic0tr, 0x00000000);      /* per ref-board manual */
  54         mtdcr(uic0vr, 0x00000000);      /* int31 highest, base=0x000 */
  55         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  56
  57         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  58         mtdcr(uic1er, 0x00000000);      /* disable all */
  59         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
  60         mtdcr(uic1pr, 0xffffffff);      /* per ref-board manual */
  61         mtdcr(uic1tr, 0x00000000);      /* per ref-board manual */
  62         mtdcr(uic1vr, 0x00000000);      /* int31 highest, base=0x000 */
  63         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  64
  65         mtdcr(uic2sr, 0xffffffff);      /* clear all */
  66         mtdcr(uic2er, 0x00000000);      /* disable all */
  67         mtdcr(uic2cr, 0x00000000);      /* all non-critical */
  68         mtdcr(uic2pr, 0xffffffff);      /* per ref-board manual */
  69         mtdcr(uic2tr, 0x00000000);      /* per ref-board manual */
  70         mtdcr(uic2vr, 0x00000000);      /* int31 highest, base=0x000 */
  71         mtdcr(uic2sr, 0xffffffff);      /* clear all */
  72
  73         mtdcr(uic3sr, 0xffffffff);      /* clear all */
  74         mtdcr(uic3er, 0x00000000);      /* disable all */
  75         mtdcr(uic3cr, 0x00000000);      /* all non-critical */
  76         mtdcr(uic3pr, 0xffffffff);      /* per ref-board manual */
  77         mtdcr(uic3tr, 0x00000000);      /* per ref-board manual */
  78         mtdcr(uic3vr, 0x00000000);      /* int31 highest, base=0x000 */
  79         mtdcr(uic3sr, 0xffffffff);      /* clear all */
  80
  81         /* SDR Setting - enable NDFC */
  82         mfsdr(SDR0_CUST0, sdr0_cust0);
  83         sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL    |
  84                 SDR0_CUST0_NDFC_ENABLE          |
  85                 SDR0_CUST0_NDFC_BW_8_BIT        |
  86                 SDR0_CUST0_NDFC_ARE_MASK        |
  87                 SDR0_CUST0_NDFC_BAC_ENCODE(3)   |
  88                 (0x80000000 >> (28 + CFG_NAND_CS));
  89         mtsdr(SDR0_CUST0, sdr0_cust0);
  90
  91         /*
  92          * Configure PFC (Pin Function Control) registers
  93          * UART0: 4 pins
  94          */
  95         mtsdr(SDR0_PFC1, 0x00040000);
  96
  97         /* Enable PCI host functionality in SDR0_PCI0 */
  98         mtsdr(SDR0_PCI0, 0xe0000000);
  99
 100         /* Enable ethernet and take out of reset */
 101         out_8((void *)CFG_BCSR_BASE + 6, 0);
 102
 103         /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
 104         out_8((void *)CFG_BCSR_BASE + 5, 0);
 105
 106         /* Enable USB host & USB-OTG */
 107         out_8((void *)CFG_BCSR_BASE + 7, 0);
 108
 109         mtsdr(SDR0_SRST1, 0);   /* Pull AHB out of reset default=1 */
 110
 111         /* Setup PLB4-AHB bridge based on the system address map */
 112         mtdcr(AHB_TOP, 0x8000004B);
 113         mtdcr(AHB_BOT, 0x8000004B);
 114
 115         if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {
 116                 /*
 117                  * Configure USB-STP pins as alternate and not GPIO
 118                  * It seems to be neccessary to configure the STP pins as GPIO
 119                  * input at powerup (perhaps while USB reset is asserted). So
 120                  * we configure those pins to their "real" function now.
 121                  */
 122                 gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
 123                 gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
 124         }
 125
 126         return 0;
 127 }
 128
 129 static void canyonlands_sata_init(int board_type)
 130 {
 131         u32 reg;
 132
 133         if (board_type == BOARD_CANYONLANDS_SATA) {
 134                 /* Put SATA in reset */
 135                 SDR_WRITE(SDR0_SRST1, 0x00020001);
 136
 137                 /* Set the phy for SATA, not PCI-E port 0 */
 138                 reg = SDR_READ(PESDR0_PHY_CTL_RST);
 139                 SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
 140                 reg = SDR_READ(PESDR0_L0CLK);
 141                 SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
 142                 SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
 143                 SDR_WRITE(PESDR0_L0DRV, 0x00000104);
 144
 145                 /* Bring SATA out of reset */
 146                 SDR_WRITE(SDR0_SRST1, 0x00000000);
 147         }
 148 }
 149
 150 int checkboard(void)
 151 {
 152         char *s = getenv("serial#");
 153         u32 pvr = get_pvr();
 154
 155         if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA)) {
 156                 printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
 157                 gd->board_type = BOARD_GLACIER;
 158         } else {
 159                 printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
 160                 if (in_8((void *)(CFG_BCSR_BASE + 3)) & CFG_BCSR3_PCIE)
 161                         gd->board_type = BOARD_CANYONLANDS_PCIE;
 162                 else
 163                         gd->board_type = BOARD_CANYONLANDS_SATA;
 164         }
 165
 166         switch (gd->board_type) {
 167         case BOARD_CANYONLANDS_PCIE:
 168         case BOARD_GLACIER:
 169                 puts(", 2*PCIe");
 170                 break;
 171
 172         case BOARD_CANYONLANDS_SATA:
 173                 puts(", 1*PCIe/1*SATA");
 174                 break;
 175         }
 176
 177         printf(", Rev. %X", in_8((void *)(CFG_BCSR_BASE + 0)));
 178
 179         if (s != NULL) {
 180                 puts(", serial# ");
 181                 puts(s);
 182         }
 183         putc('\n');
 184
 185         canyonlands_sata_init(gd->board_type);
 186
 187         return (0);
 188 }
 189
 190 /*
 191  * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
 192  * board specific values.
 193  */
 194 u32 ddr_wrdtr(u32 default_val) {
 195         return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
 196 }
 197
 198 u32 ddr_clktr(u32 default_val) {
 199         return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
 200 }
 201
 202 #if defined(CONFIG_NAND_U_BOOT)
 203 /*
 204  * NAND booting U-Boot version uses a fixed initialization, since the whole
 205  * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
 206  * code.
 207  */
 208 long int initdram(int board_type)
 209 {
 210         return CFG_MBYTES_SDRAM << 20;
 211 }
 212 #endif
 213
 214 /*
 215  *  pci_target_init
 216  *
 217  *      The bootstrap configuration provides default settings for the pci
 218  *      inbound map (PIM). But the bootstrap config choices are limited and
 219  *      may not be sufficient for a given board.
 220  */
 221 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 222 void pci_target_init(struct pci_controller * hose )
 223 {
 224         /*
 225          * Disable everything
 226          */
 227         out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
 228         out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
 229         out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
 230         out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
 231
 232         /*
 233          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
 234          * strapping options to not support sizes such as 128/256 MB.
 235          */
 236         out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE);
 237         out_le32((void *)PCIX0_PIM0LAH, 0);
 238         out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
 239         out_le32((void *)PCIX0_BAR0, 0);
 240
 241         /*
 242          * Program the board's subsystem id/vendor id
 243          */
 244         out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
 245         out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
 246
 247         out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
 248 }
 249 #endif  /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 250
 251 #if defined(CONFIG_PCI)
 252 /*
 253  * is_pci_host
 254  *
 255  * This routine is called to determine if a pci scan should be
 256  * performed. With various hardware environments (especially cPCI and
 257  * PPMC) it's insufficient to depend on the state of the arbiter enable
 258  * bit in the strap register, or generic host/adapter assumptions.
 259  *
 260  * Rather than hard-code a bad assumption in the general 440 code, the
 261  * 440 pci code requires the board to decide at runtime.
 262  *
 263  * Return 0 for adapter mode, non-zero for host (monarch) mode.
 264  */
 265 int is_pci_host(struct pci_controller *hose)
 266 {
 267         /* Board is always configured as host. */
 268         return (1);
 269 }
 270
 271 static struct pci_controller pcie_hose[2] = {{0},{0}};
 272
 273 void pcie_setup_hoses(int busno)
 274 {
 275         struct pci_controller *hose;
 276         int i, bus;
 277         int ret = 0;
 278         char *env;
 279         unsigned int delay;
 280         int start;
 281
 282         /*
 283          * assume we're called after the PCIX hose is initialized, which takes
 284          * bus ID 0 and therefore start numbering PCIe's from 1.
 285          */
 286         bus = busno;
 287
 288         /*
 289          * Canyonlands with SATA enabled has only one PCIe slot
 290          * (2nd one).
 291          */
 292         if (gd->board_type == BOARD_CANYONLANDS_SATA)
 293                 start = 1;
 294         else
 295                 start = 0;
 296
 297         for (i = start; i <= 1; i++) {
 298
 299                 if (is_end_point(i))
 300                         ret = ppc4xx_init_pcie_endport(i);
 301                 else
 302                         ret = ppc4xx_init_pcie_rootport(i);
 303                 if (ret) {
 304                         printf("PCIE%d: initialization as %s failed\n", i,
 305                                is_end_point(i) ? "endpoint" : "root-complex");
 306                         continue;
 307                 }
 308
 309                 hose = &pcie_hose[i];
 310                 hose->first_busno = bus;
 311                 hose->last_busno = bus;
 312                 hose->current_busno = bus;
 313
 314                 /* setup mem resource */
 315                 pci_set_region(hose->regions + 0,
 316                                CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
 317                                CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
 318                                CFG_PCIE_MEMSIZE,
 319                                PCI_REGION_MEM);
 320                 hose->region_count = 1;
 321                 pci_register_hose(hose);
 322
 323                 if (is_end_point(i)) {
 324                         ppc4xx_setup_pcie_endpoint(hose, i);
 325                         /*
 326                          * Reson for no scanning is endpoint can not generate
 327                          * upstream configuration accesses.
 328                          */
 329                 } else {
 330                         ppc4xx_setup_pcie_rootpoint(hose, i);
 331                         env = getenv ("pciscandelay");
 332                         if (env != NULL) {
 333                                 delay = simple_strtoul(env, NULL, 10);
 334                                 if (delay > 5)
 335                                         printf("Warning, expect noticable delay before "
 336                                                "PCIe scan due to 'pciscandelay' value!\n");
 337                                 mdelay(delay * 1000);
 338                         }
 339
 340                         /*
 341                          * Config access can only go down stream
 342                          */
 343                         hose->last_busno = pci_hose_scan(hose);
 344                         bus = hose->last_busno + 1;
 345                 }
 346         }
 347 }
 348 #endif /* CONFIG_PCI */
 349
 350 int board_early_init_r (void)
 351 {
 352         /*
 353          * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
 354          * boot EBC mapping only supports a maximum of 16MBytes
 355          * (4.ff00.0000 - 4.ffff.ffff).
 356          * To solve this problem, the FLASH has to get remapped to another
 357          * EBC address which accepts bigger regions:
 358          *
 359          * 0xfc00.0000 -> 4.cc00.0000
 360          */
 361
 362         /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
 363 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 364         mtebc(pb3cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
 365 #else
 366         mtebc(pb0cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
 367 #endif
 368
 369         /* Remove TLB entry of boot EBC mapping */
 370         remove_tlb(CFG_BOOT_BASE_ADDR, 16 << 20);
 371
 372         /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
 373         program_tlb(CFG_FLASH_BASE_PHYS, CFG_FLASH_BASE, CFG_FLASH_SIZE,
 374                     TLB_WORD2_I_ENABLE);
 375
 376         /*
 377          * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
 378          * 0xfc00.0000 is possible
 379          */
 380
 381         /*
 382          * Clear potential errors resulting from auto-calibration.
 383          * If not done, then we could get an interrupt later on when
 384          * exceptions are enabled.
 385          */
 386         set_mcsr(get_mcsr());
 387
 388         return 0;
 389 }
 390
 391 int misc_init_r(void)
 392 {
 393         u32 sdr0_srst1 = 0;
 394         u32 eth_cfg;
 395         u32 pvr = get_pvr();
 396
 397         /*
 398          * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
 399          * This is board specific, so let's do it here.
 400          */
 401         mfsdr(SDR0_ETH_CFG, eth_cfg);
 402         /* disable SGMII mode */
 403         eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
 404                      SDR0_ETH_CFG_SGMII1_ENABLE |
 405                      SDR0_ETH_CFG_SGMII0_ENABLE);
 406         /* Set the for 2 RGMII mode */
 407         /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
 408         eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
 409         if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA))
 410                 eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
 411         else
 412                 eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
 413         mtsdr(SDR0_ETH_CFG, eth_cfg);
 414
 415         /*
 416          * The AHB Bridge core is held in reset after power-on or reset
 417          * so enable it now
 418          */
 419         mfsdr(SDR0_SRST1, sdr0_srst1);
 420         sdr0_srst1 &= ~SDR0_SRST1_AHB;
 421         mtsdr(SDR0_SRST1, sdr0_srst1);
 422
 423         return 0;
 424 }
 425
 426 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 427 void ft_board_setup(void *blob, bd_t *bd)
 428 {
 429         u32 val[4];
 430         int rc;
 431
 432         ft_cpu_setup(blob, bd);
 433
 434         /* Fixup NOR mapping */
 435         val[0] = 0;                             /* chip select number */
 436         val[1] = 0;                             /* always 0 */
 437         val[2] = CFG_FLASH_BASE_PHYS_L;         /* we fixed up this address */
 438         val[3] = gd->bd->bi_flashsize;
 439         rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
 440                                   val, sizeof(val), 1);
 441         if (rc) {
 442                 printf("Unable to update property NOR mapping, err=%s\n",
 443                        fdt_strerror(rc));
 444         }
 445
 446         if (gd->board_type == BOARD_CANYONLANDS_SATA) {
 447                 /*
 448                  * When SATA is selected we need to disable the first PCIe
 449                  * node in the device tree, so that Linux doesn't initialize
 450                  * it.
 451                  */
 452                 rc = fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
 453                                           "disabled", sizeof("disabled"), 1);
 454                 if (rc) {
 455                         printf("Unable to update property status in PCIe node, err=%s\n",
 456                                fdt_strerror(rc));
 457                 }
 458         }
 459
 460         if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
 461                 /*
 462                  * When PCIe is selected we need to disable the SATA
 463                  * node in the device tree, so that Linux doesn't initialize
 464                  * it.
 465                  */
 466                 rc = fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
 467                                           "disabled", sizeof("disabled"), 1);
 468                 if (rc) {
 469                         printf("Unable to update property status in PCIe node, err=%s\n",
 470                                fdt_strerror(rc));
 471                 }
 472         }
 473 }
 474 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */