board/amcc/canyonlands/canyonlands.c

   1 /*
   2  * (C) Copyright 2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #include <common.h>
  22 #include <asm/ppc440.h>
  23 #include <libfdt.h>
  24 #include <fdt_support.h>
  25 #include <i2c.h>
  26 #include <asm/processor.h>
  27 #include <asm/io.h>
  28 #include <asm/mmu.h>
  29 #include <asm/4xx_pcie.h>
  30 #include <asm/ppc4xx-gpio.h>
  31 #include <asm/errno.h>
  32
  33 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 struct board_bcsr {
  38         u8      board_id;
  39         u8      cpld_rev;
  40         u8      led_user;
  41         u8      board_status;
  42         u8      reset_ctrl;
  43         u8      flash_ctrl;
  44         u8      eth_ctrl;
  45         u8      usb_ctrl;
  46         u8      irq_ctrl;
  47 };
  48
  49 #define BOARD_CANYONLANDS_PCIE  1
  50 #define BOARD_CANYONLANDS_SATA  2
  51 #define BOARD_GLACIER           3
  52 #define BOARD_ARCHES            4
  53
  54 /*
  55  * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
  56  * board specific values.
  57  */
  58 #if defined(CONFIG_ARCHES)
  59 u32 ddr_wrdtr(u32 default_val) {
  60         return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823);
  61 }
  62 #else
  63 u32 ddr_wrdtr(u32 default_val) {
  64         return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
  65 }
  66
  67 u32 ddr_clktr(u32 default_val) {
  68         return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
  69 }
  70 #endif
  71
  72 #if defined(CONFIG_ARCHES)
  73 /*
  74  * FPGA read/write helper macros
  75  */
  76 static inline int board_fpga_read(int offset)
  77 {
  78         int data;
  79
  80         data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
  81
  82         return data;
  83 }
  84
  85 static inline void board_fpga_write(int offset, int data)
  86 {
  87         out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
  88 }
  89
  90 /*
  91  * CPLD read/write helper macros
  92  */
  93 static inline int board_cpld_read(int offset)
  94 {
  95         int data;
  96
  97         out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
  98         data = in_8((void *)(CONFIG_SYS_CPLD_DATA));
  99
 100         return data;
 101 }
 102
 103 static inline void board_cpld_write(int offset, int data)
 104 {
 105         out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
 106         out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
 107 }
 108 #else
 109 static int pvr_460ex(void)
 110 {
 111         u32 pvr = get_pvr();
 112
 113         if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) ||
 114             (pvr == PVR_460EX_RB))
 115                 return 1;
 116
 117         return 0;
 118 }
 119 #endif  /* defined(CONFIG_ARCHES) */
 120
 121 int board_early_init_f(void)
 122 {
 123 #if !defined(CONFIG_ARCHES)
 124         u32 sdr0_cust0;
 125         struct board_bcsr *bcsr_data =
 126                 (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
 127
 128 #endif
 129
 130         /*
 131          * Setup the interrupt controller polarities, triggers, etc.
 132          */
 133         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
 134         mtdcr(UIC0ER, 0x00000000);      /* disable all */
 135         mtdcr(UIC0CR, 0x00000005);      /* ATI & UIC1 crit are critical */
 136         mtdcr(UIC0PR, 0xffffffff);      /* per ref-board manual */
 137         mtdcr(UIC0TR, 0x00000000);      /* per ref-board manual */
 138         mtdcr(UIC0VR, 0x00000000);      /* int31 highest, base=0x000 */
 139         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
 140
 141         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 142         mtdcr(UIC1ER, 0x00000000);      /* disable all */
 143         mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
 144         mtdcr(UIC1PR, 0xffffffff);      /* per ref-board manual */
 145         mtdcr(UIC1TR, 0x00000000);      /* per ref-board manual */
 146         mtdcr(UIC1VR, 0x00000000);      /* int31 highest, base=0x000 */
 147         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 148
 149         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
 150         mtdcr(UIC2ER, 0x00000000);      /* disable all */
 151         mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
 152         mtdcr(UIC2PR, 0xffffffff);      /* per ref-board manual */
 153         mtdcr(UIC2TR, 0x00000000);      /* per ref-board manual */
 154         mtdcr(UIC2VR, 0x00000000);      /* int31 highest, base=0x000 */
 155         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
 156
 157         mtdcr(UIC3SR, 0xffffffff);      /* clear all */
 158         mtdcr(UIC3ER, 0x00000000);      /* disable all */
 159         mtdcr(UIC3CR, 0x00000000);      /* all non-critical */
 160         mtdcr(UIC3PR, 0xffffffff);      /* per ref-board manual */
 161         mtdcr(UIC3TR, 0x00000000);      /* per ref-board manual */
 162         mtdcr(UIC3VR, 0x00000000);      /* int31 highest, base=0x000 */
 163         mtdcr(UIC3SR, 0xffffffff);      /* clear all */
 164
 165 #if !defined(CONFIG_ARCHES)
 166         /* SDR Setting - enable NDFC */
 167         mfsdr(SDR0_CUST0, sdr0_cust0);
 168         sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL    |
 169                 SDR0_CUST0_NDFC_ENABLE          |
 170                 SDR0_CUST0_NDFC_BW_8_BIT        |
 171                 SDR0_CUST0_NDFC_ARE_MASK        |
 172                 SDR0_CUST0_NDFC_BAC_ENCODE(3)   |
 173                 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
 174         mtsdr(SDR0_CUST0, sdr0_cust0);
 175 #endif
 176
 177         /*
 178          * Configure PFC (Pin Function Control) registers
 179          * UART0: 4 pins
 180          */
 181         mtsdr(SDR0_PFC1, 0x00040000);
 182
 183         /* Enable PCI host functionality in SDR0_PCI0 */
 184         mtsdr(SDR0_PCI0, 0xe0000000);
 185
 186 #if !defined(CONFIG_ARCHES)
 187         /* Enable ethernet and take out of reset */
 188         out_8(&bcsr_data->eth_ctrl, 0) ;
 189
 190         /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
 191         out_8(&bcsr_data->flash_ctrl, 0) ;
 192         mtsdr(SDR0_SRST1, 0);   /* Pull AHB out of reset default=1 */
 193
 194         /* Setup PLB4-AHB bridge based on the system address map */
 195         mtdcr(AHB_TOP, 0x8000004B);
 196         mtdcr(AHB_BOT, 0x8000004B);
 197
 198 #endif
 199
 200         return 0;
 201 }
 202
 203 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
 204 int usb_board_init(void)
 205 {
 206         struct board_bcsr *bcsr_data =
 207                 (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
 208         u8 val;
 209
 210         /* Enable USB host & USB-OTG */
 211         val = in_8(&bcsr_data->usb_ctrl);
 212         val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
 213         out_8(&bcsr_data->usb_ctrl, val);
 214
 215         /*
 216          * Configure USB-STP pins as alternate and not GPIO
 217          * It seems to be neccessary to configure the STP pins as GPIO
 218          * input at powerup (perhaps while USB reset is asserted). So
 219          * we configure those pins to their "real" function now.
 220          */
 221         gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
 222         gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
 223
 224         return 0;
 225 }
 226
 227 int usb_board_stop(void)
 228 {
 229         struct board_bcsr *bcsr_data =
 230                 (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
 231         u8 val;
 232
 233         /* Disable USB host & USB-OTG */
 234         val = in_8(&bcsr_data->usb_ctrl);
 235         val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
 236         out_8(&bcsr_data->usb_ctrl, val);
 237
 238         /* Reconfigure USB-STP pins as input */
 239         gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
 240         gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
 241
 242         return 0;
 243 }
 244
 245 int usb_board_init_fail(void)
 246 {
 247         return usb_board_stop();
 248 }
 249 #endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
 250
 251 #if !defined(CONFIG_ARCHES)
 252 static void canyonlands_sata_init(int board_type)
 253 {
 254         u32 reg;
 255
 256         if (board_type == BOARD_CANYONLANDS_SATA) {
 257                 /* Put SATA in reset */
 258                 SDR_WRITE(SDR0_SRST1, 0x00020001);
 259
 260                 /* Set the phy for SATA, not PCI-E port 0 */
 261                 reg = SDR_READ(PESDR0_PHY_CTL_RST);
 262                 SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
 263                 reg = SDR_READ(PESDR0_L0CLK);
 264                 SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
 265                 SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
 266                 SDR_WRITE(PESDR0_L0DRV, 0x00000104);
 267
 268                 /* Bring SATA out of reset */
 269                 SDR_WRITE(SDR0_SRST1, 0x00000000);
 270         }
 271 }
 272 #endif  /* !defined(CONFIG_ARCHES) */
 273
 274 int get_cpu_num(void)
 275 {
 276         int cpu = NA_OR_UNKNOWN_CPU;
 277
 278 #if defined(CONFIG_ARCHES)
 279         int cpu_num;
 280
 281         cpu_num = board_fpga_read(0x3);
 282
 283         /* sanity check; assume cpu numbering starts and increments from 0 */
 284         if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
 285                 cpu = cpu_num;
 286 #endif
 287
 288         return cpu;
 289 }
 290
 291 #if !defined(CONFIG_ARCHES)
 292 int checkboard(void)
 293 {
 294         struct board_bcsr *bcsr_data =
 295                 (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
 296         char *s = getenv("serial#");
 297
 298         if (pvr_460ex()) {
 299                 printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
 300                 if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
 301                         gd->board_type = BOARD_CANYONLANDS_PCIE;
 302                 else
 303                         gd->board_type = BOARD_CANYONLANDS_SATA;
 304         } else {
 305                 printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
 306                 gd->board_type = BOARD_GLACIER;
 307         }
 308
 309         switch (gd->board_type) {
 310         case BOARD_CANYONLANDS_PCIE:
 311         case BOARD_GLACIER:
 312                 puts(", 2*PCIe");
 313                 break;
 314
 315         case BOARD_CANYONLANDS_SATA:
 316                 puts(", 1*PCIe/1*SATA");
 317                 break;
 318         }
 319
 320         printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));
 321
 322         if (s != NULL) {
 323                 puts(", serial# ");
 324                 puts(s);
 325         }
 326         putc('\n');
 327
 328         canyonlands_sata_init(gd->board_type);
 329
 330         return (0);
 331 }
 332
 333 #else   /* defined(CONFIG_ARCHES) */
 334
 335 int checkboard(void)
 336 {
 337         char *s = getenv("serial#");
 338
 339         printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
 340         printf("       Revision %02x.%02x ",
 341                                 board_fpga_read(0x0), board_fpga_read(0x1));
 342
 343         gd->board_type = BOARD_ARCHES;
 344
 345         /* Only CPU0 has access to CPLD registers */
 346         if (get_cpu_num() == 0) {
 347                 u8 cfg_sw = board_cpld_read(0x1);
 348                 printf("(FPGA=%02x, CPLD=%02x)\n",
 349                                 board_fpga_read(0x2), board_cpld_read(0x0));
 350                 printf("       Configuration Switch %d%d%d%d\n",
 351                                 ((cfg_sw >> 3) & 0x01),
 352                                 ((cfg_sw >> 2) & 0x01),
 353                                 ((cfg_sw >> 1) & 0x01),
 354                                 ((cfg_sw >> 0) & 0x01));
 355         } else
 356                 printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
 357
 358
 359         if (s != NULL)
 360                 printf("       Serial# %s\n", s);
 361
 362         return 0;
 363 }
 364 #endif  /* !defined(CONFIG_ARCHES) */
 365
 366 #if defined(CONFIG_PCI)
 367 int board_pcie_first(void)
 368 {
 369         /*
 370          * Canyonlands with SATA enabled has only one PCIe slot
 371          * (2nd one).
 372          */
 373         if (gd->board_type == BOARD_CANYONLANDS_SATA)
 374                 return 1;
 375
 376         return 0;
 377 }
 378 #endif /* CONFIG_PCI */
 379
 380 int board_early_init_r (void)
 381 {
 382         /*
 383          * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
 384          * boot EBC mapping only supports a maximum of 16MBytes
 385          * (4.ff00.0000 - 4.ffff.ffff).
 386          * To solve this problem, the FLASH has to get remapped to another
 387          * EBC address which accepts bigger regions:
 388          *
 389          * 0xfc00.0000 -> 4.cc00.0000
 390          */
 391
 392         /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
 393 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 394         mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
 395 #else
 396         mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
 397 #endif
 398
 399         /* Remove TLB entry of boot EBC mapping */
 400         remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
 401
 402         /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
 403         program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
 404                     TLB_WORD2_I_ENABLE);
 405
 406         /*
 407          * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
 408          * 0xfc00.0000 is possible
 409          */
 410
 411         /*
 412          * Clear potential errors resulting from auto-calibration.
 413          * If not done, then we could get an interrupt later on when
 414          * exceptions are enabled.
 415          */
 416         set_mcsr(get_mcsr());
 417
 418         return 0;
 419 }
 420
 421 #if !defined(CONFIG_ARCHES)
 422 int misc_init_r(void)
 423 {
 424         u32 sdr0_srst1 = 0;
 425         u32 eth_cfg;
 426         u8 val;
 427
 428         /*
 429          * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
 430          * This is board specific, so let's do it here.
 431          */
 432         mfsdr(SDR0_ETH_CFG, eth_cfg);
 433         /* disable SGMII mode */
 434         eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
 435                      SDR0_ETH_CFG_SGMII1_ENABLE |
 436                      SDR0_ETH_CFG_SGMII0_ENABLE);
 437         /* Set the for 2 RGMII mode */
 438         /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
 439         eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
 440         if (pvr_460ex())
 441                 eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
 442         else
 443                 eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
 444         mtsdr(SDR0_ETH_CFG, eth_cfg);
 445
 446         /*
 447          * The AHB Bridge core is held in reset after power-on or reset
 448          * so enable it now
 449          */
 450         mfsdr(SDR0_SRST1, sdr0_srst1);
 451         sdr0_srst1 &= ~SDR0_SRST1_AHB;
 452         mtsdr(SDR0_SRST1, sdr0_srst1);
 453
 454         /*
 455          * RTC/M41T62:
 456          * Disable square wave output: Batterie will be drained
 457          * quickly, when this output is not disabled
 458          */
 459         val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
 460         val &= ~0x40;
 461         i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);
 462
 463         return 0;
 464 }
 465
 466 #else   /* defined(CONFIG_ARCHES) */
 467
 468 int misc_init_r(void)
 469 {
 470         u32 eth_cfg = 0;
 471         u32 eth_pll;
 472         u32 reg;
 473
 474         /*
 475          * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
 476          * This is board specific, so let's do it here.
 477          */
 478
 479         /* enable SGMII mode */
 480         eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE |
 481                         SDR0_ETH_CFG_SGMII1_ENABLE |
 482                         SDR0_ETH_CFG_SGMII2_ENABLE);
 483
 484         /* Set EMAC for MDIO */
 485         eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
 486
 487         /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
 488         eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
 489
 490         mtsdr(SDR0_ETH_CFG, eth_cfg);
 491
 492         /* reset all SGMII interfaces */
 493         mfsdr(SDR0_SRST1,   reg);
 494         reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2);
 495         mtsdr(SDR0_SRST1, reg);
 496         mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
 497         mtsdr(SDR0_SRST1,   0x00000000);
 498
 499         do {
 500                 mfsdr(SDR0_ETH_PLL, eth_pll);
 501         } while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));
 502
 503         return 0;
 504 }
 505 #endif  /* !defined(CONFIG_ARCHES) */
 506
 507 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 508 extern void __ft_board_setup(void *blob, bd_t *bd);
 509
 510 void ft_board_setup(void *blob, bd_t *bd)
 511 {
 512         __ft_board_setup(blob, bd);
 513
 514         if (gd->board_type == BOARD_CANYONLANDS_SATA) {
 515                 /*
 516                  * When SATA is selected we need to disable the first PCIe
 517                  * node in the device tree, so that Linux doesn't initialize
 518                  * it.
 519                  */
 520                 fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
 521                                      "disabled", sizeof("disabled"), 1);
 522         }
 523
 524         if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
 525                 /*
 526                  * When PCIe is selected we need to disable the SATA
 527                  * node in the device tree, so that Linux doesn't initialize
 528                  * it.
 529                  */
 530                 fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
 531                                      "disabled", sizeof("disabled"), 1);
 532         }
 533 }
 534 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */