board/amcc/canyonlands/canyonlands.c

   1 /*
   2  * (C) Copyright 2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #include <common.h>
  22 #include <ppc440.h>
  23 #include <libfdt.h>
  24 #include <fdt_support.h>
  25 #include <i2c.h>
  26 #include <asm/processor.h>
  27 #include <asm/io.h>
  28 #include <asm/mmu.h>
  29 #include <asm/4xx_pcie.h>
  30 #include <asm/gpio.h>
  31
  32 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #define CONFIG_SYS_BCSR3_PCIE           0x10
  37
  38 #define BOARD_CANYONLANDS_PCIE  1
  39 #define BOARD_CANYONLANDS_SATA  2
  40 #define BOARD_GLACIER           3
  41 #define BOARD_ARCHES            4
  42
  43 /*
  44  * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
  45  * board specific values.
  46  */
  47 #if defined(CONFIG_ARCHES)
  48 u32 ddr_wrdtr(u32 default_val) {
  49         return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823);
  50 }
  51 #else
  52 u32 ddr_wrdtr(u32 default_val) {
  53         return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
  54 }
  55
  56 u32 ddr_clktr(u32 default_val) {
  57         return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
  58 }
  59 #endif
  60
  61 #if defined(CONFIG_ARCHES)
  62 /*
  63  * FPGA read/write helper macros
  64  */
  65 static inline int board_fpga_read(int offset)
  66 {
  67         int data;
  68
  69         data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
  70
  71         return data;
  72 }
  73
  74 static inline void board_fpga_write(int offset, int data)
  75 {
  76         out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
  77 }
  78
  79 /*
  80  * CPLD read/write helper macros
  81  */
  82 static inline int board_cpld_read(int offset)
  83 {
  84         int data;
  85
  86         out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
  87         data = in_8((void *)(CONFIG_SYS_CPLD_DATA));
  88
  89         return data;
  90 }
  91
  92 static inline void board_cpld_write(int offset, int data)
  93 {
  94         out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
  95         out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
  96 }
  97 #else
  98 static int pvr_460ex(void)
  99 {
 100         u32 pvr = get_pvr();
 101
 102         if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) ||
 103             (pvr == PVR_460EX_RB))
 104                 return 1;
 105
 106         return 0;
 107 }
 108 #endif  /* defined(CONFIG_ARCHES) */
 109
 110 int board_early_init_f(void)
 111 {
 112 #if !defined(CONFIG_ARCHES)
 113         u32 sdr0_cust0;
 114 #endif
 115
 116         /*
 117          * Setup the interrupt controller polarities, triggers, etc.
 118          */
 119         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 120         mtdcr(uic0er, 0x00000000);      /* disable all */
 121         mtdcr(uic0cr, 0x00000005);      /* ATI & UIC1 crit are critical */
 122         mtdcr(uic0pr, 0xffffffff);      /* per ref-board manual */
 123         mtdcr(uic0tr, 0x00000000);      /* per ref-board manual */
 124         mtdcr(uic0vr, 0x00000000);      /* int31 highest, base=0x000 */
 125         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 126
 127         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 128         mtdcr(uic1er, 0x00000000);      /* disable all */
 129         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
 130         mtdcr(uic1pr, 0xffffffff);      /* per ref-board manual */
 131         mtdcr(uic1tr, 0x00000000);      /* per ref-board manual */
 132         mtdcr(uic1vr, 0x00000000);      /* int31 highest, base=0x000 */
 133         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 134
 135         mtdcr(uic2sr, 0xffffffff);      /* clear all */
 136         mtdcr(uic2er, 0x00000000);      /* disable all */
 137         mtdcr(uic2cr, 0x00000000);      /* all non-critical */
 138         mtdcr(uic2pr, 0xffffffff);      /* per ref-board manual */
 139         mtdcr(uic2tr, 0x00000000);      /* per ref-board manual */
 140         mtdcr(uic2vr, 0x00000000);      /* int31 highest, base=0x000 */
 141         mtdcr(uic2sr, 0xffffffff);      /* clear all */
 142
 143         mtdcr(uic3sr, 0xffffffff);      /* clear all */
 144         mtdcr(uic3er, 0x00000000);      /* disable all */
 145         mtdcr(uic3cr, 0x00000000);      /* all non-critical */
 146         mtdcr(uic3pr, 0xffffffff);      /* per ref-board manual */
 147         mtdcr(uic3tr, 0x00000000);      /* per ref-board manual */
 148         mtdcr(uic3vr, 0x00000000);      /* int31 highest, base=0x000 */
 149         mtdcr(uic3sr, 0xffffffff);      /* clear all */
 150
 151 #if !defined(CONFIG_ARCHES)
 152         /* SDR Setting - enable NDFC */
 153         mfsdr(SDR0_CUST0, sdr0_cust0);
 154         sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL    |
 155                 SDR0_CUST0_NDFC_ENABLE          |
 156                 SDR0_CUST0_NDFC_BW_8_BIT        |
 157                 SDR0_CUST0_NDFC_ARE_MASK        |
 158                 SDR0_CUST0_NDFC_BAC_ENCODE(3)   |
 159                 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
 160         mtsdr(SDR0_CUST0, sdr0_cust0);
 161 #endif
 162
 163         /*
 164          * Configure PFC (Pin Function Control) registers
 165          * UART0: 4 pins
 166          */
 167         mtsdr(SDR0_PFC1, 0x00040000);
 168
 169         /* Enable PCI host functionality in SDR0_PCI0 */
 170         mtsdr(SDR0_PCI0, 0xe0000000);
 171
 172 #if !defined(CONFIG_ARCHES)
 173         /* Enable ethernet and take out of reset */
 174         out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0);
 175
 176         /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
 177         out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0);
 178
 179         /* Enable USB host & USB-OTG */
 180         out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0);
 181
 182         mtsdr(SDR0_SRST1, 0);   /* Pull AHB out of reset default=1 */
 183
 184         /* Setup PLB4-AHB bridge based on the system address map */
 185         mtdcr(AHB_TOP, 0x8000004B);
 186         mtdcr(AHB_BOT, 0x8000004B);
 187
 188         if (pvr_460ex()) {
 189                 /*
 190                  * Configure USB-STP pins as alternate and not GPIO
 191                  * It seems to be neccessary to configure the STP pins as GPIO
 192                  * input at powerup (perhaps while USB reset is asserted). So
 193                  * we configure those pins to their "real" function now.
 194                  */
 195                 gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
 196                 gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
 197         }
 198 #endif
 199
 200         return 0;
 201 }
 202
 203 #if !defined(CONFIG_ARCHES)
 204 static void canyonlands_sata_init(int board_type)
 205 {
 206         u32 reg;
 207
 208         if (board_type == BOARD_CANYONLANDS_SATA) {
 209                 /* Put SATA in reset */
 210                 SDR_WRITE(SDR0_SRST1, 0x00020001);
 211
 212                 /* Set the phy for SATA, not PCI-E port 0 */
 213                 reg = SDR_READ(PESDR0_PHY_CTL_RST);
 214                 SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
 215                 reg = SDR_READ(PESDR0_L0CLK);
 216                 SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
 217                 SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
 218                 SDR_WRITE(PESDR0_L0DRV, 0x00000104);
 219
 220                 /* Bring SATA out of reset */
 221                 SDR_WRITE(SDR0_SRST1, 0x00000000);
 222         }
 223 }
 224 #endif  /* !defined(CONFIG_ARCHES) */
 225
 226 int get_cpu_num(void)
 227 {
 228         int cpu = NA_OR_UNKNOWN_CPU;
 229
 230 #if defined(CONFIG_ARCHES)
 231         int cpu_num;
 232
 233         cpu_num = board_fpga_read(0x3);
 234
 235         /* sanity check; assume cpu numbering starts and increments from 0 */
 236         if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
 237                 cpu = cpu_num;
 238 #endif
 239
 240         return cpu;
 241 }
 242
 243 #if !defined(CONFIG_ARCHES)
 244 int checkboard(void)
 245 {
 246         char *s = getenv("serial#");
 247
 248         if (pvr_460ex()) {
 249                 printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
 250                 if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE)
 251                         gd->board_type = BOARD_CANYONLANDS_PCIE;
 252                 else
 253                         gd->board_type = BOARD_CANYONLANDS_SATA;
 254         } else {
 255                 printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
 256                 gd->board_type = BOARD_GLACIER;
 257         }
 258
 259         switch (gd->board_type) {
 260         case BOARD_CANYONLANDS_PCIE:
 261         case BOARD_GLACIER:
 262                 puts(", 2*PCIe");
 263                 break;
 264
 265         case BOARD_CANYONLANDS_SATA:
 266                 puts(", 1*PCIe/1*SATA");
 267                 break;
 268         }
 269
 270         printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)));
 271
 272         if (s != NULL) {
 273                 puts(", serial# ");
 274                 puts(s);
 275         }
 276         putc('\n');
 277
 278         canyonlands_sata_init(gd->board_type);
 279
 280         return (0);
 281 }
 282
 283 #else   /* defined(CONFIG_ARCHES) */
 284
 285 int checkboard(void)
 286 {
 287         char *s = getenv("serial#");
 288
 289         printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
 290         printf("       Revision %02x.%02x ",
 291                                 board_fpga_read(0x0), board_fpga_read(0x1));
 292
 293         gd->board_type = BOARD_ARCHES;
 294
 295         /* Only CPU0 has access to CPLD registers */
 296         if (get_cpu_num() == 0) {
 297                 u8 cfg_sw = board_cpld_read(0x1);
 298                 printf("(FPGA=%02x, CPLD=%02x)\n",
 299                                 board_fpga_read(0x2), board_cpld_read(0x0));
 300                 printf("       Configuration Switch %d%d%d%d\n",
 301                                 ((cfg_sw >> 3) & 0x01),
 302                                 ((cfg_sw >> 2) & 0x01),
 303                                 ((cfg_sw >> 1) & 0x01),
 304                                 ((cfg_sw >> 0) & 0x01));
 305         } else
 306                 printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
 307
 308
 309         if (s != NULL)
 310                 printf("       Serial# %s\n", s);
 311
 312         return 0;
 313 }
 314 #endif  /* !defined(CONFIG_ARCHES) */
 315
 316 #if defined(CONFIG_NAND_U_BOOT)
 317 /*
 318  * NAND booting U-Boot version uses a fixed initialization, since the whole
 319  * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
 320  * code.
 321  */
 322 phys_size_t initdram(int board_type)
 323 {
 324         return CONFIG_SYS_MBYTES_SDRAM << 20;
 325 }
 326 #endif
 327
 328 /*
 329  *  pci_target_init
 330  *
 331  *      The bootstrap configuration provides default settings for the pci
 332  *      inbound map (PIM). But the bootstrap config choices are limited and
 333  *      may not be sufficient for a given board.
 334  */
 335 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 336 void pci_target_init(struct pci_controller * hose )
 337 {
 338         /*
 339          * Disable everything
 340          */
 341         out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
 342         out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
 343         out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
 344         out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
 345
 346         /*
 347          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
 348          * strapping options to not support sizes such as 128/256 MB.
 349          */
 350         out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
 351         out_le32((void *)PCIX0_PIM0LAH, 0);
 352         out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
 353         out_le32((void *)PCIX0_BAR0, 0);
 354
 355         /*
 356          * Program the board's subsystem id/vendor id
 357          */
 358         out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
 359         out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 360
 361         out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
 362 }
 363 #endif  /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 364
 365 #if defined(CONFIG_PCI)
 366 /*
 367  * is_pci_host
 368  *
 369  * This routine is called to determine if a pci scan should be
 370  * performed. With various hardware environments (especially cPCI and
 371  * PPMC) it's insufficient to depend on the state of the arbiter enable
 372  * bit in the strap register, or generic host/adapter assumptions.
 373  *
 374  * Rather than hard-code a bad assumption in the general 440 code, the
 375  * 440 pci code requires the board to decide at runtime.
 376  *
 377  * Return 0 for adapter mode, non-zero for host (monarch) mode.
 378  */
 379 int is_pci_host(struct pci_controller *hose)
 380 {
 381         /* Board is always configured as host. */
 382         return (1);
 383 }
 384
 385 static struct pci_controller pcie_hose[2] = {{0},{0}};
 386
 387 void pcie_setup_hoses(int busno)
 388 {
 389         struct pci_controller *hose;
 390         int i, bus;
 391         int ret = 0;
 392         char *env;
 393         unsigned int delay;
 394         int start;
 395
 396         /*
 397          * assume we're called after the PCIX hose is initialized, which takes
 398          * bus ID 0 and therefore start numbering PCIe's from 1.
 399          */
 400         bus = busno;
 401
 402         /*
 403          * Canyonlands with SATA enabled has only one PCIe slot
 404          * (2nd one).
 405          */
 406         if (gd->board_type == BOARD_CANYONLANDS_SATA)
 407                 start = 1;
 408         else
 409                 start = 0;
 410
 411         for (i = start; i <= 1; i++) {
 412
 413                 if (is_end_point(i))
 414                         ret = ppc4xx_init_pcie_endport(i);
 415                 else
 416                         ret = ppc4xx_init_pcie_rootport(i);
 417                 if (ret) {
 418                         printf("PCIE%d: initialization as %s failed\n", i,
 419                                is_end_point(i) ? "endpoint" : "root-complex");
 420                         continue;
 421                 }
 422
 423                 hose = &pcie_hose[i];
 424                 hose->first_busno = bus;
 425                 hose->last_busno = bus;
 426                 hose->current_busno = bus;
 427
 428                 /* setup mem resource */
 429                 pci_set_region(hose->regions + 0,
 430                                CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
 431                                CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
 432                                CONFIG_SYS_PCIE_MEMSIZE,
 433                                PCI_REGION_MEM);
 434                 hose->region_count = 1;
 435                 pci_register_hose(hose);
 436
 437                 if (is_end_point(i)) {
 438                         ppc4xx_setup_pcie_endpoint(hose, i);
 439                         /*
 440                          * Reson for no scanning is endpoint can not generate
 441                          * upstream configuration accesses.
 442                          */
 443                 } else {
 444                         ppc4xx_setup_pcie_rootpoint(hose, i);
 445                         env = getenv ("pciscandelay");
 446                         if (env != NULL) {
 447                                 delay = simple_strtoul(env, NULL, 10);
 448                                 if (delay > 5)
 449                                         printf("Warning, expect noticable delay before "
 450                                                "PCIe scan due to 'pciscandelay' value!\n");
 451                                 mdelay(delay * 1000);
 452                         }
 453
 454                         /*
 455                          * Config access can only go down stream
 456                          */
 457                         hose->last_busno = pci_hose_scan(hose);
 458                         bus = hose->last_busno + 1;
 459                 }
 460         }
 461 }
 462 #endif /* CONFIG_PCI */
 463
 464 int board_early_init_r (void)
 465 {
 466         /*
 467          * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
 468          * boot EBC mapping only supports a maximum of 16MBytes
 469          * (4.ff00.0000 - 4.ffff.ffff).
 470          * To solve this problem, the FLASH has to get remapped to another
 471          * EBC address which accepts bigger regions:
 472          *
 473          * 0xfc00.0000 -> 4.cc00.0000
 474          */
 475
 476         /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
 477 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 478         mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
 479 #else
 480         mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
 481 #endif
 482
 483         /* Remove TLB entry of boot EBC mapping */
 484         remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
 485
 486         /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
 487         program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
 488                     TLB_WORD2_I_ENABLE);
 489
 490         /*
 491          * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
 492          * 0xfc00.0000 is possible
 493          */
 494
 495         /*
 496          * Clear potential errors resulting from auto-calibration.
 497          * If not done, then we could get an interrupt later on when
 498          * exceptions are enabled.
 499          */
 500         set_mcsr(get_mcsr());
 501
 502         return 0;
 503 }
 504
 505 #if !defined(CONFIG_ARCHES)
 506 int misc_init_r(void)
 507 {
 508         u32 sdr0_srst1 = 0;
 509         u32 eth_cfg;
 510         u8 val;
 511
 512         /*
 513          * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
 514          * This is board specific, so let's do it here.
 515          */
 516         mfsdr(SDR0_ETH_CFG, eth_cfg);
 517         /* disable SGMII mode */
 518         eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
 519                      SDR0_ETH_CFG_SGMII1_ENABLE |
 520                      SDR0_ETH_CFG_SGMII0_ENABLE);
 521         /* Set the for 2 RGMII mode */
 522         /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
 523         eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
 524         if (pvr_460ex())
 525                 eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
 526         else
 527                 eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
 528         mtsdr(SDR0_ETH_CFG, eth_cfg);
 529
 530         /*
 531          * The AHB Bridge core is held in reset after power-on or reset
 532          * so enable it now
 533          */
 534         mfsdr(SDR0_SRST1, sdr0_srst1);
 535         sdr0_srst1 &= ~SDR0_SRST1_AHB;
 536         mtsdr(SDR0_SRST1, sdr0_srst1);
 537
 538         /*
 539          * RTC/M41T62:
 540          * Disable square wave output: Batterie will be drained
 541          * quickly, when this output is not disabled
 542          */
 543         val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
 544         val &= ~0x40;
 545         i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);
 546
 547         return 0;
 548 }
 549
 550 #else   /* defined(CONFIG_ARCHES) */
 551
 552 int misc_init_r(void)
 553 {
 554         u32 eth_cfg = 0;
 555         u32 eth_pll;
 556         u32 reg;
 557
 558         /*
 559          * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
 560          * This is board specific, so let's do it here.
 561          */
 562
 563         /* enable SGMII mode */
 564         eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE |
 565                         SDR0_ETH_CFG_SGMII1_ENABLE |
 566                         SDR0_ETH_CFG_SGMII2_ENABLE);
 567
 568         /* Set EMAC for MDIO */
 569         eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
 570
 571         /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
 572         eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
 573
 574         mtsdr(SDR0_ETH_CFG, eth_cfg);
 575
 576         /* reset all SGMII interfaces */
 577         mfsdr(SDR0_SRST1,   reg);
 578         reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2);
 579         mtsdr(SDR0_SRST1, reg);
 580         mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
 581         mtsdr(SDR0_SRST1,   0x00000000);
 582
 583         do {
 584                 mfsdr(SDR0_ETH_PLL, eth_pll);
 585         } while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));
 586
 587         return 0;
 588 }
 589 #endif  /* !defined(CONFIG_ARCHES) */
 590
 591 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 592 extern void __ft_board_setup(void *blob, bd_t *bd);
 593
 594 void ft_board_setup(void *blob, bd_t *bd)
 595 {
 596         __ft_board_setup(blob, bd);
 597
 598         if (gd->board_type == BOARD_CANYONLANDS_SATA) {
 599                 /*
 600                  * When SATA is selected we need to disable the first PCIe
 601                  * node in the device tree, so that Linux doesn't initialize
 602                  * it.
 603                  */
 604                 fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
 605                                      "disabled", sizeof("disabled"), 1);
 606         }
 607
 608         if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
 609                 /*
 610                  * When PCIe is selected we need to disable the SATA
 611                  * node in the device tree, so that Linux doesn't initialize
 612                  * it.
 613                  */
 614                 fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
 615                                      "disabled", sizeof("disabled"), 1);
 616         }
 617 }
 618 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */