board/amcc/canyonlands/init.S

   1 /*
   2  * (C) Copyright 2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <asm-offsets.h>
   9 #include <ppc_asm.tmpl>
  10 #include <config.h>
  11 #include <asm/mmu.h>
  12
  13 /**************************************************************************
  14  * TLB TABLE
  15  *
  16  * This table is used by the cpu boot code to setup the initial tlb
  17  * entries. Rather than make broad assumptions in the cpu source tree,
  18  * this table lets each board set things up however they like.
  19  *
  20  *  Pointer to the table is returned in r1
  21  *
  22  *************************************************************************/
  23         .section .bootpg,"ax"
  24         .globl tlbtab
  25
  26 tlbtab:
  27         tlbtab_start
  28
  29         /*
  30          * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
  31          * use the speed up boot process. It is patched after relocation to
  32          * enable SA_I
  33          */
  34 #ifndef CONFIG_NAND_SPL
  35         tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */
  36 #else
  37         tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_RWX | SA_G)
  38         tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
  39         tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_RWX | SA_IG)
  40 #endif
  41
  42         /*
  43          * TLB entries for SDRAM are not needed on this platform.
  44          * They are dynamically generated in the SPD DDR(2) detection
  45          * routine.
  46          */
  47
  48 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
  49         /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
  50         tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
  51 #endif
  52
  53         tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
  54         tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_RW | SA_IG)
  55         tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
  56
  57         tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
  58         tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
  59         tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
  60         tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
  61
  62         /* PCIe UTL register */
  63         tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_RW | SA_IG)
  64
  65 #if !defined(CONFIG_ARCHES)
  66         /* TLB-entry for NAND */
  67         tlbentry(CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 4, AC_RWX | SA_IG)
  68
  69         /* TLB-entry for CPLD */
  70         tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_RW | SA_IG)
  71 #else
  72         /* TLB-entry for FPGA */
  73         tlbentry(CONFIG_SYS_FPGA_BASE, SZ_16M, CONFIG_SYS_FPGA_BASE, 4, AC_RW | SA_IG)
  74 #endif
  75
  76         /* TLB-entry for OCM */
  77         tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, AC_RWX | SA_I)
  78
  79         /* TLB-entry for Local Configuration registers => peripherals */
  80         tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG)
  81
  82         /* AHB: Internal USB Peripherals (USB, SATA) */
  83         tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_RWX | SA_IG)
  84
  85 #if defined(CONFIG_RAPIDIO)
  86         /* TLB-entries for RapidIO (SRIO) */
  87         tlbentry(CONFIG_SYS_SRGPL0_REG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_REG_BAR,
  88                                         0xD, AC_RW | SA_IG)
  89         tlbentry(CONFIG_SYS_SRGPL0_CFG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_CFG_BAR,
  90                                         0xD, AC_RW | SA_IG)
  91         tlbentry(CONFIG_SYS_SRGPL0_MNT_BAR, SZ_16M, CONFIG_SYS_SRGPL0_MNT_BAR,
  92                                         0xD, AC_RW | SA_IG)
  93         tlbentry(CONFIG_SYS_I2ODMA_BASE, SZ_1K,  0x00100000,
  94                                         0x4, AC_RW | SA_IG)
  95 #endif
  96
  97         tlbtab_end
  98
  99 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 100         /*
 101          * For NAND booting the first TLB has to be reconfigured to full size
 102          * and with caching disabled after running from RAM!
 103          */
 104 #define TLB00   TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
 105 #define TLB01   TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
 106 #define TLB02   TLB2(AC_RWX | SA_IG)
 107
 108         .globl  reconfig_tlb0
 109 reconfig_tlb0:
 110         sync
 111         isync
 112         addi    r4,r0,0x0000            /* TLB entry #0 */
 113         lis     r5,TLB00@h
 114         ori     r5,r5,TLB00@l
 115         tlbwe   r5,r4,0x0000            /* Save it out */
 116         lis     r5,TLB01@h
 117         ori     r5,r5,TLB01@l
 118         tlbwe   r5,r4,0x0001            /* Save it out */
 119         lis     r5,TLB02@h
 120         ori     r5,r5,TLB02@l
 121         tlbwe   r5,r4,0x0002            /* Save it out */
 122         sync
 123         isync
 124         blr
 125 #endif