board/amcc/luan/luan.c

   1 /*
   2  * (C) Copyright 2005
   3  * John Otken, jotken@softadvances.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <command.h>
  26 #include <ppc4xx.h>
  27 #include <asm/processor.h>
  28 #include <spd_sdram.h>
  29 #include "epld.h"
  30
  31
  32 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  33
  34
  35 /*************************************************************************
  36  *  int board_early_init_f()
  37  *
  38  ************************************************************************/
  39 int board_early_init_f(void)
  40 {
  41         volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
  42
  43         mtebc( pb0ap,  0x03800000 );    /* set chip selects */
  44         mtebc( pb0cr,  0xffc58000 );    /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
  45         mtebc( pb1ap,  0x03800000 );
  46         mtebc( pb1cr,  0xff018000 );    /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
  47         mtebc( pb2ap,  0x03800000 );
  48         mtebc( pb2cr,  0xff838000 );    /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
  49
  50         mtdcr( uic1sr, 0xffffffff );    /* Clear all interrupts */
  51         mtdcr( uic1er, 0x00000000 );    /* disable all interrupts */
  52         mtdcr( uic1cr, 0x00000000 );    /* Set Critical / Non Critical interrupts */
  53         mtdcr( uic1pr, 0x7fff83ff );    /* Set Interrupt Polarities */
  54         mtdcr( uic1tr, 0x001f8000 );    /* Set Interrupt Trigger Levels */
  55         mtdcr( uic1vr, 0x00000001 );    /* Set Vect base=0,INT31 Highest priority */
  56         mtdcr( uic1sr, 0x00000000 );    /* clear all interrupts */
  57         mtdcr( uic1sr, 0xffffffff );
  58
  59         mtdcr( uic0sr, 0xffffffff );    /* Clear all interrupts */
  60         mtdcr( uic0er, 0x00000000 );    /* disable all interrupts excepted cascade */
  61         mtdcr( uic0cr, 0x00000001 );    /* Set Critical / Non Critical interrupts */
  62         mtdcr( uic0pr, 0xffffffff );    /* Set Interrupt Polarities */
  63         mtdcr( uic0tr, 0x01000004 );    /* Set Interrupt Trigger Levels */
  64         mtdcr( uic0vr, 0x00000001 );    /* Set Vect base=0,INT31 Highest priority */
  65         mtdcr( uic0sr, 0x00000000 );    /* clear all interrupts */
  66         mtdcr( uic0sr, 0xffffffff );
  67
  68         x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */
  69
  70         return  0;
  71 }
  72
  73
  74 /*************************************************************************
  75  *  int misc_init_r()
  76  *
  77  ************************************************************************/
  78 int misc_init_r(void)
  79 {
  80         volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
  81         x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */
  82
  83         return  0;
  84 }
  85
  86
  87 /*************************************************************************
  88  *  int checkboard()
  89  *
  90  ************************************************************************/
  91 int checkboard(void)
  92 {
  93         char *s = getenv("serial#");
  94
  95         printf("Board: Luan - AMCC PPC440SP Evaluation Board");
  96
  97         if (s != NULL) {
  98                 puts(", serial# ");
  99                 puts(s);
 100         }
 101         putc('\n');
 102
 103         return  0;
 104 }
 105
 106
 107 /*************************************************************************
 108  *  long int fixed_sdram()
 109  *
 110  ************************************************************************/
 111 static long int fixed_sdram(void)
 112 {                                       /* DDR2 init from BDI2000 script */
 113         mtdcr( 0x10, 0x00000021 );      /* MCIF0_MCOPT2 - zero DCEN bit */
 114         mtdcr( 0x11, 0x84000000 );
 115         mtdcr( 0x10, 0x00000020 );      /* MCIF0_MCOPT1 - no ECC, 64 bits, 4 banks, DDR2 */
 116         mtdcr( 0x11, 0x2D122000 );
 117         mtdcr( 0x10, 0x00000026 );      /* MCIF0_CODT  - die termination on */
 118         mtdcr( 0x11, 0x00800026 );
 119         mtdcr( 0x10, 0x00000081 );      /* MCIF0_WRDTR - Write DQS Adv 90 + Fractional DQS Delay */
 120         mtdcr( 0x11, 0x82000800 );
 121         mtdcr( 0x10, 0x00000080 );      /* MCIF0_CLKTR - advance addr clock by 180 deg */
 122         mtdcr( 0x11, 0x80000000 );
 123         mtdcr( 0x10, 0x00000040 );      /* MCIF0_MB0CF - turn on CS0, N x 10 coll */
 124         mtdcr( 0x11, 0x00000201 );
 125         mtdcr( 0x10, 0x00000044 );      /* MCIF0_MB1CF - turn on CS0, N x 10 coll */
 126         mtdcr( 0x11, 0x00000201 );
 127         mtdcr( 0x10, 0x00000030 );      /* MCIF0_RTR   - refresh every 7.8125uS */
 128         mtdcr( 0x11, 0x08200000 );
 129         mtdcr( 0x10, 0x00000085 );      /* MCIF0_SDTR1 - timing register 1 */
 130         mtdcr( 0x11, 0x80201000 );
 131         mtdcr( 0x10, 0x00000086 );      /* MCIF0_SDTR2 - timing register 2 */
 132         mtdcr( 0x11, 0x42103242 );
 133         mtdcr( 0x10, 0x00000087 );      /* MCIF0_SDTR3 - timing register 3 */
 134         mtdcr( 0x11, 0x0C100D14 );
 135         mtdcr( 0x10, 0x00000088 );      /* MCIF0_MMODE - CAS is 4 cycles */
 136         mtdcr( 0x11, 0x00000642 );
 137         mtdcr( 0x10, 0x00000089 );      /* MCIF0_MEMODE - diff DQS disabled */
 138         mtdcr( 0x11, 0x00000400 );      /*                ODT term disabled */
 139
 140         mtdcr( 0x10, 0x00000050 );      /* MCIF0_INITPLR0 - NOP */
 141         mtdcr( 0x11, 0x81b80000 );
 142         mtdcr( 0x10, 0x00000051 );      /* MCIF0_INITPLR1 - PRE */
 143         mtdcr( 0x11, 0x82100400 );
 144         mtdcr( 0x10, 0x00000052 );      /* MCIF0_INITPLR2 - EMR2 */
 145         mtdcr( 0x11, 0x80820000 );
 146         mtdcr( 0x10, 0x00000053 );      /* MCIF0_INITPLR3 - EMR3 */
 147         mtdcr( 0x11, 0x80830000 );
 148         mtdcr( 0x10, 0x00000054 );      /* MCIF0_INITPLR4 - EMR DLL ENABLE */
 149         mtdcr( 0x11, 0x80810000 );
 150         mtdcr( 0x10, 0x00000055 );      /* MCIF0_INITPLR5 - MR DLL RESET */
 151         mtdcr( 0x11, 0x80800542 );
 152         mtdcr( 0x10, 0x00000056 );      /* MCIF0_INITPLR6 - PRE */
 153         mtdcr( 0x11, 0x82100400 );
 154         mtdcr( 0x10, 0x00000057 );      /* MCIF0_INITPLR7 - refresh */
 155         mtdcr( 0x11, 0x99080000 );
 156         mtdcr( 0x10, 0x00000058 );      /* MCIF0_INITPLR8 */
 157         mtdcr( 0x11, 0x99080000 );
 158         mtdcr( 0x10, 0x00000059 );      /* MCIF0_INITPLR9 */
 159         mtdcr( 0x11, 0x99080000 );
 160         mtdcr( 0x10, 0x0000005A );      /* MCIF0_INITPLR10 */
 161         mtdcr( 0x11, 0x99080000 );
 162         mtdcr( 0x10, 0x0000005B );      /* MCIF0_INITPLR11 - MR */
 163         mtdcr( 0x11, 0x80800442 );
 164         mtdcr( 0x10, 0x0000005C );      /* MCIF0_INITPLR12 - EMR OCD Default */
 165         mtdcr( 0x11, 0x80810380 );
 166         mtdcr( 0x10, 0x0000005D );      /* MCIF0_INITPLR13 - EMR OCD exit */
 167         mtdcr( 0x11, 0x80810000 );
 168         udelay( 10*1000 );
 169
 170         mtdcr( 0x10, 0x00000021 );      /* MCIF0_MCOPT2 - execute preloaded init */
 171         mtdcr( 0x11, 0x28000000 );      /*                set DC_EN */
 172         udelay( 100*1000 );
 173
 174         mtdcr( 0x40, 0x0000F800 );      /* MQ0_B0BAS: base addr 00000000 / 256MB */
 175         mtdcr( 0x41, 0x1000F800 );      /* MQ0_B1BAS: base addr 10000000 / 256MB */
 176
 177         mtdcr( 0x10, 0x00000078 );      /* MCIF0_RDCC - auto set read stage */
 178         mtdcr( 0x11, 0x00000000 );
 179         mtdcr( 0x10, 0x00000070 );      /* MCIF0_RQDC - read DQS delay control */
 180         mtdcr( 0x11, 0x8000003A );      /*              enabled, frac DQS delay */
 181         mtdcr( 0x10, 0x00000074 );      /* MCIF0_RFDC - two clock feedback delay */
 182         mtdcr( 0x11, 0x00000200 );
 183
 184         return  512 << 20;
 185 }
 186
 187
 188 /*************************************************************************
 189  *  long int initdram
 190  *
 191  ************************************************************************/
 192 long int initdram( int board_type )
 193 {
 194         long dram_size = 0;
 195
 196 #if defined(CONFIG_SPD_EEPROM)
 197         dram_size = spd_sdram (0);
 198 #else
 199         dram_size = fixed_sdram ();
 200 #endif
 201
 202         return  dram_size;
 203 }
 204
 205
 206 /*************************************************************************
 207  *  int testdram()
 208  *
 209  ************************************************************************/
 210 #if defined(CFG_DRAM_TEST)
 211 int testdram(void)
 212 {
 213         unsigned long *mem = (unsigned long *) 0;
 214         const unsigned long kend = (1024 / sizeof(unsigned long));
 215         unsigned long k, n;
 216
 217         mtmsr(0);
 218
 219         for (k = 0; k < CFG_KBYTES_SDRAM;
 220              ++k, mem += (1024 / sizeof(unsigned long))) {
 221                 if ((k & 1023) == 0) {
 222                         printf("%3d MB\r", k / 1024);
 223                 }
 224
 225                 memset(mem, 0xaaaaaaaa, 1024);
 226                 for (n = 0; n < kend; ++n) {
 227                         if (mem[n] != 0xaaaaaaaa) {
 228                                 printf("SDRAM test fails at: %08x\n",
 229                                        (uint) & mem[n]);
 230                                 return 1;
 231                         }
 232                 }
 233
 234                 memset(mem, 0x55555555, 1024);
 235                 for (n = 0; n < kend; ++n) {
 236                         if (mem[n] != 0x55555555) {
 237                                 printf("SDRAM test fails at: %08x\n",
 238                                        (uint) & mem[n]);
 239                                 return 1;
 240                         }
 241                 }
 242         }
 243         printf("SDRAM test passes\n");
 244
 245         return  0;
 246 }
 247 #endif
 248
 249
 250 /*************************************************************************
 251  *  pci_pre_init
 252  *
 253  *  This routine is called just prior to registering the hose and gives
 254  *  the board the opportunity to check things. Returning a value of zero
 255  *  indicates that things are bad & PCI initialization should be aborted.
 256  *
 257  *      Different boards may wish to customize the pci controller structure
 258  *      (add regions, override default access routines, etc) or perform
 259  *      certain pre-initialization actions.
 260  *
 261  ************************************************************************/
 262 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
 263 int pci_pre_init( struct pci_controller *hose )
 264 {
 265         unsigned long strap;
 266
 267         /*--------------------------------------------------------------------------+
 268          *      The luan board is always configured as the host & requires the
 269          *      PCI arbiter to be enabled.
 270          *--------------------------------------------------------------------------*/
 271         mfsdr(sdr_sdstp1, strap);
 272         if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
 273                 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
 274
 275                 return  0;
 276         }
 277
 278         return  1;
 279 }
 280 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
 281
 282
 283 /*************************************************************************
 284  *  pci_target_init
 285  *
 286  *      The bootstrap configuration provides default settings for the pci
 287  *      inbound map (PIM). But the bootstrap config choices are limited and
 288  *      may not be sufficient for a given board.
 289  *
 290  ************************************************************************/
 291 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 292 void pci_target_init(struct pci_controller *hose)
 293 {
 294         DECLARE_GLOBAL_DATA_PTR;
 295
 296         /*--------------------------------------------------------------------------+
 297          * Disable everything
 298          *--------------------------------------------------------------------------*/
 299         out32r( PCIX0_PIM0SA, 0 ); /* disable */
 300         out32r( PCIX0_PIM1SA, 0 ); /* disable */
 301         out32r( PCIX0_PIM2SA, 0 ); /* disable */
 302         out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
 303
 304         /*--------------------------------------------------------------------------+
 305          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 306          * options to not support sizes such as 128/256 MB.
 307          *--------------------------------------------------------------------------*/
 308         out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
 309         out32r( PCIX0_PIM0LAH, 0 );
 310         out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 311
 312         out32r( PCIX0_BAR0, 0 );
 313
 314         /*--------------------------------------------------------------------------+
 315          * Program the board's subsystem id/vendor id
 316          *--------------------------------------------------------------------------*/
 317         out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
 318         out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
 319
 320         out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
 321 }
 322 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 323
 324
 325 /*************************************************************************
 326  *  is_pci_host
 327  *
 328  *      This routine is called to determine if a pci scan should be
 329  *      performed. With various hardware environments (especially cPCI and
 330  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 331  *      bit in the strap register, or generic host/adapter assumptions.
 332  *
 333  *      Rather than hard-code a bad assumption in the general 440 code, the
 334  *      440 pci code requires the board to decide at runtime.
 335  *
 336  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 337  *
 338  *
 339  ************************************************************************/
 340 #if defined(CONFIG_PCI)
 341 int is_pci_host(struct pci_controller *hose)
 342 {
 343         return  1;
 344 }
 345 #endif                          /* defined(CONFIG_PCI) */
 346
 347
 348 /*************************************************************************
 349  *  hw_watchdog_reset
 350  *
 351  *      This routine is called to reset (keep alive) the watchdog timer
 352  *
 353  ************************************************************************/
 354 #if defined(CONFIG_HW_WATCHDOG)
 355 void hw_watchdog_reset(void)
 356 {
 357 }
 358 #endif
 359
 360
 361 /*************************************************************************
 362  *  int on_off()
 363  *
 364  ************************************************************************/
 365 static int on_off( const char *s )
 366 {
 367         if (strcmp(s, "on") == 0) {
 368                 return  1;
 369         } else if (strcmp(s, "off") == 0) {
 370                 return  0;
 371         }
 372         return  -1;
 373 }
 374
 375
 376 /*************************************************************************
 377  *  void l2cache_disable()
 378  *
 379  ************************************************************************/
 380 static void l2cache_disable(void)
 381 {
 382         mtdcr( l2_cache_cfg, 0 );
 383 }
 384
 385
 386 /*************************************************************************
 387  *  void l2cache_enable()
 388  *
 389  ************************************************************************/
 390 static void l2cache_enable(void)        /* see p258 7.4.1 Enabling L2 Cache */
 391 {
 392         mtdcr( l2_cache_cfg, 0x80000000 );      /* enable L2_MODE L2_CFG[L2M] */
 393
 394         mtdcr( l2_cache_addr, 0 );              /* set L2_ADDR with all zeros */
 395
 396         mtdcr( l2_cache_cmd, 0x80000000 );      /* issue HCLEAR command via L2_CMD */
 397
 398         while (!(mfdcr( l2_cache_stat ) & 0x80000000 ))  ;; /* poll L2_SR for completion */
 399
 400         mtdcr( l2_cache_cmd, 0x10000000 );      /* clear cache errors L2_CMD[CCP] */
 401
 402         mtdcr( l2_cache_cmd, 0x08000000 );      /* clear tag errors L2_CMD[CTE] */
 403
 404         mtdcr( l2_cache_snp0, 0 );              /* snoop registers */
 405         mtdcr( l2_cache_snp1, 0 );
 406
 407         __asm__ volatile ("sync");              /* msync */
 408
 409         mtdcr( l2_cache_cfg, 0xe0000000 );      /* inst and data use L2 */
 410
 411         __asm__ volatile ("sync");
 412 }
 413
 414
 415 /*************************************************************************
 416  *  int l2cache_status()
 417  *
 418  ************************************************************************/
 419 static int l2cache_status(void)
 420 {
 421         return  (mfdcr( l2_cache_cfg ) & 0x60000000) != 0;
 422 }
 423
 424
 425 /*************************************************************************
 426  *  int do_l2cache()
 427  *
 428  ************************************************************************/
 429 int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
 430 {
 431         switch (argc) {
 432         case 2:                 /* on / off     */
 433                 switch (on_off(argv[1])) {
 434                 case 0: l2cache_disable();
 435                         break;
 436                 case 1: l2cache_enable();
 437                         break;
 438                 }
 439                 /* FALL TROUGH */
 440         case 1:                 /* get status */
 441                 printf ("L2 Cache is %s\n",
 442                         l2cache_status() ? "ON" : "OFF");
 443                 return 0;
 444         default:
 445                 printf ("Usage:\n%s\n", cmdtp->usage);
 446                 return 1;
 447         }
 448
 449         return  0;
 450 }
 451
 452
 453 U_BOOT_CMD(
 454         l2cache,   2,   1,     do_l2cache,
 455         "l2cache  - enable or disable L2 cache\n",
 456         "[on, off]\n"
 457         "    - enable or disable L2 cache\n"
 458         );