board/amcc/luan/luan.c

   1 /*
   2  * (C) Copyright 2005
   3  * John Otken, jotken@softadvances.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <command.h>
  26 #include <ppc4xx.h>
  27 #include <asm/processor.h>
  28 #include <asm/ppc4xx-isram.h>
  29 #include <spd_sdram.h>
  30 #include "epld.h"
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
  35
  36
  37 /*************************************************************************
  38  *  int board_early_init_f()
  39  *
  40  ************************************************************************/
  41 int board_early_init_f(void)
  42 {
  43         u32 mfr;
  44
  45         mtebc( PB0AP,  0x03800000 );    /* set chip selects */
  46         mtebc( PB0CR,  0xffc58000 );    /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
  47         mtebc( PB1AP,  0x03800000 );
  48         mtebc( PB1CR,  0xff018000 );    /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
  49         mtebc( PB2AP,  0x03800000 );
  50         mtebc( PB2CR,  0xff838000 );    /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
  51
  52         mtdcr( UIC1SR, 0xffffffff );    /* Clear all interrupts */
  53         mtdcr( UIC1ER, 0x00000000 );    /* disable all interrupts */
  54         mtdcr( UIC1CR, 0x00000000 );    /* Set Critical / Non Critical interrupts */
  55         mtdcr( UIC1PR, 0x7fff83ff );    /* Set Interrupt Polarities */
  56         mtdcr( UIC1TR, 0x001f8000 );    /* Set Interrupt Trigger Levels */
  57         mtdcr( UIC1VR, 0x00000001 );    /* Set Vect base=0,INT31 Highest priority */
  58         mtdcr( UIC1SR, 0x00000000 );    /* clear all interrupts */
  59         mtdcr( UIC1SR, 0xffffffff );
  60
  61         mtdcr( UIC0SR, 0xffffffff );    /* Clear all interrupts */
  62         mtdcr( UIC0ER, 0x00000000 );    /* disable all interrupts excepted cascade */
  63         mtdcr( UIC0CR, 0x00000001 );    /* Set Critical / Non Critical interrupts */
  64         mtdcr( UIC0PR, 0xffffffff );    /* Set Interrupt Polarities */
  65         mtdcr( UIC0TR, 0x01000004 );    /* Set Interrupt Trigger Levels */
  66         mtdcr( UIC0VR, 0x00000001 );    /* Set Vect base=0,INT31 Highest priority */
  67         mtdcr( UIC0SR, 0x00000000 );    /* clear all interrupts */
  68         mtdcr( UIC0SR, 0xffffffff );
  69
  70         mfsdr(SDR0_MFR, mfr);
  71         mfr |= SDR0_MFR_FIXD;           /* Workaround for PCI/DMA */
  72         mtsdr(SDR0_MFR, mfr);
  73
  74         return  0;
  75 }
  76
  77
  78 /*************************************************************************
  79  *  int misc_init_r()
  80  *
  81  ************************************************************************/
  82 int misc_init_r(void)
  83 {
  84         volatile epld_t *x = (epld_t *) CONFIG_SYS_EPLD_BASE;
  85
  86         /* set modes of operation */
  87         x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
  88                 EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE;
  89         /* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */
  90         x->ethuart &= ~EPLD2_ETH_AUTO_NEGO;
  91
  92         /* put Ethernet+PHY in reset */
  93         x->ethuart &= ~EPLD2_RESET_ETH_N;
  94         udelay(10000);
  95         /* take Ethernet+PHY out of reset */
  96         x->ethuart |= EPLD2_RESET_ETH_N;
  97
  98         return  0;
  99 }
 100
 101
 102 /*************************************************************************
 103  *  int checkboard()
 104  *
 105  ************************************************************************/
 106 int checkboard(void)
 107 {
 108         char *s = getenv("serial#");
 109
 110         printf("Board: Luan - AMCC PPC440SP Evaluation Board");
 111
 112         if (s != NULL) {
 113                 puts(", serial# ");
 114                 puts(s);
 115         }
 116         putc('\n');
 117
 118         return  0;
 119 }
 120
 121 /*
 122  * Override the default functions in arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c with
 123  * board specific values.
 124  */
 125 u32 ddr_clktr(u32 default_val) {
 126         return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
 127 }
 128
 129 /*************************************************************************
 130  *  hw_watchdog_reset
 131  *
 132  *      This routine is called to reset (keep alive) the watchdog timer
 133  *
 134  ************************************************************************/
 135 #if defined(CONFIG_HW_WATCHDOG)
 136 void hw_watchdog_reset(void)
 137 {
 138 }
 139 #endif
 140
 141
 142 /*************************************************************************
 143  *  int on_off()
 144  *
 145  ************************************************************************/
 146 static int on_off( const char *s )
 147 {
 148         if (strcmp(s, "on") == 0) {
 149                 return  1;
 150         } else if (strcmp(s, "off") == 0) {
 151                 return  0;
 152         }
 153         return  -1;
 154 }
 155
 156
 157 /*************************************************************************
 158  *  void l2cache_disable()
 159  *
 160  ************************************************************************/
 161 static void l2cache_disable(void)
 162 {
 163         mtdcr( L2_CACHE_CFG, 0 );
 164 }
 165
 166
 167 /*************************************************************************
 168  *  void l2cache_enable()
 169  *
 170  ************************************************************************/
 171 static void l2cache_enable(void)        /* see p258 7.4.1 Enabling L2 Cache */
 172 {
 173         mtdcr( L2_CACHE_CFG, 0x80000000 );      /* enable L2_MODE L2_CFG[L2M] */
 174
 175         mtdcr( L2_CACHE_ADDR, 0 );              /* set L2_ADDR with all zeros */
 176
 177         mtdcr( L2_CACHE_CMD, 0x80000000 );      /* issue HCLEAR command via L2_CMD */
 178
 179         while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 ))  ;; /* poll L2_SR for completion */
 180
 181         mtdcr( L2_CACHE_CMD, 0x10000000 );      /* clear cache errors L2_CMD[CCP] */
 182
 183         mtdcr( L2_CACHE_CMD, 0x08000000 );      /* clear tag errors L2_CMD[CTE] */
 184
 185         mtdcr( L2_CACHE_SNP0, 0 );              /* snoop registers */
 186         mtdcr( L2_CACHE_SNP1, 0 );
 187
 188         __asm__ volatile ("sync");              /* msync */
 189
 190         mtdcr( L2_CACHE_CFG, 0xe0000000 );      /* inst and data use L2 */
 191
 192         __asm__ volatile ("sync");
 193 }
 194
 195
 196 /*************************************************************************
 197  *  int l2cache_status()
 198  *
 199  ************************************************************************/
 200 static int l2cache_status(void)
 201 {
 202         return  (mfdcr( L2_CACHE_CFG ) & 0x60000000) != 0;
 203 }
 204
 205
 206 /*************************************************************************
 207  *  int do_l2cache()
 208  *
 209  ************************************************************************/
 210 int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
 211 {
 212         switch (argc) {
 213         case 2:                 /* on / off     */
 214                 switch (on_off(argv[1])) {
 215                 case 0: l2cache_disable();
 216                         break;
 217                 case 1: l2cache_enable();
 218                         break;
 219                 }
 220                 /* FALL TROUGH */
 221         case 1:                 /* get status */
 222                 printf ("L2 Cache is %s\n",
 223                         l2cache_status() ? "ON" : "OFF");
 224                 return 0;
 225         default:
 226                 cmd_usage(cmdtp);
 227                 return 1;
 228         }
 229
 230         return  0;
 231 }
 232
 233
 234 U_BOOT_CMD(
 235         l2cache,   2,   1,     do_l2cache,
 236         "enable or disable L2 cache",
 237         "[on, off]\n"
 238         "    - enable or disable L2 cache"
 239 );