board/amcc/ocotea/ocotea.c

   1 /*
   2  *  Copyright (C) 2004 PaulReynolds@lhsolutions.com
   3  *
   4  * (C) Copyright 2005
   5  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10
  11 #include <common.h>
  12 #include "ocotea.h"
  13 #include <asm/processor.h>
  14 #include <spd_sdram.h>
  15 #include <asm/ppc4xx-emac.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 #define BOOT_SMALL_FLASH        32      /* 00100000 */
  20 #define FLASH_ONBD_N            2       /* 00000010 */
  21 #define FLASH_SRAM_SEL          1       /* 00000001 */
  22
  23 long int fixed_sdram (void);
  24 void fpga_init (void);
  25
  26 int board_early_init_f (void)
  27 {
  28         unsigned long mfr;
  29         unsigned char *fpga_base = (unsigned char *) CONFIG_SYS_FPGA_BASE;
  30         unsigned char switch_status;
  31         unsigned long cs0_base;
  32         unsigned long cs0_size;
  33         unsigned long cs0_twt;
  34         unsigned long cs2_base;
  35         unsigned long cs2_size;
  36         unsigned long cs2_twt;
  37
  38         /*-------------------------------------------------------------------------+
  39           | Initialize EBC CONFIG
  40           +-------------------------------------------------------------------------*/
  41         mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
  42               EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
  43               EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
  44               EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
  45               EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
  46
  47         /*-------------------------------------------------------------------------+
  48           | FPGA. Initialize bank 7 with default values.
  49           +-------------------------------------------------------------------------*/
  50         mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
  51               EBC_BXAP_BCE_DISABLE|
  52               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
  53               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
  54               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
  55               EBC_BXAP_BEM_WRITEONLY|
  56               EBC_BXAP_PEN_DISABLED);
  57         mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)|
  58               EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
  59
  60         /* read FPGA base register FPGA_REG0 */
  61         switch_status = *fpga_base;
  62
  63         if (switch_status & 0x40) {
  64                 cs0_base = 0xFFE00000;
  65                 cs0_size = EBC_BXCR_BS_2MB;
  66                 cs0_twt = 8;
  67                 cs2_base = 0xFF800000;
  68                 cs2_size = EBC_BXCR_BS_4MB;
  69                 cs2_twt = 10;
  70         } else {
  71                 cs0_base = 0xFFC00000;
  72                 cs0_size = EBC_BXCR_BS_4MB;
  73                 cs0_twt = 10;
  74                 cs2_base = 0xFF800000;
  75                 cs2_size = EBC_BXCR_BS_2MB;
  76                 cs2_twt = 8;
  77         }
  78
  79         /*-------------------------------------------------------------------------+
  80           | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
  81           +-------------------------------------------------------------------------*/
  82         mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
  83               EBC_BXAP_BCE_DISABLE|
  84               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
  85               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
  86               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
  87               EBC_BXAP_BEM_WRITEONLY|
  88               EBC_BXAP_PEN_DISABLED);
  89         mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(cs0_base)|
  90               cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
  91
  92         /*-------------------------------------------------------------------------+
  93           | 8KB NVRAM/RTC. Initialize bank 1 with default values.
  94           +-------------------------------------------------------------------------*/
  95         mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
  96               EBC_BXAP_BCE_DISABLE|
  97               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
  98               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
  99               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
 100               EBC_BXAP_BEM_WRITEONLY|
 101               EBC_BXAP_PEN_DISABLED);
 102         mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000)|
 103               EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
 104
 105         /*-------------------------------------------------------------------------+
 106           | 4 MB FLASH. Initialize bank 2 with default values.
 107           +-------------------------------------------------------------------------*/
 108         mtebc(PB2AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
 109               EBC_BXAP_BCE_DISABLE|
 110               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
 111               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
 112               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
 113               EBC_BXAP_BEM_WRITEONLY|
 114               EBC_BXAP_PEN_DISABLED);
 115         mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(cs2_base)|
 116               cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
 117
 118         /*-------------------------------------------------------------------------+
 119           | FPGA. Initialize bank 7 with default values.
 120           +-------------------------------------------------------------------------*/
 121         mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
 122               EBC_BXAP_BCE_DISABLE|
 123               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
 124               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
 125               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
 126               EBC_BXAP_BEM_WRITEONLY|
 127               EBC_BXAP_PEN_DISABLED);
 128         mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)|
 129               EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
 130
 131         /*--------------------------------------------------------------------
 132          * Setup the interrupt controller polarities, triggers, etc.
 133          *-------------------------------------------------------------------*/
 134         /*
 135          * Because of the interrupt handling rework to handle 440GX interrupts
 136          * with the common code, we needed to change names of the UIC registers.
 137          * Here the new relationship:
 138          *
 139          * U-Boot name  440GX name
 140          * -----------------------
 141          * UIC0         UICB0
 142          * UIC1         UIC0
 143          * UIC2         UIC1
 144          * UIC3         UIC2
 145          */
 146         mtdcr (UIC1SR, 0xffffffff);     /* clear all */
 147         mtdcr (UIC1ER, 0x00000000);     /* disable all */
 148         mtdcr (UIC1CR, 0x00000009);     /* SMI & UIC1 crit are critical */
 149         mtdcr (UIC1PR, 0xfffffe13);     /* per ref-board manual */
 150         mtdcr (UIC1TR, 0x01c00008);     /* per ref-board manual */
 151         mtdcr (UIC1VR, 0x00000001);     /* int31 highest, base=0x000 */
 152         mtdcr (UIC1SR, 0xffffffff);     /* clear all */
 153
 154         mtdcr (UIC2SR, 0xffffffff);     /* clear all */
 155         mtdcr (UIC2ER, 0x00000000);     /* disable all */
 156         mtdcr (UIC2CR, 0x00000000);     /* all non-critical */
 157         mtdcr (UIC2PR, 0xffffe0ff);     /* per ref-board manual */
 158         mtdcr (UIC2TR, 0x00ffc000);     /* per ref-board manual */
 159         mtdcr (UIC2VR, 0x00000001);     /* int31 highest, base=0x000 */
 160         mtdcr (UIC2SR, 0xffffffff);     /* clear all */
 161
 162         mtdcr (UIC3SR, 0xffffffff);     /* clear all */
 163         mtdcr (UIC3ER, 0x00000000);     /* disable all */
 164         mtdcr (UIC3CR, 0x00000000);     /* all non-critical */
 165         mtdcr (UIC3PR, 0xffffffff);     /* per ref-board manual */
 166         mtdcr (UIC3TR, 0x00ff8c0f);     /* per ref-board manual */
 167         mtdcr (UIC3VR, 0x00000001);     /* int31 highest, base=0x000 */
 168         mtdcr (UIC3SR, 0xffffffff);     /* clear all */
 169
 170         mtdcr (UIC0SR, 0xfc000000); /* clear all */
 171         mtdcr (UIC0ER, 0x00000000); /* disable all */
 172         mtdcr (UIC0CR, 0x00000000); /* all non-critical */
 173         mtdcr (UIC0PR, 0xfc000000); /* */
 174         mtdcr (UIC0TR, 0x00000000); /* */
 175         mtdcr (UIC0VR, 0x00000001); /* */
 176         mfsdr (SDR0_MFR, mfr);
 177         mfr &= ~SDR0_MFR_ECS_MASK;
 178 /*      mtsdr(SDR0_MFR, mfr); */
 179         fpga_init();
 180
 181         return 0;
 182 }
 183
 184
 185 int checkboard (void)
 186 {
 187         char buf[64];
 188         int i = getenv_f("serial#", buf, sizeof(buf));
 189
 190         printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");
 191         if (i > 0) {
 192                 puts(", serial# ");
 193                 puts(buf);
 194         }
 195         putc ('\n');
 196
 197         return (0);
 198 }
 199
 200
 201 phys_size_t initdram (int board_type)
 202 {
 203         long dram_size = 0;
 204
 205 #if defined(CONFIG_SPD_EEPROM)
 206         dram_size = spd_sdram ();
 207 #else
 208         dram_size = fixed_sdram ();
 209 #endif
 210         return dram_size;
 211 }
 212
 213
 214 #if !defined(CONFIG_SPD_EEPROM)
 215 /*************************************************************************
 216  *  fixed sdram init -- doesn't use serial presence detect.
 217  *
 218  *  Assumes:    128 MB, non-ECC, non-registered
 219  *              PLB @ 133 MHz
 220  *
 221  ************************************************************************/
 222 long int fixed_sdram (void)
 223 {
 224         uint reg;
 225
 226         /*--------------------------------------------------------------------
 227          * Setup some default
 228          *------------------------------------------------------------------*/
 229         mtsdram (SDRAM0_UABBA, 0x00000000);     /* ubba=0 (default)             */
 230         mtsdram (SDRAM0_SLIO, 0x00000000);              /* rdre=0 wrre=0 rarw=0         */
 231         mtsdram (SDRAM0_DEVOPT, 0x00000000);    /* dll=0 ds=0 (normal)          */
 232         mtsdram (SDRAM0_WDDCTR, 0x00000000);    /* wrcp=0 dcd=0                 */
 233         mtsdram (SDRAM0_CLKTR, 0x40000000);     /* clkp=1 (90 deg wr) dcdt=0    */
 234
 235         /*--------------------------------------------------------------------
 236          * Setup for board-specific specific mem
 237          *------------------------------------------------------------------*/
 238         /*
 239          * Following for CAS Latency = 2.5 @ 133 MHz PLB
 240          */
 241         mtsdram (SDRAM0_B0CR, 0x000a4001);      /* SDBA=0x000 128MB, Mode 3, enabled */
 242         mtsdram (SDRAM0_TR0, 0x410a4012);       /* WR=2  WD=1 CL=2.5 PA=3 CP=4 LD=2 */
 243         /* RA=10 RD=3                       */
 244         mtsdram (SDRAM0_TR1, 0x8080082f);       /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
 245         mtsdram (SDRAM0_RTR, 0x08200000);       /* Rate 15.625 ns @ 133 MHz PLB     */
 246         mtsdram (SDRAM0_CFG1, 0x00000000);      /* Self-refresh exit, disable PM    */
 247         udelay (400);                   /* Delay 200 usecs (min)            */
 248
 249         /*--------------------------------------------------------------------
 250          * Enable the controller, then wait for DCEN to complete
 251          *------------------------------------------------------------------*/
 252         mtsdram (SDRAM0_CFG0, 0x86000000);      /* DCEN=1, PMUD=1, 64-bit           */
 253         for (;;) {
 254                 mfsdram (SDRAM0_MCSTS, reg);
 255                 if (reg & 0x80000000)
 256                         break;
 257         }
 258
 259         return (128 * 1024 * 1024);     /* 128 MB                           */
 260 }
 261 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 262
 263 void fpga_init(void)
 264 {
 265         unsigned long group;
 266         unsigned long sdr0_pfc0;
 267         unsigned long sdr0_pfc1;
 268         unsigned long sdr0_cust0;
 269         unsigned long pvr;
 270
 271         mfsdr (SDR0_PFC0, sdr0_pfc0);
 272         mfsdr (SDR0_PFC1, sdr0_pfc1);
 273         group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
 274         pvr = get_pvr ();
 275
 276         sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE;
 277         if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) {
 278                 sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE;
 279                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
 280                 out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
 281                      FPGA_REG2_EXT_INTFACE_ENABLE);
 282                 mtsdr (SDR0_PFC0, sdr0_pfc0);
 283                 mtsdr (SDR0_PFC1, sdr0_pfc1);
 284         } else {
 285                 sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
 286                 switch (group)
 287                 {
 288                 case 0:
 289                 case 1:
 290                 case 2:
 291                         /* CPU trace A */
 292                         out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
 293                              FPGA_REG2_EXT_INTFACE_ENABLE);
 294                         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
 295                         mtsdr (SDR0_PFC0, sdr0_pfc0);
 296                         mtsdr (SDR0_PFC1, sdr0_pfc1);
 297                         break;
 298                 case 3:
 299                 case 4:
 300                 case 5:
 301                 case 6:
 302                         /* CPU trace B - Over EBMI */
 303                         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
 304                         mtsdr (SDR0_PFC0, sdr0_pfc0);
 305                         mtsdr (SDR0_PFC1, sdr0_pfc1);
 306                         out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
 307                              FPGA_REG2_EXT_INTFACE_DISABLE);
 308                         break;
 309                 }
 310         }
 311
 312         /* Initialize the ethernet specific functions in the fpga */
 313         mfsdr(SDR0_PFC1, sdr0_pfc1);
 314         mfsdr(SDR0_CUST0, sdr0_cust0);
 315         if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
 316             ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
 317              (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
 318         {
 319                 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
 320                 {
 321                         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
 322                              FPGA_REG3_ENET_GROUP7);
 323                 }
 324                 else
 325                 {
 326                         if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
 327                         {
 328                                 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
 329                                      FPGA_REG3_ENET_GROUP7);
 330                         }
 331                         else
 332                         {
 333                                 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
 334                                      FPGA_REG3_ENET_GROUP8);
 335                         }
 336                 }
 337         }
 338         else
 339         {
 340                 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
 341                 {
 342                         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
 343                              FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
 344                 }
 345                 else
 346                 {
 347                         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
 348                              FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
 349                 }
 350         }
 351         out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 |
 352              FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 |
 353              FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS);
 354
 355         /* reset the gigabyte phy if necessary */
 356         if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
 357         {
 358                 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
 359                 {
 360                         out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
 361                         udelay(10000);
 362                         out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE);
 363                 }
 364                 else
 365                 {
 366                         out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
 367                         udelay(10000);
 368                         out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE);
 369                 }
 370         }
 371
 372         /*
 373          * new Ocotea with Rev. F (pass 3) chips has SMII PHY reset
 374          */
 375         if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) {
 376                 out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE);
 377                 udelay(10000);
 378                 out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE);
 379         }
 380
 381         /* Turn off the LED's */
 382         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
 383              FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
 384              FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB);
 385
 386         return;
 387 }