board/amcc/sequoia/init.S

   1 /*
   2  * (C) Copyright 2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <ppc_asm.tmpl>
  25 #include <asm-ppc/mmu.h>
  26 #include <config.h>
  27
  28 /*
  29  * TLB TABLE
  30  *
  31  * This table is used by the cpu boot code to setup the initial tlb
  32  * entries. Rather than make broad assumptions in the cpu source tree,
  33  * this table lets each board set things up however they like.
  34  *
  35  *  Pointer to the table is returned in r1
  36  */
  37     .section .bootpg,"ax"
  38     .globl tlbtab
  39
  40 tlbtab:
  41         tlbtab_start
  42
  43         /* vxWorks needs this as first entry for the Machine Check interrupt */
  44         tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
  45
  46         /* TLB-entry for DDR SDRAM (Up to 2GB) */
  47 #ifdef CONFIG_4xx_DCACHE
  48         tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
  49 #else
  50         tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
  51 #endif
  52
  53         /* TLB-entry for EBC */
  54         tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
  55
  56         /* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the
  57          * speed up boot process. It is patched after relocation to enable SA_I
  58          */
  59 #ifndef CONFIG_NAND_SPL
  60         tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
  61 #else
  62         tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
  63 #endif
  64
  65 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
  66         /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
  67         tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
  68 #endif
  69
  70         /* TLB-entry for PCI Memory */
  71         tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
  72         tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
  73         tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
  74         tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
  75
  76         /* TLB-entry for NAND */
  77         tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
  78
  79         /* TLB-entry for Internal Registers & OCM */
  80         tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_R|AC_W|AC_X|SA_I )
  81
  82         /*TLB-entry PCI registers*/
  83         tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_R|AC_W|AC_X|SA_G|SA_I )
  84
  85         /* TLB-entry for peripherals */
  86         tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
  87
  88         /* TLB-entry PCI IO Space - from sr@denx.de */
  89         tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
  90
  91         tlbtab_end
  92
  93 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  94         /*
  95          * For NAND booting the first TLB has to be reconfigured to full size
  96          * and with caching disabled after running from RAM!
  97          */
  98 #define TLB00   TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
  99 #define TLB01   TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
 100 #define TLB02   TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
 101
 102         .globl  reconfig_tlb0
 103 reconfig_tlb0:
 104         sync
 105         isync
 106         addi    r4,r0,0x0000            /* TLB entry #0 */
 107         lis     r5,TLB00@h
 108         ori     r5,r5,TLB00@l
 109         tlbwe   r5,r4,0x0000            /* Save it out */
 110         lis     r5,TLB01@h
 111         ori     r5,r5,TLB01@l
 112         tlbwe   r5,r4,0x0001            /* Save it out */
 113         lis     r5,TLB02@h
 114         ori     r5,r5,TLB02@l
 115         tlbwe   r5,r4,0x0002            /* Save it out */
 116         sync
 117         isync
 118         blr
 119 #endif