]>
git.ipfire.org Git - people/ms/u-boot.git/blob - board/amcc/sequoia/sdram.c
b5c7d6d50634069cda4c19513be22e3f565126a9
3 * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
4 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
5 * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
6 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
7 * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
9 * (C) Copyright 2006-2007
10 * Stefan Roese, DENX Software Engineering, sr@denx.de.
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 /* define DEBUG for debug output */
32 #include <asm/processor.h>
36 /*-----------------------------------------------------------------------------+
38 *-----------------------------------------------------------------------------*/
39 extern int denali_wait_for_dlllock(void);
40 extern void denali_core_search_data_eye(void);
42 #if defined(CONFIG_NAND_SPL)
43 /* Using arch/ppc/cpu/ppc4xx/speed.c to calculate the bus frequency is too big
44 * for the 4k NAND boot image so define bus_frequency to 133MHz here
45 * which is save for the refresh counter setup.
47 #define get_bus_freq(val) 133333333
50 /*************************************************************************
52 * initdram -- 440EPx's DDR controller is a DENALI Core
54 ************************************************************************/
55 phys_size_t
initdram (int board_type
)
57 #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)) || \
58 defined(CONFIG_NAND_SPL)
59 ulong speed
= get_bus_freq(0);
61 mtsdram(DDR0_02
, 0x00000000);
63 mtsdram(DDR0_00
, 0x0000190A);
64 mtsdram(DDR0_01
, 0x01000000);
65 mtsdram(DDR0_03
, 0x02030602);
66 mtsdram(DDR0_04
, 0x0A020200);
67 mtsdram(DDR0_05
, 0x02020308);
68 mtsdram(DDR0_06
, 0x0102C812);
69 mtsdram(DDR0_07
, 0x000D0100);
70 mtsdram(DDR0_08
, 0x02430001);
71 mtsdram(DDR0_09
, 0x00011D5F);
72 mtsdram(DDR0_10
, 0x00000100);
73 mtsdram(DDR0_11
, 0x0027C800);
74 mtsdram(DDR0_12
, 0x00000003);
75 mtsdram(DDR0_14
, 0x00000000);
76 mtsdram(DDR0_17
, 0x19000000);
77 mtsdram(DDR0_18
, 0x19191919);
78 mtsdram(DDR0_19
, 0x19191919);
79 mtsdram(DDR0_20
, 0x0B0B0B0B);
80 mtsdram(DDR0_21
, 0x0B0B0B0B);
81 mtsdram(DDR0_22
, 0x00267F0B);
82 mtsdram(DDR0_23
, 0x00000000);
83 mtsdram(DDR0_24
, 0x01010002);
84 if (speed
> 133333334)
85 mtsdram(DDR0_26
, 0x5B26050C);
87 mtsdram(DDR0_26
, 0x5B260408);
88 mtsdram(DDR0_27
, 0x0000682B);
89 mtsdram(DDR0_28
, 0x00000000);
90 mtsdram(DDR0_31
, 0x00000000);
91 mtsdram(DDR0_42
, 0x01000006);
92 mtsdram(DDR0_43
, 0x030A0200);
93 mtsdram(DDR0_44
, 0x00000003);
94 mtsdram(DDR0_02
, 0x00000001);
96 denali_wait_for_dlllock();
97 #endif /* #ifndef CONFIG_NAND_U_BOOT */
99 #ifdef CONFIG_DDR_DATA_EYE
100 /* -----------------------------------------------------------+
101 * Perform data eye search if requested.
102 * ----------------------------------------------------------*/
103 denali_core_search_data_eye();
107 * Clear possible errors resulting from data-eye-search.
108 * If not done, then we could get an interrupt later on when
109 * exceptions are enabled.
111 set_mcsr(get_mcsr());
113 return (CONFIG_SYS_MBYTES_SDRAM
<< 20);