board/amcc/sequoia/sdram.c

   1 /*
   2  * (C) Copyright 2006
   3  * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
   4  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   5  * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
   6  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   7  * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
   8  *
   9  * (C) Copyright 2006-2007
  10  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14
  15 /* define DEBUG for debug output */
  16 #undef DEBUG
  17
  18 #include <common.h>
  19 #include <asm/processor.h>
  20 #include <asm/io.h>
  21 #include <asm/ppc440.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 /*-----------------------------------------------------------------------------+
  26  * Prototypes
  27  *-----------------------------------------------------------------------------*/
  28 extern int denali_wait_for_dlllock(void);
  29 extern void denali_core_search_data_eye(void);
  30
  31 /*************************************************************************
  32  *
  33  * dram_init -- 440EPx's DDR controller is a DENALI Core
  34  *
  35  ************************************************************************/
  36 int dram_init(void)
  37 {
  38 #if !defined(CONFIG_SYS_RAMBOOT)
  39         ulong speed = get_bus_freq(0);
  40
  41         mtsdram(DDR0_02, 0x00000000);
  42
  43         mtsdram(DDR0_00, 0x0000190A);
  44         mtsdram(DDR0_01, 0x01000000);
  45         mtsdram(DDR0_03, 0x02030602);
  46         mtsdram(DDR0_04, 0x0A020200);
  47         mtsdram(DDR0_05, 0x02020308);
  48         mtsdram(DDR0_06, 0x0102C812);
  49         mtsdram(DDR0_07, 0x000D0100);
  50         mtsdram(DDR0_08, 0x02430001);
  51         mtsdram(DDR0_09, 0x00011D5F);
  52         mtsdram(DDR0_10, 0x00000100);
  53         mtsdram(DDR0_11, 0x0027C800);
  54         mtsdram(DDR0_12, 0x00000003);
  55         mtsdram(DDR0_14, 0x00000000);
  56         mtsdram(DDR0_17, 0x19000000);
  57         mtsdram(DDR0_18, 0x19191919);
  58         mtsdram(DDR0_19, 0x19191919);
  59         mtsdram(DDR0_20, 0x0B0B0B0B);
  60         mtsdram(DDR0_21, 0x0B0B0B0B);
  61         mtsdram(DDR0_22, 0x00267F0B);
  62         mtsdram(DDR0_23, 0x00000000);
  63         mtsdram(DDR0_24, 0x01010002);
  64         if (speed > 133333334)
  65                 mtsdram(DDR0_26, 0x5B26050C);
  66         else
  67                 mtsdram(DDR0_26, 0x5B260408);
  68         mtsdram(DDR0_27, 0x0000682B);
  69         mtsdram(DDR0_28, 0x00000000);
  70         mtsdram(DDR0_31, 0x00000000);
  71         mtsdram(DDR0_42, 0x01000006);
  72         mtsdram(DDR0_43, 0x030A0200);
  73         mtsdram(DDR0_44, 0x00000003);
  74         mtsdram(DDR0_02, 0x00000001);
  75
  76         denali_wait_for_dlllock();
  77 #endif /* #ifndef CONFIG_SYS_RAMBOOT */
  78
  79 #ifdef CONFIG_DDR_DATA_EYE
  80         /* -----------------------------------------------------------+
  81          * Perform data eye search if requested.
  82          * ----------------------------------------------------------*/
  83         denali_core_search_data_eye();
  84 #endif
  85
  86         /*
  87          * Clear possible errors resulting from data-eye-search.
  88          * If not done, then we could get an interrupt later on when
  89          * exceptions are enabled.
  90          */
  91         set_mcsr(get_mcsr());
  92
  93         gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20;
  94
  95         return 0;
  96 }