board/amcc/yellowstone/yellowstone.c

   1 /*
   2  *
   3  * See file CREDITS for list of people who contributed to this
   4  * project.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include <common.h>
  23 #include <ppc4xx.h>
  24 #include <asm/processor.h>
  25 #include <spd_sdram.h>
  26
  27 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips    */
  28
  29 int board_early_init_f(void)
  30 {
  31         register uint reg;
  32
  33         /*--------------------------------------------------------------------
  34          * Setup the external bus controller/chip selects
  35          *-------------------------------------------------------------------*/
  36         mtdcr(ebccfga, xbcfg);
  37         reg = mfdcr(ebccfgd);
  38         mtdcr(ebccfgd, reg | 0x04000000);       /* Set ATC */
  39
  40         mtebc(pb0ap, 0x03017300);       /* FLASH/SRAM */
  41         mtebc(pb0cr, 0xfc0da000);       /* BAS=0xfc0 64MB r/w 16-bit */
  42
  43         mtebc(pb1ap, 0x00000000);
  44         mtebc(pb1cr, 0x00000000);
  45
  46         mtebc(pb2ap, 0x04814500);
  47         /*CPLD*/ mtebc(pb2cr, 0x80018000);      /*BAS=0x800 1MB r/w 8-bit */
  48
  49         mtebc(pb3ap, 0x00000000);
  50         mtebc(pb3cr, 0x00000000);
  51
  52         mtebc(pb4ap, 0x00000000);
  53         mtebc(pb4cr, 0x00000000);
  54
  55         mtebc(pb5ap, 0x00000000);
  56         mtebc(pb5cr, 0x00000000);
  57
  58         /*--------------------------------------------------------------------
  59          * Setup the GPIO pins
  60          *-------------------------------------------------------------------*/
  61         /*CPLD cs */
  62         /*setup Address lines for flash size 64Meg. */
  63         out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
  64         out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
  65         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
  66
  67         /*setup emac */
  68         out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
  69         out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
  70         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
  71         out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
  72         out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
  73
  74         /*UART1 */
  75         out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
  76         out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
  77         out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
  78
  79         /* external interrupts IRQ0...3 */
  80         out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000);
  81         out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
  82         out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
  83
  84 #if 0 /* test-only */
  85         /*setup USB 2.0 */
  86         out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
  87         out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
  88         out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
  89         out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
  90         out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
  91 #endif
  92
  93         /*--------------------------------------------------------------------
  94          * Setup the interrupt controller polarities, triggers, etc.
  95          *-------------------------------------------------------------------*/
  96         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  97         mtdcr(uic0er, 0x00000000);      /* disable all */
  98         mtdcr(uic0cr, 0x00000009);      /* ATI & UIC1 crit are critical */
  99         mtdcr(uic0pr, 0xfffffe13);      /* per ref-board manual */
 100         mtdcr(uic0tr, 0x01c00008);      /* per ref-board manual */
 101         mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
 102         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 103
 104         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 105         mtdcr(uic1er, 0x00000000);      /* disable all */
 106         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
 107         mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
 108         mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
 109         mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
 110         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 111
 112         /*--------------------------------------------------------------------
 113          * Setup other serial configuration
 114          *-------------------------------------------------------------------*/
 115         mfsdr(sdr_pci0, reg);
 116         mtsdr(sdr_pci0, 0x80000000 | reg);      /* PCI arbiter enabled */
 117         mtsdr(sdr_pfc0, 0x00003e00);    /* Pin function */
 118         mtsdr(sdr_pfc1, 0x00048000);    /* Pin function: UART0 has 4 pins */
 119
 120         /*clear tmrclk divisor */
 121         *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
 122
 123         /*enable ethernet */
 124         *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
 125
 126 #if 0 /* test-only */
 127         /*enable usb 1.1 fs device and remove usb 2.0 reset */
 128         *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
 129 #endif
 130
 131         /*get rid of flash write protect */
 132         *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
 133
 134         return 0;
 135 }
 136
 137 int misc_init_r (void)
 138 {
 139         DECLARE_GLOBAL_DATA_PTR;
 140         uint pbcr;
 141         int size_val = 0;
 142
 143         /* Re-do sizing to get full correct info */
 144         mtdcr(ebccfga, pb0cr);
 145         pbcr = mfdcr(ebccfgd);
 146         switch (gd->bd->bi_flashsize) {
 147         case 1 << 20:
 148                 size_val = 0;
 149                 break;
 150         case 2 << 20:
 151                 size_val = 1;
 152                 break;
 153         case 4 << 20:
 154                 size_val = 2;
 155                 break;
 156         case 8 << 20:
 157                 size_val = 3;
 158                 break;
 159         case 16 << 20:
 160                 size_val = 4;
 161                 break;
 162         case 32 << 20:
 163                 size_val = 5;
 164                 break;
 165         case 64 << 20:
 166                 size_val = 6;
 167                 break;
 168         case 128 << 20:
 169                 size_val = 7;
 170                 break;
 171         }
 172         pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 173         mtdcr(ebccfga, pb0cr);
 174         mtdcr(ebccfgd, pbcr);
 175
 176         /* adjust flash start and offset */
 177         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 178         gd->bd->bi_flashoffset = 0;
 179
 180         /* Monitor protection ON by default */
 181         (void)flash_protect(FLAG_PROTECT_SET,
 182                             -CFG_MONITOR_LEN,
 183                             0xffffffff,
 184                             &flash_info[0]);
 185
 186         return 0;
 187 }
 188
 189 int checkboard(void)
 190 {
 191         char *s = getenv("serial#");
 192
 193         printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
 194         if (s != NULL) {
 195                 puts(", serial# ");
 196                 puts(s);
 197         }
 198         putc('\n');
 199
 200         return (0);
 201 }
 202
 203 /*************************************************************************
 204  *  sdram_init -- doesn't use serial presence detect.
 205  *
 206  *  Assumes:    256 MB, ECC, non-registered
 207  *              PLB @ 133 MHz
 208  *
 209  ************************************************************************/
 210 #define NUM_TRIES 64
 211 #define NUM_READS 10
 212
 213 void sdram_tr1_set(int ram_address, int* tr1_value)
 214 {
 215         int i;
 216         int j, k;
 217         volatile unsigned int* ram_pointer =  (unsigned int*)ram_address;
 218         int first_good = -1, last_bad = 0x1ff;
 219
 220         unsigned long test[NUM_TRIES] = {
 221                 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 222                 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 223                 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 224                 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 225                 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 226                 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 227                 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 228                 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 229                 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 230                 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 231                 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 232                 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 233                 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 234                 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 235                 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
 236                 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
 237
 238         /* go through all possible SDRAM0_TR1[RDCT] values */
 239         for (i=0; i<=0x1ff; i++) {
 240                 /* set the current value for TR1 */
 241                 mtsdram(mem_tr1, (0x80800800 | i));
 242
 243                 /* write values */
 244                 for (j=0; j<NUM_TRIES; j++) {
 245                         ram_pointer[j] = test[j];
 246
 247                         /* clear any cache at ram location */
 248                         __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
 249                 }
 250
 251                 /* read values back */
 252                 for (j=0; j<NUM_TRIES; j++) {
 253                         for (k=0; k<NUM_READS; k++) {
 254                                 /* clear any cache at ram location */
 255                                 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
 256
 257                                 if (ram_pointer[j] != test[j])
 258                                         break;
 259                         }
 260
 261                         /* read error */
 262                         if (k != NUM_READS) {
 263                                 break;
 264                         }
 265                 }
 266
 267                 /* we have a SDRAM0_TR1[RDCT] that is part of the window */
 268                 if (j == NUM_TRIES) {
 269                         if (first_good == -1)
 270                                 first_good = i;         /* found beginning of window */
 271                 } else { /* bad read */
 272                         /* if we have not had a good read then don't care */
 273                         if(first_good != -1) {
 274                                 /* first failure after a good read */
 275                                 last_bad = i-1;
 276                                 break;
 277                         }
 278                 }
 279         }
 280
 281         /* return the current value for TR1 */
 282         *tr1_value = (first_good + last_bad) / 2;
 283 }
 284
 285 void sdram_init(void)
 286 {
 287         register uint reg;
 288         int tr1_bank1, tr1_bank2;
 289
 290         /*--------------------------------------------------------------------
 291          * Setup some default
 292          *------------------------------------------------------------------*/
 293         mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default)             */
 294         mtsdram(mem_slio, 0x00000000);  /* rdre=0 wrre=0 rarw=0         */
 295         mtsdram(mem_devopt, 0x00000000);        /* dll=0 ds=0 (normal)          */
 296         mtsdram(mem_clktr, 0x40000000); /* ?? */
 297         mtsdram(mem_wddctr, 0x40000000);        /* ?? */
 298
 299         /*clear this first, if the DDR is enabled by a debugger
 300           then you can not make changes. */
 301         mtsdram(mem_cfg0, 0x00000000);  /* Disable EEC */
 302
 303         /*--------------------------------------------------------------------
 304          * Setup for board-specific specific mem
 305          *------------------------------------------------------------------*/
 306         /*
 307          * Following for CAS Latency = 2.5 @ 133 MHz PLB
 308          */
 309         mtsdram(mem_b0cr, 0x000a4001);  /* SDBA=0x000 128MB, Mode 3, enabled */
 310         mtsdram(mem_b1cr, 0x080a4001);  /* SDBA=0x080 128MB, Mode 3, enabled */
 311
 312         mtsdram(mem_tr0, 0x410a4012);   /* ?? */
 313         mtsdram(mem_rtr, 0x04080000);   /* ?? */
 314         mtsdram(mem_cfg1, 0x00000000);  /* Self-refresh exit, disable PM    */
 315         mtsdram(mem_cfg0, 0x34000000);  /* Disable EEC */
 316         udelay(400);            /* Delay 200 usecs (min)            */
 317
 318         /*--------------------------------------------------------------------
 319          * Enable the controller, then wait for DCEN to complete
 320          *------------------------------------------------------------------*/
 321         mtsdram(mem_cfg0, 0x84000000);  /* Enable */
 322
 323         for (;;) {
 324                 mfsdram(mem_mcsts, reg);
 325                 if (reg & 0x80000000)
 326                         break;
 327         }
 328
 329         sdram_tr1_set(0x00000000, &tr1_bank1);
 330         sdram_tr1_set(0x08000000, &tr1_bank2);
 331         mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
 332 }
 333
 334 /*************************************************************************
 335  *  long int initdram
 336  *
 337  ************************************************************************/
 338 long int initdram(int board)
 339 {
 340         sdram_init();
 341         return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024);     /* return bytes */
 342 }
 343
 344 #if defined(CFG_DRAM_TEST)
 345 int testdram(void)
 346 {
 347         unsigned long *mem = (unsigned long *)0;
 348         const unsigned long kend = (1024 / sizeof(unsigned long));
 349         unsigned long k, n;
 350
 351         mtmsr(0);
 352
 353         for (k = 0; k < CFG_KBYTES_SDRAM;
 354              ++k, mem += (1024 / sizeof(unsigned long))) {
 355                 if ((k & 1023) == 0) {
 356                         printf("%3d MB\r", k / 1024);
 357                 }
 358
 359                 memset(mem, 0xaaaaaaaa, 1024);
 360                 for (n = 0; n < kend; ++n) {
 361                         if (mem[n] != 0xaaaaaaaa) {
 362                                 printf("SDRAM test fails at: %08x\n",
 363                                        (uint) & mem[n]);
 364                                 return 1;
 365                         }
 366                 }
 367
 368                 memset(mem, 0x55555555, 1024);
 369                 for (n = 0; n < kend; ++n) {
 370                         if (mem[n] != 0x55555555) {
 371                                 printf("SDRAM test fails at: %08x\n",
 372                                        (uint) & mem[n]);
 373                                 return 1;
 374                         }
 375                 }
 376         }
 377         printf("SDRAM test passes\n");
 378         return 0;
 379 }
 380 #endif
 381
 382 /*************************************************************************
 383  *  pci_pre_init
 384  *
 385  *  This routine is called just prior to registering the hose and gives
 386  *  the board the opportunity to check things. Returning a value of zero
 387  *  indicates that things are bad & PCI initialization should be aborted.
 388  *
 389  *      Different boards may wish to customize the pci controller structure
 390  *      (add regions, override default access routines, etc) or perform
 391  *      certain pre-initialization actions.
 392  *
 393  ************************************************************************/
 394 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
 395 int pci_pre_init(struct pci_controller *hose)
 396 {
 397         unsigned long addr;
 398
 399         /*-------------------------------------------------------------------------+
 400           | Set priority for all PLB3 devices to 0.
 401           | Set PLB3 arbiter to fair mode.
 402           +-------------------------------------------------------------------------*/
 403         mfsdr(sdr_amp1, addr);
 404         mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
 405         addr = mfdcr(plb3_acr);
 406         mtdcr(plb3_acr, addr | 0x80000000);
 407
 408         /*-------------------------------------------------------------------------+
 409           | Set priority for all PLB4 devices to 0.
 410           +-------------------------------------------------------------------------*/
 411         mfsdr(sdr_amp0, addr);
 412         mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
 413         addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
 414         mtdcr(plb4_acr, addr);
 415
 416         /*-------------------------------------------------------------------------+
 417           | Set Nebula PLB4 arbiter to fair mode.
 418           +-------------------------------------------------------------------------*/
 419         /* Segment0 */
 420         addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
 421         addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
 422         addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
 423         addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
 424         mtdcr(plb0_acr, addr);
 425
 426         /* Segment1 */
 427         addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
 428         addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
 429         addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
 430         addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
 431         mtdcr(plb1_acr, addr);
 432
 433         return 1;
 434 }
 435 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
 436
 437 /*************************************************************************
 438  *  pci_target_init
 439  *
 440  *      The bootstrap configuration provides default settings for the pci
 441  *      inbound map (PIM). But the bootstrap config choices are limited and
 442  *      may not be sufficient for a given board.
 443  *
 444  ************************************************************************/
 445 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 446 void pci_target_init(struct pci_controller *hose)
 447 {
 448         /*--------------------------------------------------------------------------+
 449          * Set up Direct MMIO registers
 450          *--------------------------------------------------------------------------*/
 451         /*--------------------------------------------------------------------------+
 452           | PowerPC440 EP PCI Master configuration.
 453           | Map one 1Gig range of PLB/processor addresses to PCI memory space.
 454           |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
 455           |   Use byte reversed out routines to handle endianess.
 456           | Make this region non-prefetchable.
 457           +--------------------------------------------------------------------------*/
 458         out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 459         out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
 460         out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);       /* PMM0 PCI Low Address */
 461         out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 462         out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 463
 464         out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 465         out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
 466         out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);      /* PMM0 PCI Low Address */
 467         out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 468         out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 469
 470         out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
 471         out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
 472         out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
 473         out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
 474
 475         /*--------------------------------------------------------------------------+
 476          * Set up Configuration registers
 477          *--------------------------------------------------------------------------*/
 478
 479         /* Program the board's subsystem id/vendor id */
 480         pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 481                               CFG_PCI_SUBSYS_VENDORID);
 482         pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
 483
 484         /* Configure command register as bus master */
 485         pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
 486
 487         /* 240nS PCI clock */
 488         pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
 489
 490         /* No error reporting */
 491         pci_write_config_word(0, PCI_ERREN, 0);
 492
 493         pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 494
 495 }
 496 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 497
 498 /*************************************************************************
 499  *  pci_master_init
 500  *
 501  ************************************************************************/
 502 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 503 void pci_master_init(struct pci_controller *hose)
 504 {
 505         unsigned short temp_short;
 506
 507         /*--------------------------------------------------------------------------+
 508           | Write the PowerPC440 EP PCI Configuration regs.
 509           |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 510           |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
 511           +--------------------------------------------------------------------------*/
 512         pci_read_config_word(0, PCI_COMMAND, &temp_short);
 513         pci_write_config_word(0, PCI_COMMAND,
 514                               temp_short | PCI_COMMAND_MASTER |
 515                               PCI_COMMAND_MEMORY);
 516 }
 517 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 518
 519 /*************************************************************************
 520  *  is_pci_host
 521  *
 522  *      This routine is called to determine if a pci scan should be
 523  *      performed. With various hardware environments (especially cPCI and
 524  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 525  *      bit in the strap register, or generic host/adapter assumptions.
 526  *
 527  *      Rather than hard-code a bad assumption in the general 440 code, the
 528  *      440 pci code requires the board to decide at runtime.
 529  *
 530  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 531  *
 532  *
 533  ************************************************************************/
 534 #if defined(CONFIG_PCI)
 535 int is_pci_host(struct pci_controller *hose)
 536 {
 537         /* Bamboo is always configured as host. */
 538         return (1);
 539 }
 540 #endif                          /* defined(CONFIG_PCI) */
 541
 542 /*************************************************************************
 543  *  hw_watchdog_reset
 544  *
 545  *      This routine is called to reset (keep alive) the watchdog timer
 546  *
 547  ************************************************************************/
 548 #if defined(CONFIG_HW_WATCHDOG)
 549 void hw_watchdog_reset(void)
 550 {
 551
 552 }
 553 #endif