board/amcc/yellowstone/yellowstone.c

   1 /*
   2  *
   3  * See file CREDITS for list of people who contributed to this
   4  * project.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include <common.h>
  23 #include <asm/processor.h>
  24 #include <spd_sdram.h>
  25
  26 int board_early_init_f(void)
  27 {
  28         register uint reg;
  29
  30         /*--------------------------------------------------------------------
  31          * Setup the external bus controller/chip selects
  32          *-------------------------------------------------------------------*/
  33         mtdcr(ebccfga, xbcfg);
  34         reg = mfdcr(ebccfgd);
  35         mtdcr(ebccfgd, reg | 0x04000000);       /* Set ATC */
  36
  37         mtebc(pb0ap, 0x03017300);       /* FLASH/SRAM */
  38         mtebc(pb0cr, 0xfe0ba000);       /* BAS=0xfe0 32MB r/w 16-bit */
  39
  40         mtebc(pb1ap, 0x00000000);
  41         mtebc(pb1cr, 0x00000000);
  42
  43         mtebc(pb2ap, 0x04814500);
  44         /*CPLD*/ mtebc(pb2cr, 0x80018000);      /*BAS=0x800 1MB r/w 8-bit */
  45
  46         mtebc(pb3ap, 0x00000000);
  47         mtebc(pb3cr, 0x00000000);
  48
  49         mtebc(pb4ap, 0x00000000);
  50         mtebc(pb4cr, 0x00000000);
  51
  52         mtebc(pb5ap, 0x00000000);
  53         mtebc(pb5cr, 0x00000000);
  54
  55         /*--------------------------------------------------------------------
  56          * Setup the interrupt controller polarities, triggers, etc.
  57          *-------------------------------------------------------------------*/
  58         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  59         mtdcr(uic0er, 0x00000000);      /* disable all */
  60         mtdcr(uic0cr, 0x00000009);      /* ATI & UIC1 crit are critical */
  61         mtdcr(uic0pr, 0xfffffe13);      /* per ref-board manual */
  62         mtdcr(uic0tr, 0x01c00008);      /* per ref-board manual */
  63         mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
  64         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  65
  66         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  67         mtdcr(uic1er, 0x00000000);      /* disable all */
  68         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
  69         mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
  70         mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
  71         mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
  72         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  73
  74         /*--------------------------------------------------------------------
  75          * Setup the GPIO pins
  76          *-------------------------------------------------------------------*/
  77         /*CPLD cs */
  78         /*setup Address lines for flash sizes larger than 16Meg. */
  79         out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
  80         out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
  81         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
  82
  83         /*setup emac */
  84         out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
  85         out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
  86         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
  87         out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
  88         out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
  89
  90         /*UART1 */
  91         out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
  92         out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
  93         out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
  94
  95         /*setup USB 2.0 */
  96         out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
  97         out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
  98         out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
  99         out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
 100         out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
 101
 102         /*--------------------------------------------------------------------
 103          * Setup other serial configuration
 104          *-------------------------------------------------------------------*/
 105         mfsdr(sdr_pci0, reg);
 106         mtsdr(sdr_pci0, 0x80000000 | reg);      /* PCI arbiter enabled */
 107         mtsdr(sdr_pfc0, 0x00003e00);    /* Pin function */
 108         mtsdr(sdr_pfc1, 0x00048000);    /* Pin function: UART0 has 4 pins */
 109
 110         /*clear tmrclk divisor */
 111         *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
 112
 113         /*enable ethernet */
 114         *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
 115
 116         /*enable usb 1.1 fs device and remove usb 2.0 reset */
 117         *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
 118
 119         /*get rid of flash write protect */
 120         *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
 121
 122         return 0;
 123 }
 124
 125 int checkboard(void)
 126 {
 127         sys_info_t sysinfo;
 128
 129         get_sys_info(&sysinfo);
 130
 131         printf("Board: AMCC YELLOWSTONE\n");
 132         printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
 133         printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
 134         printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
 135         printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
 136         printf("\tPER: %lu MHz\n", sysinfo.freqEPB / 1000000);
 137         printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
 138         return (0);
 139 }
 140
 141 /*************************************************************************
 142  *  sdram_init -- doesn't use serial presence detect.
 143  *
 144  *  Assumes:    256 MB, ECC, non-registered
 145  *              PLB @ 133 MHz
 146  *
 147  ************************************************************************/
 148 void sdram_init(void)
 149 {
 150         register uint reg;
 151
 152         /*--------------------------------------------------------------------
 153          * Setup some default
 154          *------------------------------------------------------------------*/
 155         mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default)             */
 156         mtsdram(mem_slio, 0x00000000);  /* rdre=0 wrre=0 rarw=0         */
 157         mtsdram(mem_devopt, 0x00000000);        /* dll=0 ds=0 (normal)          */
 158         mtsdram(mem_clktr, 0x40000000); /* ?? */
 159         mtsdram(mem_wddctr, 0x40000000);        /* ?? */
 160
 161         /*clear this first, if the DDR is enabled by a debugger
 162            then you can not make changes. */
 163         mtsdram(mem_cfg0, 0x00000000);  /* Disable EEC */
 164
 165         /*--------------------------------------------------------------------
 166          * Setup for board-specific specific mem
 167          *------------------------------------------------------------------*/
 168         /*
 169          * Following for CAS Latency = 2.5 @ 133 MHz PLB
 170          */
 171         mtsdram(mem_b0cr, 0x000a4001);  /* SDBA=0x000 128MB, Mode 3, enabled */
 172         mtsdram(mem_b1cr, 0x080a4001);  /* SDBA=0x080 128MB, Mode 3, enabled */
 173         mtsdram(mem_tr0, 0x410a4012);   /* ?? */
 174         mtsdram(mem_tr1, 0x8080080b);   /* ?? */
 175         mtsdram(mem_rtr, 0x04080000);   /* ?? */
 176         mtsdram(mem_cfg1, 0x00000000);  /* Self-refresh exit, disable PM    */
 177         mtsdram(mem_cfg0, 0x34000000);  /* Disable EEC */
 178         udelay(400);            /* Delay 200 usecs (min)            */
 179
 180         /*--------------------------------------------------------------------
 181          * Enable the controller, then wait for DCEN to complete
 182          *------------------------------------------------------------------*/
 183         mtsdram(mem_cfg0, 0x84000000);  /* Enable */
 184
 185         for (;;) {
 186                 mfsdram(mem_mcsts, reg);
 187                 if (reg & 0x80000000)
 188                         break;
 189         }
 190 }
 191
 192 /*************************************************************************
 193  *  long int initdram
 194  *
 195  ************************************************************************/
 196 long int initdram(int board)
 197 {
 198         sdram_init();
 199         return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024);     /* return bytes */
 200 }
 201
 202 #if defined(CFG_DRAM_TEST)
 203 int testdram(void)
 204 {
 205         unsigned long *mem = (unsigned long *)0;
 206         const unsigned long kend = (1024 / sizeof(unsigned long));
 207         unsigned long k, n;
 208
 209         mtmsr(0);
 210
 211         for (k = 0; k < CFG_KBYTES_SDRAM;
 212              ++k, mem += (1024 / sizeof(unsigned long))) {
 213                 if ((k & 1023) == 0) {
 214                         printf("%3d MB\r", k / 1024);
 215                 }
 216
 217                 memset(mem, 0xaaaaaaaa, 1024);
 218                 for (n = 0; n < kend; ++n) {
 219                         if (mem[n] != 0xaaaaaaaa) {
 220                                 printf("SDRAM test fails at: %08x\n",
 221                                        (uint) & mem[n]);
 222                                 return 1;
 223                         }
 224                 }
 225
 226                 memset(mem, 0x55555555, 1024);
 227                 for (n = 0; n < kend; ++n) {
 228                         if (mem[n] != 0x55555555) {
 229                                 printf("SDRAM test fails at: %08x\n",
 230                                        (uint) & mem[n]);
 231                                 return 1;
 232                         }
 233                 }
 234         }
 235         printf("SDRAM test passes\n");
 236         return 0;
 237 }
 238 #endif
 239
 240 /*************************************************************************
 241  *  pci_pre_init
 242  *
 243  *  This routine is called just prior to registering the hose and gives
 244  *  the board the opportunity to check things. Returning a value of zero
 245  *  indicates that things are bad & PCI initialization should be aborted.
 246  *
 247  *      Different boards may wish to customize the pci controller structure
 248  *      (add regions, override default access routines, etc) or perform
 249  *      certain pre-initialization actions.
 250  *
 251  ************************************************************************/
 252 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
 253 int pci_pre_init(struct pci_controller *hose)
 254 {
 255         unsigned long strap;
 256         unsigned long addr;
 257
 258         /*--------------------------------------------------------------------------+
 259      *  Bamboo is always configured as the host & requires the
 260      *  PCI arbiter to be enabled.
 261          *--------------------------------------------------------------------------*/
 262         mfsdr(sdr_sdstp1, strap);
 263         if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
 264                 printf("PCI: SDR0_STRP1[PAE] not set.\n");
 265                 printf("PCI: Configuration aborted.\n");
 266                 return 0;
 267         }
 268
 269     /*-------------------------------------------------------------------------+
 270     | Set priority for all PLB3 devices to 0.
 271     | Set PLB3 arbiter to fair mode.
 272     +-------------------------------------------------------------------------*/
 273         mfsdr(sdr_amp1, addr);
 274         mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
 275         addr = mfdcr(plb3_acr);
 276         mtdcr(plb3_acr, addr | 0x80000000);
 277
 278     /*-------------------------------------------------------------------------+
 279     | Set priority for all PLB4 devices to 0.
 280     +-------------------------------------------------------------------------*/
 281         mfsdr(sdr_amp0, addr);
 282         mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
 283         addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
 284         mtdcr(plb4_acr, addr);
 285
 286     /*-------------------------------------------------------------------------+
 287     | Set Nebula PLB4 arbiter to fair mode.
 288     +-------------------------------------------------------------------------*/
 289         /*  Segment0 */
 290         addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
 291         addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
 292         addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
 293         addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
 294         mtdcr(plb0_acr, addr);
 295
 296         /* Segment1 */
 297         addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
 298         addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
 299         addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
 300         addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
 301         mtdcr(plb1_acr, addr);
 302
 303         return 1;
 304 }
 305 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
 306
 307 /*************************************************************************
 308  *  pci_target_init
 309  *
 310  *      The bootstrap configuration provides default settings for the pci
 311  *      inbound map (PIM). But the bootstrap config choices are limited and
 312  *      may not be sufficient for a given board.
 313  *
 314  ************************************************************************/
 315 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 316 void pci_target_init(struct pci_controller *hose)
 317 {
 318         /*--------------------------------------------------------------------------+
 319          * Set up Direct MMIO registers
 320          *--------------------------------------------------------------------------*/
 321    /*--------------------------------------------------------------------------+
 322    | PowerPC440 EP PCI Master configuration.
 323    | Map one 1Gig range of PLB/processor addresses to PCI memory space.
 324    |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
 325    |   Use byte reversed out routines to handle endianess.
 326    | Make this region non-prefetchable.
 327    +--------------------------------------------------------------------------*/
 328         out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 329         out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
 330         out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);       /* PMM0 PCI Low Address */
 331         out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 332         out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 333
 334         out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 335         out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
 336         out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);      /* PMM0 PCI Low Address */
 337         out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 338         out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 339
 340         out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
 341         out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
 342         out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
 343         out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
 344
 345         /*--------------------------------------------------------------------------+
 346          * Set up Configuration registers
 347          *--------------------------------------------------------------------------*/
 348
 349         /* Program the board's subsystem id/vendor id */
 350         pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 351                               CFG_PCI_SUBSYS_VENDORID);
 352         pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
 353
 354         /* Configure command register as bus master */
 355         pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
 356
 357         /* 240nS PCI clock */
 358         pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
 359
 360         /* No error reporting */
 361         pci_write_config_word(0, PCI_ERREN, 0);
 362
 363         pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 364
 365 }
 366 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 367
 368 /*************************************************************************
 369  *  pci_master_init
 370  *
 371  ************************************************************************/
 372 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 373 void pci_master_init(struct pci_controller *hose)
 374 {
 375         unsigned short temp_short;
 376
 377    /*--------------------------------------------------------------------------+
 378    | Write the PowerPC440 EP PCI Configuration regs.
 379    |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 380    |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
 381    +--------------------------------------------------------------------------*/
 382         pci_read_config_word(0, PCI_COMMAND, &temp_short);
 383         pci_write_config_word(0, PCI_COMMAND,
 384                               temp_short | PCI_COMMAND_MASTER |
 385                               PCI_COMMAND_MEMORY);
 386 }
 387 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 388
 389 /*************************************************************************
 390  *  is_pci_host
 391  *
 392  *      This routine is called to determine if a pci scan should be
 393  *      performed. With various hardware environments (especially cPCI and
 394  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 395  *      bit in the strap register, or generic host/adapter assumptions.
 396  *
 397  *      Rather than hard-code a bad assumption in the general 440 code, the
 398  *      440 pci code requires the board to decide at runtime.
 399  *
 400  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 401  *
 402  *
 403  ************************************************************************/
 404 #if defined(CONFIG_PCI)
 405 int is_pci_host(struct pci_controller *hose)
 406 {
 407         /* Bamboo is always configured as host. */
 408         return (1);
 409 }
 410 #endif                          /* defined(CONFIG_PCI) */
 411
 412 /*************************************************************************
 413  *  hw_watchdog_reset
 414  *
 415  *      This routine is called to reset (keep alive) the watchdog timer
 416  *
 417  ************************************************************************/
 418 #if defined(CONFIG_HW_WATCHDOG)
 419 void hw_watchdog_reset(void)
 420 {
 421 }
 422 #endif